/drivers/net/ixgbe/ixgbe_dcb_82598.c
C | 338 lines | 183 code | 50 blank | 105 comment | 29 complexity | 9ae2ea8778dbb272fd5ea83773853525 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
1/******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2011 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27*******************************************************************************/ 28 29#include "ixgbe.h" 30#include "ixgbe_type.h" 31#include "ixgbe_dcb.h" 32#include "ixgbe_dcb_82598.h" 33 34/** 35 * ixgbe_dcb_config_packet_buffers_82598 - Configure packet buffers 36 * @hw: pointer to hardware structure 37 * @dcb_config: pointer to ixgbe_dcb_config structure 38 * 39 * Configure packet buffers for DCB mode. 40 */ 41static s32 ixgbe_dcb_config_packet_buffers_82598(struct ixgbe_hw *hw, u8 rx_pba) 42{ 43 s32 ret_val = 0; 44 u32 value = IXGBE_RXPBSIZE_64KB; 45 u8 i = 0; 46 47 /* Setup Rx packet buffer sizes */ 48 switch (rx_pba) { 49 case pba_80_48: 50 /* Setup the first four at 80KB */ 51 value = IXGBE_RXPBSIZE_80KB; 52 for (; i < 4; i++) 53 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), value); 54 /* Setup the last four at 48KB...don't re-init i */ 55 value = IXGBE_RXPBSIZE_48KB; 56 /* Fall Through */ 57 case pba_equal: 58 default: 59 for (; i < IXGBE_MAX_PACKET_BUFFERS; i++) 60 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), value); 61 62 /* Setup Tx packet buffer sizes */ 63 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) { 64 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 65 IXGBE_TXPBSIZE_40KB); 66 } 67 break; 68 } 69 70 return ret_val; 71} 72 73/** 74 * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter 75 * @hw: pointer to hardware structure 76 * @dcb_config: pointer to ixgbe_dcb_config structure 77 * 78 * Configure Rx Data Arbiter and credits for each traffic class. 79 */ 80s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, 81 u16 *refill, 82 u16 *max, 83 u8 *prio_type) 84{ 85 u32 reg = 0; 86 u32 credit_refill = 0; 87 u32 credit_max = 0; 88 u8 i = 0; 89 90 reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA; 91 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg); 92 93 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 94 /* Enable Arbiter */ 95 reg &= ~IXGBE_RMCS_ARBDIS; 96 /* Enable Receive Recycle within the BWG */ 97 reg |= IXGBE_RMCS_RRM; 98 /* Enable Deficit Fixed Priority arbitration*/ 99 reg |= IXGBE_RMCS_DFP; 100 101 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); 102 103 /* Configure traffic class credits and priority */ 104 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 105 credit_refill = refill[i]; 106 credit_max = max[i]; 107 108 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT); 109 110 if (prio_type[i] == prio_link) 111 reg |= IXGBE_RT2CR_LSP; 112 113 IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg); 114 } 115 116 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 117 reg |= IXGBE_RDRXCTL_RDMTS_1_2; 118 reg |= IXGBE_RDRXCTL_MPBEN; 119 reg |= IXGBE_RDRXCTL_MCEN; 120 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); 121 122 reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 123 /* Make sure there is enough descriptors before arbitration */ 124 reg &= ~IXGBE_RXCTRL_DMBYPS; 125 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg); 126 127 return 0; 128} 129 130/** 131 * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter 132 * @hw: pointer to hardware structure 133 * @dcb_config: pointer to ixgbe_dcb_config structure 134 * 135 * Configure Tx Descriptor Arbiter and credits for each traffic class. 136 */ 137s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw, 138 u16 *refill, 139 u16 *max, 140 u8 *bwg_id, 141 u8 *prio_type) 142{ 143 u32 reg, max_credits; 144 u8 i; 145 146 reg = IXGBE_READ_REG(hw, IXGBE_DPMCS); 147 148 /* Enable arbiter */ 149 reg &= ~IXGBE_DPMCS_ARBDIS; 150 /* Enable DFP and Recycle mode */ 151 reg |= (IXGBE_DPMCS_TDPAC | IXGBE_DPMCS_TRM); 152 reg |= IXGBE_DPMCS_TSOEF; 153 /* Configure Max TSO packet size 34KB including payload and headers */ 154 reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT); 155 156 IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg); 157 158 /* Configure traffic class credits and priority */ 159 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 160 max_credits = max[i]; 161 reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT; 162 reg |= refill[i]; 163 reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT; 164 165 if (prio_type[i] == prio_group) 166 reg |= IXGBE_TDTQ2TCCR_GSP; 167 168 if (prio_type[i] == prio_link) 169 reg |= IXGBE_TDTQ2TCCR_LSP; 170 171 IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg); 172 } 173 174 return 0; 175} 176 177/** 178 * ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter 179 * @hw: pointer to hardware structure 180 * @dcb_config: pointer to ixgbe_dcb_config structure 181 * 182 * Configure Tx Data Arbiter and credits for each traffic class. 183 */ 184s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw, 185 u16 *refill, 186 u16 *max, 187 u8 *bwg_id, 188 u8 *prio_type) 189{ 190 u32 reg; 191 u8 i; 192 193 reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS); 194 /* Enable Data Plane Arbiter */ 195 reg &= ~IXGBE_PDPMCS_ARBDIS; 196 /* Enable DFP and Transmit Recycle Mode */ 197 reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM); 198 199 IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg); 200 201 /* Configure traffic class credits and priority */ 202 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 203 reg = refill[i]; 204 reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT; 205 reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT; 206 207 if (prio_type[i] == prio_group) 208 reg |= IXGBE_TDPT2TCCR_GSP; 209 210 if (prio_type[i] == prio_link) 211 reg |= IXGBE_TDPT2TCCR_LSP; 212 213 IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg); 214 } 215 216 /* Enable Tx packet buffer division */ 217 reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL); 218 reg |= IXGBE_DTXCTL_ENDBUBD; 219 IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg); 220 221 return 0; 222} 223 224/** 225 * ixgbe_dcb_config_pfc_82598 - Config priority flow control 226 * @hw: pointer to hardware structure 227 * @dcb_config: pointer to ixgbe_dcb_config structure 228 * 229 * Configure Priority Flow Control for each traffic class. 230 */ 231s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en) 232{ 233 u32 reg, rx_pba_size; 234 u8 i; 235 236 if (pfc_en) { 237 /* Enable Transmit Priority Flow Control */ 238 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 239 reg &= ~IXGBE_RMCS_TFCE_802_3X; 240 /* correct the reporting of our flow control status */ 241 reg |= IXGBE_RMCS_TFCE_PRIORITY; 242 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); 243 244 /* Enable Receive Priority Flow Control */ 245 reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 246 reg &= ~IXGBE_FCTRL_RFCE; 247 reg |= IXGBE_FCTRL_RPFCE; 248 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg); 249 250 /* Configure pause time */ 251 for (i = 0; i < (MAX_TRAFFIC_CLASS >> 1); i++) 252 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), 0x68006800); 253 254 /* Configure flow control refresh threshold value */ 255 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, 0x3400); 256 } 257 258 /* 259 * Configure flow control thresholds and enable priority flow control 260 * for each traffic class. 261 */ 262 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 263 int enabled = pfc_en & (1 << i); 264 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)); 265 rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT; 266 reg = (rx_pba_size - hw->fc.low_water) << 10; 267 268 if (enabled == pfc_enabled_tx || 269 enabled == pfc_enabled_full) 270 reg |= IXGBE_FCRTL_XONE; 271 272 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), reg); 273 274 reg = (rx_pba_size - hw->fc.high_water) << 10; 275 if (enabled == pfc_enabled_tx || 276 enabled == pfc_enabled_full) 277 reg |= IXGBE_FCRTH_FCEN; 278 279 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg); 280 } 281 282 return 0; 283} 284 285/** 286 * ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics 287 * @hw: pointer to hardware structure 288 * 289 * Configure queue statistics registers, all queues belonging to same traffic 290 * class uses a single set of queue statistics counters. 291 */ 292static s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw) 293{ 294 u32 reg = 0; 295 u8 i = 0; 296 u8 j = 0; 297 298 /* Receive Queues stats setting - 8 queues per statistics reg */ 299 for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) { 300 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i)); 301 reg |= ((0x1010101) * j); 302 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg); 303 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1)); 304 reg |= ((0x1010101) * j); 305 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg); 306 } 307 /* Transmit Queues stats setting - 4 queues per statistics reg */ 308 for (i = 0; i < 8; i++) { 309 reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i)); 310 reg |= ((0x1010101) * i); 311 IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg); 312 } 313 314 return 0; 315} 316 317/** 318 * ixgbe_dcb_hw_config_82598 - Config and enable DCB 319 * @hw: pointer to hardware structure 320 * @dcb_config: pointer to ixgbe_dcb_config structure 321 * 322 * Configure dcb settings and enable dcb mode. 323 */ 324s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, 325 u8 rx_pba, u8 pfc_en, u16 *refill, 326 u16 *max, u8 *bwg_id, u8 *prio_type) 327{ 328 ixgbe_dcb_config_packet_buffers_82598(hw, rx_pba); 329 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, prio_type); 330 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, 331 bwg_id, prio_type); 332 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, 333 bwg_id, prio_type); 334 ixgbe_dcb_config_pfc_82598(hw, pfc_en); 335 ixgbe_dcb_config_tc_stats_82598(hw); 336 337 return 0; 338}