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/drivers/net/igbvf/regs.h

https://bitbucket.org/ndreys/linux-sunxi
C++ Header | 108 lines | 65 code | 6 blank | 37 comment | 0 complexity | 4976387a8245e02614e96e658db4f9dc MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1/*******************************************************************************
  2
  3  Intel(R) 82576 Virtual Function Linux driver
  4  Copyright(c) 2009 - 2010 Intel Corporation.
  5
  6  This program is free software; you can redistribute it and/or modify it
  7  under the terms and conditions of the GNU General Public License,
  8  version 2, as published by the Free Software Foundation.
  9
 10  This program is distributed in the hope it will be useful, but WITHOUT
 11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 12  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 13  more details.
 14
 15  You should have received a copy of the GNU General Public License along with
 16  this program; if not, write to the Free Software Foundation, Inc.,
 17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 18
 19  The full GNU General Public License is included in this distribution in
 20  the file called "COPYING".
 21
 22  Contact Information:
 23  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
 24  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 25
 26*******************************************************************************/
 27
 28#ifndef _E1000_REGS_H_
 29#define _E1000_REGS_H_
 30
 31#define E1000_CTRL      0x00000 /* Device Control - RW */
 32#define E1000_STATUS    0x00008 /* Device Status - RO */
 33#define E1000_ITR       0x000C4 /* Interrupt Throttling Rate - RW */
 34#define E1000_EICR      0x01580 /* Ext. Interrupt Cause Read - R/clr */
 35#define E1000_EITR(_n)  (0x01680 + (0x4 * (_n)))
 36#define E1000_EICS      0x01520 /* Ext. Interrupt Cause Set - W0 */
 37#define E1000_EIMS      0x01524 /* Ext. Interrupt Mask Set/Read - RW */
 38#define E1000_EIMC      0x01528 /* Ext. Interrupt Mask Clear - WO */
 39#define E1000_EIAC      0x0152C /* Ext. Interrupt Auto Clear - RW */
 40#define E1000_EIAM      0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
 41#define E1000_IVAR0     0x01700 /* Interrupt Vector Allocation (array) - RW */
 42#define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
 43/*
 44 * Convenience macros
 45 *
 46 * Note: "_n" is the queue number of the register to be written to.
 47 *
 48 * Example usage:
 49 * E1000_RDBAL_REG(current_rx_queue)
 50 */
 51#define E1000_RDBAL(_n)      ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \
 52                                         (0x0C000 + ((_n) * 0x40)))
 53#define E1000_RDBAH(_n)      ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \
 54                                         (0x0C004 + ((_n) * 0x40)))
 55#define E1000_RDLEN(_n)      ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \
 56                                         (0x0C008 + ((_n) * 0x40)))
 57#define E1000_SRRCTL(_n)     ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \
 58                                         (0x0C00C + ((_n) * 0x40)))
 59#define E1000_RDH(_n)        ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \
 60                                         (0x0C010 + ((_n) * 0x40)))
 61#define E1000_RDT(_n)        ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \
 62                                         (0x0C018 + ((_n) * 0x40)))
 63#define E1000_RXDCTL(_n)     ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \
 64                                         (0x0C028 + ((_n) * 0x40)))
 65#define E1000_TDBAL(_n)      ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \
 66                                         (0x0E000 + ((_n) * 0x40)))
 67#define E1000_TDBAH(_n)      ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \
 68                                         (0x0E004 + ((_n) * 0x40)))
 69#define E1000_TDLEN(_n)      ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \
 70                                         (0x0E008 + ((_n) * 0x40)))
 71#define E1000_TDH(_n)        ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \
 72                                         (0x0E010 + ((_n) * 0x40)))
 73#define E1000_TDT(_n)        ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \
 74                                         (0x0E018 + ((_n) * 0x40)))
 75#define E1000_TXDCTL(_n)     ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \
 76                                         (0x0E028 + ((_n) * 0x40)))
 77#define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8))
 78#define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8))
 79#define E1000_RAL(_i)  (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
 80                                       (0x054E0 + ((_i - 16) * 8)))
 81#define E1000_RAH(_i)  (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
 82                                       (0x054E4 + ((_i - 16) * 8)))
 83
 84/* Statistics registers */
 85#define E1000_VFGPRC    0x00F10
 86#define E1000_VFGORC    0x00F18
 87#define E1000_VFMPRC    0x00F3C
 88#define E1000_VFGPTC    0x00F14
 89#define E1000_VFGOTC    0x00F34
 90#define E1000_VFGOTLBC  0x00F50
 91#define E1000_VFGPTLBC  0x00F44
 92#define E1000_VFGORLBC  0x00F48
 93#define E1000_VFGPRLBC  0x00F40
 94
 95/* These act per VF so an array friendly macro is used */
 96#define E1000_V2PMAILBOX(_n)   (0x00C40 + (4 * (_n)))
 97#define E1000_VMBMEM(_n)       (0x00800 + (64 * (_n)))
 98
 99/* Define macros for handling registers */
100#define er32(reg) readl(hw->hw_addr + E1000_##reg)
101#define ew32(reg, val) writel((val), hw->hw_addr +  E1000_##reg)
102#define array_er32(reg, offset) \
103	readl(hw->hw_addr + E1000_##reg + (offset << 2))
104#define array_ew32(reg, offset, val) \
105	writel((val), hw->hw_addr +  E1000_##reg + (offset << 2))
106#define e1e_flush() er32(STATUS)
107
108#endif