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/drivers/net/igb/e1000_hw.h

https://bitbucket.org/ndreys/linux-sunxi
C++ Header | 529 lines | 430 code | 68 blank | 31 comment | 0 complexity | 376c6f75b703e41696e6922889737cd1 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1/*******************************************************************************
  2
  3  Intel(R) Gigabit Ethernet Linux driver
  4  Copyright(c) 2007-2009 Intel Corporation.
  5
  6  This program is free software; you can redistribute it and/or modify it
  7  under the terms and conditions of the GNU General Public License,
  8  version 2, as published by the Free Software Foundation.
  9
 10  This program is distributed in the hope it will be useful, but WITHOUT
 11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 12  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 13  more details.
 14
 15  You should have received a copy of the GNU General Public License along with
 16  this program; if not, write to the Free Software Foundation, Inc.,
 17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 18
 19  The full GNU General Public License is included in this distribution in
 20  the file called "COPYING".
 21
 22  Contact Information:
 23  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
 24  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 25
 26*******************************************************************************/
 27
 28#ifndef _E1000_HW_H_
 29#define _E1000_HW_H_
 30
 31#include <linux/types.h>
 32#include <linux/delay.h>
 33#include <linux/io.h>
 34#include <linux/netdevice.h>
 35
 36#include "e1000_regs.h"
 37#include "e1000_defines.h"
 38
 39struct e1000_hw;
 40
 41#define E1000_DEV_ID_82576                    0x10C9
 42#define E1000_DEV_ID_82576_FIBER              0x10E6
 43#define E1000_DEV_ID_82576_SERDES             0x10E7
 44#define E1000_DEV_ID_82576_QUAD_COPPER        0x10E8
 45#define E1000_DEV_ID_82576_QUAD_COPPER_ET2    0x1526
 46#define E1000_DEV_ID_82576_NS                 0x150A
 47#define E1000_DEV_ID_82576_NS_SERDES          0x1518
 48#define E1000_DEV_ID_82576_SERDES_QUAD        0x150D
 49#define E1000_DEV_ID_82575EB_COPPER           0x10A7
 50#define E1000_DEV_ID_82575EB_FIBER_SERDES     0x10A9
 51#define E1000_DEV_ID_82575GB_QUAD_COPPER      0x10D6
 52#define E1000_DEV_ID_82580_COPPER             0x150E
 53#define E1000_DEV_ID_82580_FIBER              0x150F
 54#define E1000_DEV_ID_82580_SERDES             0x1510
 55#define E1000_DEV_ID_82580_SGMII              0x1511
 56#define E1000_DEV_ID_82580_COPPER_DUAL        0x1516
 57#define E1000_DEV_ID_82580_QUAD_FIBER         0x1527
 58#define E1000_DEV_ID_DH89XXCC_SGMII           0x0438
 59#define E1000_DEV_ID_DH89XXCC_SERDES          0x043A
 60#define E1000_DEV_ID_DH89XXCC_BACKPLANE       0x043C
 61#define E1000_DEV_ID_DH89XXCC_SFP             0x0440
 62#define E1000_DEV_ID_I350_COPPER              0x1521
 63#define E1000_DEV_ID_I350_FIBER               0x1522
 64#define E1000_DEV_ID_I350_SERDES              0x1523
 65#define E1000_DEV_ID_I350_SGMII               0x1524
 66
 67#define E1000_REVISION_2 2
 68#define E1000_REVISION_4 4
 69
 70#define E1000_FUNC_0     0
 71#define E1000_FUNC_1     1
 72#define E1000_FUNC_2     2
 73#define E1000_FUNC_3     3
 74
 75#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
 76#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
 77#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2   6
 78#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3   9
 79
 80enum e1000_mac_type {
 81	e1000_undefined = 0,
 82	e1000_82575,
 83	e1000_82576,
 84	e1000_82580,
 85	e1000_i350,
 86	e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
 87};
 88
 89enum e1000_media_type {
 90	e1000_media_type_unknown = 0,
 91	e1000_media_type_copper = 1,
 92	e1000_media_type_internal_serdes = 2,
 93	e1000_num_media_types
 94};
 95
 96enum e1000_nvm_type {
 97	e1000_nvm_unknown = 0,
 98	e1000_nvm_none,
 99	e1000_nvm_eeprom_spi,
100	e1000_nvm_flash_hw,
101	e1000_nvm_flash_sw
102};
103
104enum e1000_nvm_override {
105	e1000_nvm_override_none = 0,
106	e1000_nvm_override_spi_small,
107	e1000_nvm_override_spi_large,
108};
109
110enum e1000_phy_type {
111	e1000_phy_unknown = 0,
112	e1000_phy_none,
113	e1000_phy_m88,
114	e1000_phy_igp,
115	e1000_phy_igp_2,
116	e1000_phy_gg82563,
117	e1000_phy_igp_3,
118	e1000_phy_ife,
119	e1000_phy_82580,
120};
121
122enum e1000_bus_type {
123	e1000_bus_type_unknown = 0,
124	e1000_bus_type_pci,
125	e1000_bus_type_pcix,
126	e1000_bus_type_pci_express,
127	e1000_bus_type_reserved
128};
129
130enum e1000_bus_speed {
131	e1000_bus_speed_unknown = 0,
132	e1000_bus_speed_33,
133	e1000_bus_speed_66,
134	e1000_bus_speed_100,
135	e1000_bus_speed_120,
136	e1000_bus_speed_133,
137	e1000_bus_speed_2500,
138	e1000_bus_speed_5000,
139	e1000_bus_speed_reserved
140};
141
142enum e1000_bus_width {
143	e1000_bus_width_unknown = 0,
144	e1000_bus_width_pcie_x1,
145	e1000_bus_width_pcie_x2,
146	e1000_bus_width_pcie_x4 = 4,
147	e1000_bus_width_pcie_x8 = 8,
148	e1000_bus_width_32,
149	e1000_bus_width_64,
150	e1000_bus_width_reserved
151};
152
153enum e1000_1000t_rx_status {
154	e1000_1000t_rx_status_not_ok = 0,
155	e1000_1000t_rx_status_ok,
156	e1000_1000t_rx_status_undefined = 0xFF
157};
158
159enum e1000_rev_polarity {
160	e1000_rev_polarity_normal = 0,
161	e1000_rev_polarity_reversed,
162	e1000_rev_polarity_undefined = 0xFF
163};
164
165enum e1000_fc_mode {
166	e1000_fc_none = 0,
167	e1000_fc_rx_pause,
168	e1000_fc_tx_pause,
169	e1000_fc_full,
170	e1000_fc_default = 0xFF
171};
172
173/* Statistics counters collected by the MAC */
174struct e1000_hw_stats {
175	u64 crcerrs;
176	u64 algnerrc;
177	u64 symerrs;
178	u64 rxerrc;
179	u64 mpc;
180	u64 scc;
181	u64 ecol;
182	u64 mcc;
183	u64 latecol;
184	u64 colc;
185	u64 dc;
186	u64 tncrs;
187	u64 sec;
188	u64 cexterr;
189	u64 rlec;
190	u64 xonrxc;
191	u64 xontxc;
192	u64 xoffrxc;
193	u64 xofftxc;
194	u64 fcruc;
195	u64 prc64;
196	u64 prc127;
197	u64 prc255;
198	u64 prc511;
199	u64 prc1023;
200	u64 prc1522;
201	u64 gprc;
202	u64 bprc;
203	u64 mprc;
204	u64 gptc;
205	u64 gorc;
206	u64 gotc;
207	u64 rnbc;
208	u64 ruc;
209	u64 rfc;
210	u64 roc;
211	u64 rjc;
212	u64 mgprc;
213	u64 mgpdc;
214	u64 mgptc;
215	u64 tor;
216	u64 tot;
217	u64 tpr;
218	u64 tpt;
219	u64 ptc64;
220	u64 ptc127;
221	u64 ptc255;
222	u64 ptc511;
223	u64 ptc1023;
224	u64 ptc1522;
225	u64 mptc;
226	u64 bptc;
227	u64 tsctc;
228	u64 tsctfc;
229	u64 iac;
230	u64 icrxptc;
231	u64 icrxatc;
232	u64 ictxptc;
233	u64 ictxatc;
234	u64 ictxqec;
235	u64 ictxqmtc;
236	u64 icrxdmtc;
237	u64 icrxoc;
238	u64 cbtmpc;
239	u64 htdpmc;
240	u64 cbrdpc;
241	u64 cbrmpc;
242	u64 rpthc;
243	u64 hgptc;
244	u64 htcbdpc;
245	u64 hgorc;
246	u64 hgotc;
247	u64 lenerrs;
248	u64 scvpc;
249	u64 hrmpc;
250	u64 doosync;
251	u64 o2bgptc;
252	u64 o2bspc;
253	u64 b2ospc;
254	u64 b2ogprc;
255};
256
257struct e1000_phy_stats {
258	u32 idle_errors;
259	u32 receive_errors;
260};
261
262struct e1000_host_mng_dhcp_cookie {
263	u32 signature;
264	u8  status;
265	u8  reserved0;
266	u16 vlan_id;
267	u32 reserved1;
268	u16 reserved2;
269	u8  reserved3;
270	u8  checksum;
271};
272
273/* Host Interface "Rev 1" */
274struct e1000_host_command_header {
275	u8 command_id;
276	u8 command_length;
277	u8 command_options;
278	u8 checksum;
279};
280
281#define E1000_HI_MAX_DATA_LENGTH     252
282struct e1000_host_command_info {
283	struct e1000_host_command_header command_header;
284	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
285};
286
287/* Host Interface "Rev 2" */
288struct e1000_host_mng_command_header {
289	u8  command_id;
290	u8  checksum;
291	u16 reserved1;
292	u16 reserved2;
293	u16 command_length;
294};
295
296#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
297struct e1000_host_mng_command_info {
298	struct e1000_host_mng_command_header command_header;
299	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
300};
301
302#include "e1000_mac.h"
303#include "e1000_phy.h"
304#include "e1000_nvm.h"
305#include "e1000_mbx.h"
306
307struct e1000_mac_operations {
308	s32  (*check_for_link)(struct e1000_hw *);
309	s32  (*reset_hw)(struct e1000_hw *);
310	s32  (*init_hw)(struct e1000_hw *);
311	bool (*check_mng_mode)(struct e1000_hw *);
312	s32  (*setup_physical_interface)(struct e1000_hw *);
313	void (*rar_set)(struct e1000_hw *, u8 *, u32);
314	s32  (*read_mac_addr)(struct e1000_hw *);
315	s32  (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *);
316};
317
318struct e1000_phy_operations {
319	s32  (*acquire)(struct e1000_hw *);
320	s32  (*check_polarity)(struct e1000_hw *);
321	s32  (*check_reset_block)(struct e1000_hw *);
322	s32  (*force_speed_duplex)(struct e1000_hw *);
323	s32  (*get_cfg_done)(struct e1000_hw *hw);
324	s32  (*get_cable_length)(struct e1000_hw *);
325	s32  (*get_phy_info)(struct e1000_hw *);
326	s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
327	void (*release)(struct e1000_hw *);
328	s32  (*reset)(struct e1000_hw *);
329	s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
330	s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
331	s32  (*write_reg)(struct e1000_hw *, u32, u16);
332};
333
334struct e1000_nvm_operations {
335	s32  (*acquire)(struct e1000_hw *);
336	s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
337	void (*release)(struct e1000_hw *);
338	s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
339	s32  (*update)(struct e1000_hw *);
340	s32  (*validate)(struct e1000_hw *);
341};
342
343struct e1000_info {
344	s32 (*get_invariants)(struct e1000_hw *);
345	struct e1000_mac_operations *mac_ops;
346	struct e1000_phy_operations *phy_ops;
347	struct e1000_nvm_operations *nvm_ops;
348};
349
350extern const struct e1000_info e1000_82575_info;
351
352struct e1000_mac_info {
353	struct e1000_mac_operations ops;
354
355	u8 addr[6];
356	u8 perm_addr[6];
357
358	enum e1000_mac_type type;
359
360	u32 ledctl_default;
361	u32 ledctl_mode1;
362	u32 ledctl_mode2;
363	u32 mc_filter_type;
364	u32 txcw;
365
366	u16 mta_reg_count;
367	u16 uta_reg_count;
368
369	/* Maximum size of the MTA register table in all supported adapters */
370	#define MAX_MTA_REG 128
371	u32 mta_shadow[MAX_MTA_REG];
372	u16 rar_entry_count;
373
374	u8  forced_speed_duplex;
375
376	bool adaptive_ifs;
377	bool arc_subsystem_valid;
378	bool asf_firmware_present;
379	bool autoneg;
380	bool autoneg_failed;
381	bool disable_hw_init_bits;
382	bool get_link_status;
383	bool ifs_params_forced;
384	bool in_ifs_mode;
385	bool report_tx_early;
386	bool serdes_has_link;
387	bool tx_pkt_filtering;
388};
389
390struct e1000_phy_info {
391	struct e1000_phy_operations ops;
392
393	enum e1000_phy_type type;
394
395	enum e1000_1000t_rx_status local_rx;
396	enum e1000_1000t_rx_status remote_rx;
397	enum e1000_ms_type ms_type;
398	enum e1000_ms_type original_ms_type;
399	enum e1000_rev_polarity cable_polarity;
400	enum e1000_smart_speed smart_speed;
401
402	u32 addr;
403	u32 id;
404	u32 reset_delay_us; /* in usec */
405	u32 revision;
406
407	enum e1000_media_type media_type;
408
409	u16 autoneg_advertised;
410	u16 autoneg_mask;
411	u16 cable_length;
412	u16 max_cable_length;
413	u16 min_cable_length;
414
415	u8 mdix;
416
417	bool disable_polarity_correction;
418	bool is_mdix;
419	bool polarity_correction;
420	bool reset_disable;
421	bool speed_downgraded;
422	bool autoneg_wait_to_complete;
423};
424
425struct e1000_nvm_info {
426	struct e1000_nvm_operations ops;
427	enum e1000_nvm_type type;
428	enum e1000_nvm_override override;
429
430	u32 flash_bank_size;
431	u32 flash_base_addr;
432
433	u16 word_size;
434	u16 delay_usec;
435	u16 address_bits;
436	u16 opcode_bits;
437	u16 page_size;
438};
439
440struct e1000_bus_info {
441	enum e1000_bus_type type;
442	enum e1000_bus_speed speed;
443	enum e1000_bus_width width;
444
445	u32 snoop;
446
447	u16 func;
448	u16 pci_cmd_word;
449};
450
451struct e1000_fc_info {
452	u32 high_water;     /* Flow control high-water mark */
453	u32 low_water;      /* Flow control low-water mark */
454	u16 pause_time;     /* Flow control pause timer */
455	bool send_xon;      /* Flow control send XON */
456	bool strict_ieee;   /* Strict IEEE mode */
457	enum e1000_fc_mode current_mode; /* Type of flow control */
458	enum e1000_fc_mode requested_mode;
459};
460
461struct e1000_mbx_operations {
462	s32 (*init_params)(struct e1000_hw *hw);
463	s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
464	s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
465	s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
466	s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
467	s32 (*check_for_msg)(struct e1000_hw *, u16);
468	s32 (*check_for_ack)(struct e1000_hw *, u16);
469	s32 (*check_for_rst)(struct e1000_hw *, u16);
470};
471
472struct e1000_mbx_stats {
473	u32 msgs_tx;
474	u32 msgs_rx;
475
476	u32 acks;
477	u32 reqs;
478	u32 rsts;
479};
480
481struct e1000_mbx_info {
482	struct e1000_mbx_operations ops;
483	struct e1000_mbx_stats stats;
484	u32 timeout;
485	u32 usec_delay;
486	u16 size;
487};
488
489struct e1000_dev_spec_82575 {
490	bool sgmii_active;
491	bool global_device_reset;
492	bool eee_disable;
493};
494
495struct e1000_hw {
496	void *back;
497
498	u8 __iomem *hw_addr;
499	u8 __iomem *flash_address;
500	unsigned long io_base;
501
502	struct e1000_mac_info  mac;
503	struct e1000_fc_info   fc;
504	struct e1000_phy_info  phy;
505	struct e1000_nvm_info  nvm;
506	struct e1000_bus_info  bus;
507	struct e1000_mbx_info mbx;
508	struct e1000_host_mng_dhcp_cookie mng_cookie;
509
510	union {
511		struct e1000_dev_spec_82575	_82575;
512	} dev_spec;
513
514	u16 device_id;
515	u16 subsystem_vendor_id;
516	u16 subsystem_device_id;
517	u16 vendor_id;
518
519	u8  revision_id;
520};
521
522extern struct net_device *igb_get_hw_dev(struct e1000_hw *hw);
523#define hw_dbg(format, arg...) \
524	netdev_dbg(igb_get_hw_dev(hw), format, ##arg)
525
526/* These functions must be implemented by drivers */
527s32  igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
528s32  igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
529#endif /* _E1000_HW_H_ */