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/drivers/net/atlx/atl1.c

https://bitbucket.org/ndreys/linux-sunxi
C | 3672 lines | 2659 code | 457 blank | 556 comment | 389 complexity | 75b6eb1456f287e935808b55aad80592 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0

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   1/*
   2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
   3 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
   4 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
   5 *
   6 * Derived from Intel e1000 driver
   7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
   8 *
   9 * This program is free software; you can redistribute it and/or modify it
  10 * under the terms of the GNU General Public License as published by the Free
  11 * Software Foundation; either version 2 of the License, or (at your option)
  12 * any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful, but WITHOUT
  15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17 * more details.
  18 *
  19 * You should have received a copy of the GNU General Public License along with
  20 * this program; if not, write to the Free Software Foundation, Inc., 59
  21 * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  22 *
  23 * The full GNU General Public License is included in this distribution in the
  24 * file called COPYING.
  25 *
  26 * Contact Information:
  27 * Xiong Huang <xiong.huang@atheros.com>
  28 * Jie Yang <jie.yang@atheros.com>
  29 * Chris Snook <csnook@redhat.com>
  30 * Jay Cliburn <jcliburn@gmail.com>
  31 *
  32 * This version is adapted from the Attansic reference driver.
  33 *
  34 * TODO:
  35 * Add more ethtool functions.
  36 * Fix abstruse irq enable/disable condition described here:
  37 *	http://marc.theaimsgroup.com/?l=linux-netdev&m=116398508500553&w=2
  38 *
  39 * NEEDS TESTING:
  40 * VLAN
  41 * multicast
  42 * promiscuous mode
  43 * interrupt coalescing
  44 * SMP torture testing
  45 */
  46
  47#include <asm/atomic.h>
  48#include <asm/byteorder.h>
  49
  50#include <linux/compiler.h>
  51#include <linux/crc32.h>
  52#include <linux/delay.h>
  53#include <linux/dma-mapping.h>
  54#include <linux/etherdevice.h>
  55#include <linux/hardirq.h>
  56#include <linux/if_ether.h>
  57#include <linux/if_vlan.h>
  58#include <linux/in.h>
  59#include <linux/interrupt.h>
  60#include <linux/ip.h>
  61#include <linux/irqflags.h>
  62#include <linux/irqreturn.h>
  63#include <linux/jiffies.h>
  64#include <linux/mii.h>
  65#include <linux/module.h>
  66#include <linux/moduleparam.h>
  67#include <linux/net.h>
  68#include <linux/netdevice.h>
  69#include <linux/pci.h>
  70#include <linux/pci_ids.h>
  71#include <linux/pm.h>
  72#include <linux/skbuff.h>
  73#include <linux/slab.h>
  74#include <linux/spinlock.h>
  75#include <linux/string.h>
  76#include <linux/tcp.h>
  77#include <linux/timer.h>
  78#include <linux/types.h>
  79#include <linux/workqueue.h>
  80
  81#include <net/checksum.h>
  82
  83#include "atl1.h"
  84
  85#define ATLX_DRIVER_VERSION "2.1.3"
  86MODULE_AUTHOR("Xiong Huang <xiong.huang@atheros.com>, "
  87	      "Chris Snook <csnook@redhat.com>, "
  88	      "Jay Cliburn <jcliburn@gmail.com>");
  89MODULE_LICENSE("GPL");
  90MODULE_VERSION(ATLX_DRIVER_VERSION);
  91
  92/* Temporary hack for merging atl1 and atl2 */
  93#include "atlx.c"
  94
  95static const struct ethtool_ops atl1_ethtool_ops;
  96
  97/*
  98 * This is the only thing that needs to be changed to adjust the
  99 * maximum number of ports that the driver can manage.
 100 */
 101#define ATL1_MAX_NIC 4
 102
 103#define OPTION_UNSET    -1
 104#define OPTION_DISABLED 0
 105#define OPTION_ENABLED  1
 106
 107#define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET }
 108
 109/*
 110 * Interrupt Moderate Timer in units of 2 us
 111 *
 112 * Valid Range: 10-65535
 113 *
 114 * Default Value: 100 (200us)
 115 */
 116static int __devinitdata int_mod_timer[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
 117static unsigned int num_int_mod_timer;
 118module_param_array_named(int_mod_timer, int_mod_timer, int,
 119	&num_int_mod_timer, 0);
 120MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer");
 121
 122#define DEFAULT_INT_MOD_CNT	100	/* 200us */
 123#define MAX_INT_MOD_CNT		65000
 124#define MIN_INT_MOD_CNT		50
 125
 126struct atl1_option {
 127	enum { enable_option, range_option, list_option } type;
 128	char *name;
 129	char *err;
 130	int def;
 131	union {
 132		struct {	/* range_option info */
 133			int min;
 134			int max;
 135		} r;
 136		struct {	/* list_option info */
 137			int nr;
 138			struct atl1_opt_list {
 139				int i;
 140				char *str;
 141			} *p;
 142		} l;
 143	} arg;
 144};
 145
 146static int __devinit atl1_validate_option(int *value, struct atl1_option *opt,
 147	struct pci_dev *pdev)
 148{
 149	if (*value == OPTION_UNSET) {
 150		*value = opt->def;
 151		return 0;
 152	}
 153
 154	switch (opt->type) {
 155	case enable_option:
 156		switch (*value) {
 157		case OPTION_ENABLED:
 158			dev_info(&pdev->dev, "%s enabled\n", opt->name);
 159			return 0;
 160		case OPTION_DISABLED:
 161			dev_info(&pdev->dev, "%s disabled\n", opt->name);
 162			return 0;
 163		}
 164		break;
 165	case range_option:
 166		if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
 167			dev_info(&pdev->dev, "%s set to %i\n", opt->name,
 168				*value);
 169			return 0;
 170		}
 171		break;
 172	case list_option:{
 173			int i;
 174			struct atl1_opt_list *ent;
 175
 176			for (i = 0; i < opt->arg.l.nr; i++) {
 177				ent = &opt->arg.l.p[i];
 178				if (*value == ent->i) {
 179					if (ent->str[0] != '\0')
 180						dev_info(&pdev->dev, "%s\n",
 181							ent->str);
 182					return 0;
 183				}
 184			}
 185		}
 186		break;
 187
 188	default:
 189		break;
 190	}
 191
 192	dev_info(&pdev->dev, "invalid %s specified (%i) %s\n",
 193		opt->name, *value, opt->err);
 194	*value = opt->def;
 195	return -1;
 196}
 197
 198/*
 199 * atl1_check_options - Range Checking for Command Line Parameters
 200 * @adapter: board private structure
 201 *
 202 * This routine checks all command line parameters for valid user
 203 * input.  If an invalid value is given, or if no user specified
 204 * value exists, a default value is used.  The final value is stored
 205 * in a variable in the adapter structure.
 206 */
 207static void __devinit atl1_check_options(struct atl1_adapter *adapter)
 208{
 209	struct pci_dev *pdev = adapter->pdev;
 210	int bd = adapter->bd_number;
 211	if (bd >= ATL1_MAX_NIC) {
 212		dev_notice(&pdev->dev, "no configuration for board#%i\n", bd);
 213		dev_notice(&pdev->dev, "using defaults for all values\n");
 214	}
 215	{			/* Interrupt Moderate Timer */
 216		struct atl1_option opt = {
 217			.type = range_option,
 218			.name = "Interrupt Moderator Timer",
 219			.err = "using default of "
 220				__MODULE_STRING(DEFAULT_INT_MOD_CNT),
 221			.def = DEFAULT_INT_MOD_CNT,
 222			.arg = {.r = {.min = MIN_INT_MOD_CNT,
 223					.max = MAX_INT_MOD_CNT} }
 224		};
 225		int val;
 226		if (num_int_mod_timer > bd) {
 227			val = int_mod_timer[bd];
 228			atl1_validate_option(&val, &opt, pdev);
 229			adapter->imt = (u16) val;
 230		} else
 231			adapter->imt = (u16) (opt.def);
 232	}
 233}
 234
 235/*
 236 * atl1_pci_tbl - PCI Device ID Table
 237 */
 238static DEFINE_PCI_DEVICE_TABLE(atl1_pci_tbl) = {
 239	{PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1)},
 240	/* required last entry */
 241	{0,}
 242};
 243MODULE_DEVICE_TABLE(pci, atl1_pci_tbl);
 244
 245static const u32 atl1_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
 246	NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
 247
 248static int debug = -1;
 249module_param(debug, int, 0);
 250MODULE_PARM_DESC(debug, "Message level (0=none,...,16=all)");
 251
 252/*
 253 * Reset the transmit and receive units; mask and clear all interrupts.
 254 * hw - Struct containing variables accessed by shared code
 255 * return : 0  or  idle status (if error)
 256 */
 257static s32 atl1_reset_hw(struct atl1_hw *hw)
 258{
 259	struct pci_dev *pdev = hw->back->pdev;
 260	struct atl1_adapter *adapter = hw->back;
 261	u32 icr;
 262	int i;
 263
 264	/*
 265	 * Clear Interrupt mask to stop board from generating
 266	 * interrupts & Clear any pending interrupt events
 267	 */
 268	/*
 269	 * iowrite32(0, hw->hw_addr + REG_IMR);
 270	 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
 271	 */
 272
 273	/*
 274	 * Issue Soft Reset to the MAC.  This will reset the chip's
 275	 * transmit, receive, DMA.  It will not effect
 276	 * the current PCI configuration.  The global reset bit is self-
 277	 * clearing, and should clear within a microsecond.
 278	 */
 279	iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
 280	ioread32(hw->hw_addr + REG_MASTER_CTRL);
 281
 282	iowrite16(1, hw->hw_addr + REG_PHY_ENABLE);
 283	ioread16(hw->hw_addr + REG_PHY_ENABLE);
 284
 285	/* delay about 1ms */
 286	msleep(1);
 287
 288	/* Wait at least 10ms for All module to be Idle */
 289	for (i = 0; i < 10; i++) {
 290		icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
 291		if (!icr)
 292			break;
 293		/* delay 1 ms */
 294		msleep(1);
 295		/* FIXME: still the right way to do this? */
 296		cpu_relax();
 297	}
 298
 299	if (icr) {
 300		if (netif_msg_hw(adapter))
 301			dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr);
 302		return icr;
 303	}
 304
 305	return 0;
 306}
 307
 308/* function about EEPROM
 309 *
 310 * check_eeprom_exist
 311 * return 0 if eeprom exist
 312 */
 313static int atl1_check_eeprom_exist(struct atl1_hw *hw)
 314{
 315	u32 value;
 316	value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
 317	if (value & SPI_FLASH_CTRL_EN_VPD) {
 318		value &= ~SPI_FLASH_CTRL_EN_VPD;
 319		iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
 320	}
 321
 322	value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
 323	return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
 324}
 325
 326static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
 327{
 328	int i;
 329	u32 control;
 330
 331	if (offset & 3)
 332		/* address do not align */
 333		return false;
 334
 335	iowrite32(0, hw->hw_addr + REG_VPD_DATA);
 336	control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
 337	iowrite32(control, hw->hw_addr + REG_VPD_CAP);
 338	ioread32(hw->hw_addr + REG_VPD_CAP);
 339
 340	for (i = 0; i < 10; i++) {
 341		msleep(2);
 342		control = ioread32(hw->hw_addr + REG_VPD_CAP);
 343		if (control & VPD_CAP_VPD_FLAG)
 344			break;
 345	}
 346	if (control & VPD_CAP_VPD_FLAG) {
 347		*p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
 348		return true;
 349	}
 350	/* timeout */
 351	return false;
 352}
 353
 354/*
 355 * Reads the value from a PHY register
 356 * hw - Struct containing variables accessed by shared code
 357 * reg_addr - address of the PHY register to read
 358 */
 359static s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
 360{
 361	u32 val;
 362	int i;
 363
 364	val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
 365		MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
 366		MDIO_CLK_SEL_SHIFT;
 367	iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
 368	ioread32(hw->hw_addr + REG_MDIO_CTRL);
 369
 370	for (i = 0; i < MDIO_WAIT_TIMES; i++) {
 371		udelay(2);
 372		val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
 373		if (!(val & (MDIO_START | MDIO_BUSY)))
 374			break;
 375	}
 376	if (!(val & (MDIO_START | MDIO_BUSY))) {
 377		*phy_data = (u16) val;
 378		return 0;
 379	}
 380	return ATLX_ERR_PHY;
 381}
 382
 383#define CUSTOM_SPI_CS_SETUP	2
 384#define CUSTOM_SPI_CLK_HI	2
 385#define CUSTOM_SPI_CLK_LO	2
 386#define CUSTOM_SPI_CS_HOLD	2
 387#define CUSTOM_SPI_CS_HI	3
 388
 389static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
 390{
 391	int i;
 392	u32 value;
 393
 394	iowrite32(0, hw->hw_addr + REG_SPI_DATA);
 395	iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
 396
 397	value = SPI_FLASH_CTRL_WAIT_READY |
 398	    (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
 399	    SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
 400					     SPI_FLASH_CTRL_CLK_HI_MASK) <<
 401	    SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
 402					   SPI_FLASH_CTRL_CLK_LO_MASK) <<
 403	    SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
 404					   SPI_FLASH_CTRL_CS_HOLD_MASK) <<
 405	    SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
 406					    SPI_FLASH_CTRL_CS_HI_MASK) <<
 407	    SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
 408	    SPI_FLASH_CTRL_INS_SHIFT;
 409
 410	iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
 411
 412	value |= SPI_FLASH_CTRL_START;
 413	iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
 414	ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
 415
 416	for (i = 0; i < 10; i++) {
 417		msleep(1);
 418		value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
 419		if (!(value & SPI_FLASH_CTRL_START))
 420			break;
 421	}
 422
 423	if (value & SPI_FLASH_CTRL_START)
 424		return false;
 425
 426	*buf = ioread32(hw->hw_addr + REG_SPI_DATA);
 427
 428	return true;
 429}
 430
 431/*
 432 * get_permanent_address
 433 * return 0 if get valid mac address,
 434 */
 435static int atl1_get_permanent_address(struct atl1_hw *hw)
 436{
 437	u32 addr[2];
 438	u32 i, control;
 439	u16 reg;
 440	u8 eth_addr[ETH_ALEN];
 441	bool key_valid;
 442
 443	if (is_valid_ether_addr(hw->perm_mac_addr))
 444		return 0;
 445
 446	/* init */
 447	addr[0] = addr[1] = 0;
 448
 449	if (!atl1_check_eeprom_exist(hw)) {
 450		reg = 0;
 451		key_valid = false;
 452		/* Read out all EEPROM content */
 453		i = 0;
 454		while (1) {
 455			if (atl1_read_eeprom(hw, i + 0x100, &control)) {
 456				if (key_valid) {
 457					if (reg == REG_MAC_STA_ADDR)
 458						addr[0] = control;
 459					else if (reg == (REG_MAC_STA_ADDR + 4))
 460						addr[1] = control;
 461					key_valid = false;
 462				} else if ((control & 0xff) == 0x5A) {
 463					key_valid = true;
 464					reg = (u16) (control >> 16);
 465				} else
 466					break;
 467			} else
 468				/* read error */
 469				break;
 470			i += 4;
 471		}
 472
 473		*(u32 *) &eth_addr[2] = swab32(addr[0]);
 474		*(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
 475		if (is_valid_ether_addr(eth_addr)) {
 476			memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
 477			return 0;
 478		}
 479	}
 480
 481	/* see if SPI FLAGS exist ? */
 482	addr[0] = addr[1] = 0;
 483	reg = 0;
 484	key_valid = false;
 485	i = 0;
 486	while (1) {
 487		if (atl1_spi_read(hw, i + 0x1f000, &control)) {
 488			if (key_valid) {
 489				if (reg == REG_MAC_STA_ADDR)
 490					addr[0] = control;
 491				else if (reg == (REG_MAC_STA_ADDR + 4))
 492					addr[1] = control;
 493				key_valid = false;
 494			} else if ((control & 0xff) == 0x5A) {
 495				key_valid = true;
 496				reg = (u16) (control >> 16);
 497			} else
 498				/* data end */
 499				break;
 500		} else
 501			/* read error */
 502			break;
 503		i += 4;
 504	}
 505
 506	*(u32 *) &eth_addr[2] = swab32(addr[0]);
 507	*(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
 508	if (is_valid_ether_addr(eth_addr)) {
 509		memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
 510		return 0;
 511	}
 512
 513	/*
 514	 * On some motherboards, the MAC address is written by the
 515	 * BIOS directly to the MAC register during POST, and is
 516	 * not stored in eeprom.  If all else thus far has failed
 517	 * to fetch the permanent MAC address, try reading it directly.
 518	 */
 519	addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
 520	addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
 521	*(u32 *) &eth_addr[2] = swab32(addr[0]);
 522	*(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
 523	if (is_valid_ether_addr(eth_addr)) {
 524		memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
 525		return 0;
 526	}
 527
 528	return 1;
 529}
 530
 531/*
 532 * Reads the adapter's MAC address from the EEPROM
 533 * hw - Struct containing variables accessed by shared code
 534 */
 535static s32 atl1_read_mac_addr(struct atl1_hw *hw)
 536{
 537	u16 i;
 538
 539	if (atl1_get_permanent_address(hw))
 540		random_ether_addr(hw->perm_mac_addr);
 541
 542	for (i = 0; i < ETH_ALEN; i++)
 543		hw->mac_addr[i] = hw->perm_mac_addr[i];
 544	return 0;
 545}
 546
 547/*
 548 * Hashes an address to determine its location in the multicast table
 549 * hw - Struct containing variables accessed by shared code
 550 * mc_addr - the multicast address to hash
 551 *
 552 * atl1_hash_mc_addr
 553 *  purpose
 554 *      set hash value for a multicast address
 555 *      hash calcu processing :
 556 *          1. calcu 32bit CRC for multicast address
 557 *          2. reverse crc with MSB to LSB
 558 */
 559static u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
 560{
 561	u32 crc32, value = 0;
 562	int i;
 563
 564	crc32 = ether_crc_le(6, mc_addr);
 565	for (i = 0; i < 32; i++)
 566		value |= (((crc32 >> i) & 1) << (31 - i));
 567
 568	return value;
 569}
 570
 571/*
 572 * Sets the bit in the multicast table corresponding to the hash value.
 573 * hw - Struct containing variables accessed by shared code
 574 * hash_value - Multicast address hash value
 575 */
 576static void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
 577{
 578	u32 hash_bit, hash_reg;
 579	u32 mta;
 580
 581	/*
 582	 * The HASH Table  is a register array of 2 32-bit registers.
 583	 * It is treated like an array of 64 bits.  We want to set
 584	 * bit BitArray[hash_value]. So we figure out what register
 585	 * the bit is in, read it, OR in the new bit, then write
 586	 * back the new value.  The register is determined by the
 587	 * upper 7 bits of the hash value and the bit within that
 588	 * register are determined by the lower 5 bits of the value.
 589	 */
 590	hash_reg = (hash_value >> 31) & 0x1;
 591	hash_bit = (hash_value >> 26) & 0x1F;
 592	mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
 593	mta |= (1 << hash_bit);
 594	iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
 595}
 596
 597/*
 598 * Writes a value to a PHY register
 599 * hw - Struct containing variables accessed by shared code
 600 * reg_addr - address of the PHY register to write
 601 * data - data to write to the PHY
 602 */
 603static s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
 604{
 605	int i;
 606	u32 val;
 607
 608	val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
 609	    (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
 610	    MDIO_SUP_PREAMBLE |
 611	    MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
 612	iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
 613	ioread32(hw->hw_addr + REG_MDIO_CTRL);
 614
 615	for (i = 0; i < MDIO_WAIT_TIMES; i++) {
 616		udelay(2);
 617		val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
 618		if (!(val & (MDIO_START | MDIO_BUSY)))
 619			break;
 620	}
 621
 622	if (!(val & (MDIO_START | MDIO_BUSY)))
 623		return 0;
 624
 625	return ATLX_ERR_PHY;
 626}
 627
 628/*
 629 * Make L001's PHY out of Power Saving State (bug)
 630 * hw - Struct containing variables accessed by shared code
 631 * when power on, L001's PHY always on Power saving State
 632 * (Gigabit Link forbidden)
 633 */
 634static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
 635{
 636	s32 ret;
 637	ret = atl1_write_phy_reg(hw, 29, 0x0029);
 638	if (ret)
 639		return ret;
 640	return atl1_write_phy_reg(hw, 30, 0);
 641}
 642
 643/*
 644 * Resets the PHY and make all config validate
 645 * hw - Struct containing variables accessed by shared code
 646 *
 647 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
 648 */
 649static s32 atl1_phy_reset(struct atl1_hw *hw)
 650{
 651	struct pci_dev *pdev = hw->back->pdev;
 652	struct atl1_adapter *adapter = hw->back;
 653	s32 ret_val;
 654	u16 phy_data;
 655
 656	if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
 657	    hw->media_type == MEDIA_TYPE_1000M_FULL)
 658		phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
 659	else {
 660		switch (hw->media_type) {
 661		case MEDIA_TYPE_100M_FULL:
 662			phy_data =
 663			    MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
 664			    MII_CR_RESET;
 665			break;
 666		case MEDIA_TYPE_100M_HALF:
 667			phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
 668			break;
 669		case MEDIA_TYPE_10M_FULL:
 670			phy_data =
 671			    MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
 672			break;
 673		default:
 674			/* MEDIA_TYPE_10M_HALF: */
 675			phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
 676			break;
 677		}
 678	}
 679
 680	ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
 681	if (ret_val) {
 682		u32 val;
 683		int i;
 684		/* pcie serdes link may be down! */
 685		if (netif_msg_hw(adapter))
 686			dev_dbg(&pdev->dev, "pcie phy link down\n");
 687
 688		for (i = 0; i < 25; i++) {
 689			msleep(1);
 690			val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
 691			if (!(val & (MDIO_START | MDIO_BUSY)))
 692				break;
 693		}
 694
 695		if ((val & (MDIO_START | MDIO_BUSY)) != 0) {
 696			if (netif_msg_hw(adapter))
 697				dev_warn(&pdev->dev,
 698					"pcie link down at least 25ms\n");
 699			return ret_val;
 700		}
 701	}
 702	return 0;
 703}
 704
 705/*
 706 * Configures PHY autoneg and flow control advertisement settings
 707 * hw - Struct containing variables accessed by shared code
 708 */
 709static s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
 710{
 711	s32 ret_val;
 712	s16 mii_autoneg_adv_reg;
 713	s16 mii_1000t_ctrl_reg;
 714
 715	/* Read the MII Auto-Neg Advertisement Register (Address 4). */
 716	mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
 717
 718	/* Read the MII 1000Base-T Control Register (Address 9). */
 719	mii_1000t_ctrl_reg = MII_ATLX_CR_1000T_DEFAULT_CAP_MASK;
 720
 721	/*
 722	 * First we clear all the 10/100 mb speed bits in the Auto-Neg
 723	 * Advertisement Register (Address 4) and the 1000 mb speed bits in
 724	 * the  1000Base-T Control Register (Address 9).
 725	 */
 726	mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
 727	mii_1000t_ctrl_reg &= ~MII_ATLX_CR_1000T_SPEED_MASK;
 728
 729	/*
 730	 * Need to parse media_type  and set up
 731	 * the appropriate PHY registers.
 732	 */
 733	switch (hw->media_type) {
 734	case MEDIA_TYPE_AUTO_SENSOR:
 735		mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
 736					MII_AR_10T_FD_CAPS |
 737					MII_AR_100TX_HD_CAPS |
 738					MII_AR_100TX_FD_CAPS);
 739		mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
 740		break;
 741
 742	case MEDIA_TYPE_1000M_FULL:
 743		mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
 744		break;
 745
 746	case MEDIA_TYPE_100M_FULL:
 747		mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
 748		break;
 749
 750	case MEDIA_TYPE_100M_HALF:
 751		mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
 752		break;
 753
 754	case MEDIA_TYPE_10M_FULL:
 755		mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
 756		break;
 757
 758	default:
 759		mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
 760		break;
 761	}
 762
 763	/* flow control fixed to enable all */
 764	mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
 765
 766	hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
 767	hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
 768
 769	ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
 770	if (ret_val)
 771		return ret_val;
 772
 773	ret_val = atl1_write_phy_reg(hw, MII_ATLX_CR, mii_1000t_ctrl_reg);
 774	if (ret_val)
 775		return ret_val;
 776
 777	return 0;
 778}
 779
 780/*
 781 * Configures link settings.
 782 * hw - Struct containing variables accessed by shared code
 783 * Assumes the hardware has previously been reset and the
 784 * transmitter and receiver are not enabled.
 785 */
 786static s32 atl1_setup_link(struct atl1_hw *hw)
 787{
 788	struct pci_dev *pdev = hw->back->pdev;
 789	struct atl1_adapter *adapter = hw->back;
 790	s32 ret_val;
 791
 792	/*
 793	 * Options:
 794	 *  PHY will advertise value(s) parsed from
 795	 *  autoneg_advertised and fc
 796	 *  no matter what autoneg is , We will not wait link result.
 797	 */
 798	ret_val = atl1_phy_setup_autoneg_adv(hw);
 799	if (ret_val) {
 800		if (netif_msg_link(adapter))
 801			dev_dbg(&pdev->dev,
 802				"error setting up autonegotiation\n");
 803		return ret_val;
 804	}
 805	/* SW.Reset , En-Auto-Neg if needed */
 806	ret_val = atl1_phy_reset(hw);
 807	if (ret_val) {
 808		if (netif_msg_link(adapter))
 809			dev_dbg(&pdev->dev, "error resetting phy\n");
 810		return ret_val;
 811	}
 812	hw->phy_configured = true;
 813	return ret_val;
 814}
 815
 816static void atl1_init_flash_opcode(struct atl1_hw *hw)
 817{
 818	if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
 819		/* Atmel */
 820		hw->flash_vendor = 0;
 821
 822	/* Init OP table */
 823	iowrite8(flash_table[hw->flash_vendor].cmd_program,
 824		hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
 825	iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
 826		hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
 827	iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
 828		hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
 829	iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
 830		hw->hw_addr + REG_SPI_FLASH_OP_RDID);
 831	iowrite8(flash_table[hw->flash_vendor].cmd_wren,
 832		hw->hw_addr + REG_SPI_FLASH_OP_WREN);
 833	iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
 834		hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
 835	iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
 836		hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
 837	iowrite8(flash_table[hw->flash_vendor].cmd_read,
 838		hw->hw_addr + REG_SPI_FLASH_OP_READ);
 839}
 840
 841/*
 842 * Performs basic configuration of the adapter.
 843 * hw - Struct containing variables accessed by shared code
 844 * Assumes that the controller has previously been reset and is in a
 845 * post-reset uninitialized state. Initializes multicast table,
 846 * and  Calls routines to setup link
 847 * Leaves the transmit and receive units disabled and uninitialized.
 848 */
 849static s32 atl1_init_hw(struct atl1_hw *hw)
 850{
 851	u32 ret_val = 0;
 852
 853	/* Zero out the Multicast HASH table */
 854	iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
 855	/* clear the old settings from the multicast hash table */
 856	iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
 857
 858	atl1_init_flash_opcode(hw);
 859
 860	if (!hw->phy_configured) {
 861		/* enable GPHY LinkChange Interrrupt */
 862		ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
 863		if (ret_val)
 864			return ret_val;
 865		/* make PHY out of power-saving state */
 866		ret_val = atl1_phy_leave_power_saving(hw);
 867		if (ret_val)
 868			return ret_val;
 869		/* Call a subroutine to configure the link */
 870		ret_val = atl1_setup_link(hw);
 871	}
 872	return ret_val;
 873}
 874
 875/*
 876 * Detects the current speed and duplex settings of the hardware.
 877 * hw - Struct containing variables accessed by shared code
 878 * speed - Speed of the connection
 879 * duplex - Duplex setting of the connection
 880 */
 881static s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
 882{
 883	struct pci_dev *pdev = hw->back->pdev;
 884	struct atl1_adapter *adapter = hw->back;
 885	s32 ret_val;
 886	u16 phy_data;
 887
 888	/* ; --- Read   PHY Specific Status Register (17) */
 889	ret_val = atl1_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
 890	if (ret_val)
 891		return ret_val;
 892
 893	if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
 894		return ATLX_ERR_PHY_RES;
 895
 896	switch (phy_data & MII_ATLX_PSSR_SPEED) {
 897	case MII_ATLX_PSSR_1000MBS:
 898		*speed = SPEED_1000;
 899		break;
 900	case MII_ATLX_PSSR_100MBS:
 901		*speed = SPEED_100;
 902		break;
 903	case MII_ATLX_PSSR_10MBS:
 904		*speed = SPEED_10;
 905		break;
 906	default:
 907		if (netif_msg_hw(adapter))
 908			dev_dbg(&pdev->dev, "error getting speed\n");
 909		return ATLX_ERR_PHY_SPEED;
 910		break;
 911	}
 912	if (phy_data & MII_ATLX_PSSR_DPLX)
 913		*duplex = FULL_DUPLEX;
 914	else
 915		*duplex = HALF_DUPLEX;
 916
 917	return 0;
 918}
 919
 920static void atl1_set_mac_addr(struct atl1_hw *hw)
 921{
 922	u32 value;
 923	/*
 924	 * 00-0B-6A-F6-00-DC
 925	 * 0:  6AF600DC   1: 000B
 926	 * low dword
 927	 */
 928	value = (((u32) hw->mac_addr[2]) << 24) |
 929	    (((u32) hw->mac_addr[3]) << 16) |
 930	    (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
 931	iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
 932	/* high dword */
 933	value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
 934	iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
 935}
 936
 937/*
 938 * atl1_sw_init - Initialize general software structures (struct atl1_adapter)
 939 * @adapter: board private structure to initialize
 940 *
 941 * atl1_sw_init initializes the Adapter private data structure.
 942 * Fields are initialized based on PCI device information and
 943 * OS network device settings (MTU size).
 944 */
 945static int __devinit atl1_sw_init(struct atl1_adapter *adapter)
 946{
 947	struct atl1_hw *hw = &adapter->hw;
 948	struct net_device *netdev = adapter->netdev;
 949
 950	hw->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
 951	hw->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
 952
 953	adapter->wol = 0;
 954	device_set_wakeup_enable(&adapter->pdev->dev, false);
 955	adapter->rx_buffer_len = (hw->max_frame_size + 7) & ~7;
 956	adapter->ict = 50000;		/* 100ms */
 957	adapter->link_speed = SPEED_0;	/* hardware init */
 958	adapter->link_duplex = FULL_DUPLEX;
 959
 960	hw->phy_configured = false;
 961	hw->preamble_len = 7;
 962	hw->ipgt = 0x60;
 963	hw->min_ifg = 0x50;
 964	hw->ipgr1 = 0x40;
 965	hw->ipgr2 = 0x60;
 966	hw->max_retry = 0xf;
 967	hw->lcol = 0x37;
 968	hw->jam_ipg = 7;
 969	hw->rfd_burst = 8;
 970	hw->rrd_burst = 8;
 971	hw->rfd_fetch_gap = 1;
 972	hw->rx_jumbo_th = adapter->rx_buffer_len / 8;
 973	hw->rx_jumbo_lkah = 1;
 974	hw->rrd_ret_timer = 16;
 975	hw->tpd_burst = 4;
 976	hw->tpd_fetch_th = 16;
 977	hw->txf_burst = 0x100;
 978	hw->tx_jumbo_task_th = (hw->max_frame_size + 7) >> 3;
 979	hw->tpd_fetch_gap = 1;
 980	hw->rcb_value = atl1_rcb_64;
 981	hw->dma_ord = atl1_dma_ord_enh;
 982	hw->dmar_block = atl1_dma_req_256;
 983	hw->dmaw_block = atl1_dma_req_256;
 984	hw->cmb_rrd = 4;
 985	hw->cmb_tpd = 4;
 986	hw->cmb_rx_timer = 1;	/* about 2us */
 987	hw->cmb_tx_timer = 1;	/* about 2us */
 988	hw->smb_timer = 100000;	/* about 200ms */
 989
 990	spin_lock_init(&adapter->lock);
 991	spin_lock_init(&adapter->mb_lock);
 992
 993	return 0;
 994}
 995
 996static int mdio_read(struct net_device *netdev, int phy_id, int reg_num)
 997{
 998	struct atl1_adapter *adapter = netdev_priv(netdev);
 999	u16 result;
1000
1001	atl1_read_phy_reg(&adapter->hw, reg_num & 0x1f, &result);
1002
1003	return result;
1004}
1005
1006static void mdio_write(struct net_device *netdev, int phy_id, int reg_num,
1007	int val)
1008{
1009	struct atl1_adapter *adapter = netdev_priv(netdev);
1010
1011	atl1_write_phy_reg(&adapter->hw, reg_num, val);
1012}
1013
1014/*
1015 * atl1_mii_ioctl -
1016 * @netdev:
1017 * @ifreq:
1018 * @cmd:
1019 */
1020static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1021{
1022	struct atl1_adapter *adapter = netdev_priv(netdev);
1023	unsigned long flags;
1024	int retval;
1025
1026	if (!netif_running(netdev))
1027		return -EINVAL;
1028
1029	spin_lock_irqsave(&adapter->lock, flags);
1030	retval = generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
1031	spin_unlock_irqrestore(&adapter->lock, flags);
1032
1033	return retval;
1034}
1035
1036/*
1037 * atl1_setup_mem_resources - allocate Tx / RX descriptor resources
1038 * @adapter: board private structure
1039 *
1040 * Return 0 on success, negative on failure
1041 */
1042static s32 atl1_setup_ring_resources(struct atl1_adapter *adapter)
1043{
1044	struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1045	struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1046	struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1047	struct atl1_ring_header *ring_header = &adapter->ring_header;
1048	struct pci_dev *pdev = adapter->pdev;
1049	int size;
1050	u8 offset = 0;
1051
1052	size = sizeof(struct atl1_buffer) * (tpd_ring->count + rfd_ring->count);
1053	tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
1054	if (unlikely(!tpd_ring->buffer_info)) {
1055		if (netif_msg_drv(adapter))
1056			dev_err(&pdev->dev, "kzalloc failed , size = D%d\n",
1057				size);
1058		goto err_nomem;
1059	}
1060	rfd_ring->buffer_info =
1061		(struct atl1_buffer *)(tpd_ring->buffer_info + tpd_ring->count);
1062
1063	/*
1064	 * real ring DMA buffer
1065	 * each ring/block may need up to 8 bytes for alignment, hence the
1066	 * additional 40 bytes tacked onto the end.
1067	 */
1068	ring_header->size = size =
1069		sizeof(struct tx_packet_desc) * tpd_ring->count
1070		+ sizeof(struct rx_free_desc) * rfd_ring->count
1071		+ sizeof(struct rx_return_desc) * rrd_ring->count
1072		+ sizeof(struct coals_msg_block)
1073		+ sizeof(struct stats_msg_block)
1074		+ 40;
1075
1076	ring_header->desc = pci_alloc_consistent(pdev, ring_header->size,
1077		&ring_header->dma);
1078	if (unlikely(!ring_header->desc)) {
1079		if (netif_msg_drv(adapter))
1080			dev_err(&pdev->dev, "pci_alloc_consistent failed\n");
1081		goto err_nomem;
1082	}
1083
1084	memset(ring_header->desc, 0, ring_header->size);
1085
1086	/* init TPD ring */
1087	tpd_ring->dma = ring_header->dma;
1088	offset = (tpd_ring->dma & 0x7) ? (8 - (ring_header->dma & 0x7)) : 0;
1089	tpd_ring->dma += offset;
1090	tpd_ring->desc = (u8 *) ring_header->desc + offset;
1091	tpd_ring->size = sizeof(struct tx_packet_desc) * tpd_ring->count;
1092
1093	/* init RFD ring */
1094	rfd_ring->dma = tpd_ring->dma + tpd_ring->size;
1095	offset = (rfd_ring->dma & 0x7) ? (8 - (rfd_ring->dma & 0x7)) : 0;
1096	rfd_ring->dma += offset;
1097	rfd_ring->desc = (u8 *) tpd_ring->desc + (tpd_ring->size + offset);
1098	rfd_ring->size = sizeof(struct rx_free_desc) * rfd_ring->count;
1099
1100
1101	/* init RRD ring */
1102	rrd_ring->dma = rfd_ring->dma + rfd_ring->size;
1103	offset = (rrd_ring->dma & 0x7) ? (8 - (rrd_ring->dma & 0x7)) : 0;
1104	rrd_ring->dma += offset;
1105	rrd_ring->desc = (u8 *) rfd_ring->desc + (rfd_ring->size + offset);
1106	rrd_ring->size = sizeof(struct rx_return_desc) * rrd_ring->count;
1107
1108
1109	/* init CMB */
1110	adapter->cmb.dma = rrd_ring->dma + rrd_ring->size;
1111	offset = (adapter->cmb.dma & 0x7) ? (8 - (adapter->cmb.dma & 0x7)) : 0;
1112	adapter->cmb.dma += offset;
1113	adapter->cmb.cmb = (struct coals_msg_block *)
1114		((u8 *) rrd_ring->desc + (rrd_ring->size + offset));
1115
1116	/* init SMB */
1117	adapter->smb.dma = adapter->cmb.dma + sizeof(struct coals_msg_block);
1118	offset = (adapter->smb.dma & 0x7) ? (8 - (adapter->smb.dma & 0x7)) : 0;
1119	adapter->smb.dma += offset;
1120	adapter->smb.smb = (struct stats_msg_block *)
1121		((u8 *) adapter->cmb.cmb +
1122		(sizeof(struct coals_msg_block) + offset));
1123
1124	return 0;
1125
1126err_nomem:
1127	kfree(tpd_ring->buffer_info);
1128	return -ENOMEM;
1129}
1130
1131static void atl1_init_ring_ptrs(struct atl1_adapter *adapter)
1132{
1133	struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1134	struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1135	struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1136
1137	atomic_set(&tpd_ring->next_to_use, 0);
1138	atomic_set(&tpd_ring->next_to_clean, 0);
1139
1140	rfd_ring->next_to_clean = 0;
1141	atomic_set(&rfd_ring->next_to_use, 0);
1142
1143	rrd_ring->next_to_use = 0;
1144	atomic_set(&rrd_ring->next_to_clean, 0);
1145}
1146
1147/*
1148 * atl1_clean_rx_ring - Free RFD Buffers
1149 * @adapter: board private structure
1150 */
1151static void atl1_clean_rx_ring(struct atl1_adapter *adapter)
1152{
1153	struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1154	struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1155	struct atl1_buffer *buffer_info;
1156	struct pci_dev *pdev = adapter->pdev;
1157	unsigned long size;
1158	unsigned int i;
1159
1160	/* Free all the Rx ring sk_buffs */
1161	for (i = 0; i < rfd_ring->count; i++) {
1162		buffer_info = &rfd_ring->buffer_info[i];
1163		if (buffer_info->dma) {
1164			pci_unmap_page(pdev, buffer_info->dma,
1165				buffer_info->length, PCI_DMA_FROMDEVICE);
1166			buffer_info->dma = 0;
1167		}
1168		if (buffer_info->skb) {
1169			dev_kfree_skb(buffer_info->skb);
1170			buffer_info->skb = NULL;
1171		}
1172	}
1173
1174	size = sizeof(struct atl1_buffer) * rfd_ring->count;
1175	memset(rfd_ring->buffer_info, 0, size);
1176
1177	/* Zero out the descriptor ring */
1178	memset(rfd_ring->desc, 0, rfd_ring->size);
1179
1180	rfd_ring->next_to_clean = 0;
1181	atomic_set(&rfd_ring->next_to_use, 0);
1182
1183	rrd_ring->next_to_use = 0;
1184	atomic_set(&rrd_ring->next_to_clean, 0);
1185}
1186
1187/*
1188 * atl1_clean_tx_ring - Free Tx Buffers
1189 * @adapter: board private structure
1190 */
1191static void atl1_clean_tx_ring(struct atl1_adapter *adapter)
1192{
1193	struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1194	struct atl1_buffer *buffer_info;
1195	struct pci_dev *pdev = adapter->pdev;
1196	unsigned long size;
1197	unsigned int i;
1198
1199	/* Free all the Tx ring sk_buffs */
1200	for (i = 0; i < tpd_ring->count; i++) {
1201		buffer_info = &tpd_ring->buffer_info[i];
1202		if (buffer_info->dma) {
1203			pci_unmap_page(pdev, buffer_info->dma,
1204				buffer_info->length, PCI_DMA_TODEVICE);
1205			buffer_info->dma = 0;
1206		}
1207	}
1208
1209	for (i = 0; i < tpd_ring->count; i++) {
1210		buffer_info = &tpd_ring->buffer_info[i];
1211		if (buffer_info->skb) {
1212			dev_kfree_skb_any(buffer_info->skb);
1213			buffer_info->skb = NULL;
1214		}
1215	}
1216
1217	size = sizeof(struct atl1_buffer) * tpd_ring->count;
1218	memset(tpd_ring->buffer_info, 0, size);
1219
1220	/* Zero out the descriptor ring */
1221	memset(tpd_ring->desc, 0, tpd_ring->size);
1222
1223	atomic_set(&tpd_ring->next_to_use, 0);
1224	atomic_set(&tpd_ring->next_to_clean, 0);
1225}
1226
1227/*
1228 * atl1_free_ring_resources - Free Tx / RX descriptor Resources
1229 * @adapter: board private structure
1230 *
1231 * Free all transmit software resources
1232 */
1233static void atl1_free_ring_resources(struct atl1_adapter *adapter)
1234{
1235	struct pci_dev *pdev = adapter->pdev;
1236	struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1237	struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1238	struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1239	struct atl1_ring_header *ring_header = &adapter->ring_header;
1240
1241	atl1_clean_tx_ring(adapter);
1242	atl1_clean_rx_ring(adapter);
1243
1244	kfree(tpd_ring->buffer_info);
1245	pci_free_consistent(pdev, ring_header->size, ring_header->desc,
1246		ring_header->dma);
1247
1248	tpd_ring->buffer_info = NULL;
1249	tpd_ring->desc = NULL;
1250	tpd_ring->dma = 0;
1251
1252	rfd_ring->buffer_info = NULL;
1253	rfd_ring->desc = NULL;
1254	rfd_ring->dma = 0;
1255
1256	rrd_ring->desc = NULL;
1257	rrd_ring->dma = 0;
1258
1259	adapter->cmb.dma = 0;
1260	adapter->cmb.cmb = NULL;
1261
1262	adapter->smb.dma = 0;
1263	adapter->smb.smb = NULL;
1264}
1265
1266static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter)
1267{
1268	u32 value;
1269	struct atl1_hw *hw = &adapter->hw;
1270	struct net_device *netdev = adapter->netdev;
1271	/* Config MAC CTRL Register */
1272	value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
1273	/* duplex */
1274	if (FULL_DUPLEX == adapter->link_duplex)
1275		value |= MAC_CTRL_DUPLX;
1276	/* speed */
1277	value |= ((u32) ((SPEED_1000 == adapter->link_speed) ?
1278			 MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
1279		  MAC_CTRL_SPEED_SHIFT);
1280	/* flow control */
1281	value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1282	/* PAD & CRC */
1283	value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1284	/* preamble length */
1285	value |= (((u32) adapter->hw.preamble_len
1286		   & MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1287	/* vlan */
1288	if (adapter->vlgrp)
1289		value |= MAC_CTRL_RMV_VLAN;
1290	/* rx checksum
1291	   if (adapter->rx_csum)
1292	   value |= MAC_CTRL_RX_CHKSUM_EN;
1293	 */
1294	/* filter mode */
1295	value |= MAC_CTRL_BC_EN;
1296	if (netdev->flags & IFF_PROMISC)
1297		value |= MAC_CTRL_PROMIS_EN;
1298	else if (netdev->flags & IFF_ALLMULTI)
1299		value |= MAC_CTRL_MC_ALL_EN;
1300	/* value |= MAC_CTRL_LOOPBACK; */
1301	iowrite32(value, hw->hw_addr + REG_MAC_CTRL);
1302}
1303
1304static u32 atl1_check_link(struct atl1_adapter *adapter)
1305{
1306	struct atl1_hw *hw = &adapter->hw;
1307	struct net_device *netdev = adapter->netdev;
1308	u32 ret_val;
1309	u16 speed, duplex, phy_data;
1310	int reconfig = 0;
1311
1312	/* MII_BMSR must read twice */
1313	atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
1314	atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
1315	if (!(phy_data & BMSR_LSTATUS)) {
1316		/* link down */
1317		if (netif_carrier_ok(netdev)) {
1318			/* old link state: Up */
1319			if (netif_msg_link(adapter))
1320				dev_info(&adapter->pdev->dev, "link is down\n");
1321			adapter->link_speed = SPEED_0;
1322			netif_carrier_off(netdev);
1323		}
1324		return 0;
1325	}
1326
1327	/* Link Up */
1328	ret_val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
1329	if (ret_val)
1330		return ret_val;
1331
1332	switch (hw->media_type) {
1333	case MEDIA_TYPE_1000M_FULL:
1334		if (speed != SPEED_1000 || duplex != FULL_DUPLEX)
1335			reconfig = 1;
1336		break;
1337	case MEDIA_TYPE_100M_FULL:
1338		if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1339			reconfig = 1;
1340		break;
1341	case MEDIA_TYPE_100M_HALF:
1342		if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1343			reconfig = 1;
1344		break;
1345	case MEDIA_TYPE_10M_FULL:
1346		if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1347			reconfig = 1;
1348		break;
1349	case MEDIA_TYPE_10M_HALF:
1350		if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1351			reconfig = 1;
1352		break;
1353	}
1354
1355	/* link result is our setting */
1356	if (!reconfig) {
1357		if (adapter->link_speed != speed ||
1358		    adapter->link_duplex != duplex) {
1359			adapter->link_speed = speed;
1360			adapter->link_duplex = duplex;
1361			atl1_setup_mac_ctrl(adapter);
1362			if (netif_msg_link(adapter))
1363				dev_info(&adapter->pdev->dev,
1364					"%s link is up %d Mbps %s\n",
1365					netdev->name, adapter->link_speed,
1366					adapter->link_duplex == FULL_DUPLEX ?
1367					"full duplex" : "half duplex");
1368		}
1369		if (!netif_carrier_ok(netdev)) {
1370			/* Link down -> Up */
1371			netif_carrier_on(netdev);
1372		}
1373		return 0;
1374	}
1375
1376	/* change original link status */
1377	if (netif_carrier_ok(netdev)) {
1378		adapter->link_speed = SPEED_0;
1379		netif_carrier_off(netdev);
1380		netif_stop_queue(netdev);
1381	}
1382
1383	if (hw->media_type != MEDIA_TYPE_AUTO_SENSOR &&
1384	    hw->media_type != MEDIA_TYPE_1000M_FULL) {
1385		switch (hw->media_type) {
1386		case MEDIA_TYPE_100M_FULL:
1387			phy_data = MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
1388			           MII_CR_RESET;
1389			break;
1390		case MEDIA_TYPE_100M_HALF:
1391			phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
1392			break;
1393		case MEDIA_TYPE_10M_FULL:
1394			phy_data =
1395			    MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
1396			break;
1397		default:
1398			/* MEDIA_TYPE_10M_HALF: */
1399			phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
1400			break;
1401		}
1402		atl1_write_phy_reg(hw, MII_BMCR, phy_data);
1403		return 0;
1404	}
1405
1406	/* auto-neg, insert timer to re-config phy */
1407	if (!adapter->phy_timer_pending) {
1408		adapter->phy_timer_pending = true;
1409		mod_timer(&adapter->phy_config_timer,
1410			  round_jiffies(jiffies + 3 * HZ));
1411	}
1412
1413	return 0;
1414}
1415
1416static void set_flow_ctrl_old(struct atl1_adapter *adapter)
1417{
1418	u32 hi, lo, value;
1419
1420	/* RFD Flow Control */
1421	value = adapter->rfd_ring.count;
1422	hi = value / 16;
1423	if (hi < 2)
1424		hi = 2;
1425	lo = value * 7 / 8;
1426
1427	value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
1428		((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
1429	iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
1430
1431	/* RRD Flow Control */
1432	value = adapter->rrd_ring.count;
1433	lo = value / 16;
1434	hi = value * 7 / 8;
1435	if (lo < 2)
1436		lo = 2;
1437	value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
1438		((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
1439	iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1440}
1441
1442static void set_flow_ctrl_new(struct atl1_hw *hw)
1443{
1444	u32 hi, lo, value;
1445
1446	/* RXF Flow Control */
1447	value = ioread32(hw->hw_addr + REG_SRAM_RXF_LEN);
1448	lo = value / 16;
1449	if (lo < 192)
1450		lo = 192;
1451	hi = value * 7 / 8;
1452	if (hi < lo)
1453		hi = lo + 16;
1454	value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
1455		((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
1456	iowrite32(value, hw->hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
1457
1458	/* RRD Flow Control */
1459	value = ioread32(hw->hw_addr + REG_SRAM_RRD_LEN);
1460	lo = value / 8;
1461	hi = value * 7 / 8;
1462	if (lo < 2)
1463		lo = 2;
1464	if (hi < lo)
1465		hi = lo + 3;
1466	value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
1467		((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
1468	iowrite32(value, hw->hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1469}
1470
1471/*
1472 * atl1_configure - Configure Transmit&Receive Unit after Reset
1473 * @adapter: board private structure
1474 *
1475 * Configure the Tx /Rx unit of the MAC after a reset.
1476 */
1477static u32 atl1_configure(struct atl1_adapter *adapter)
1478{
1479	struct atl1_hw *hw = &adapter->hw;
1480	u32 value;
1481
1482	/* clear interrupt status */
1483	iowrite32(0xffffffff, adapter->hw.hw_addr + REG_ISR);
1484
1485	/* set MAC Address */
1486	value = (((u32) hw->mac_addr[2]) << 24) |
1487		(((u32) hw->mac_addr[3]) << 16) |
1488		(((u32) hw->mac_addr[4]) << 8) |
1489		(((u32) hw->mac_addr[5]));
1490	iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
1491	value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
1492	iowrite32(value, hw->hw_addr + (REG_MAC_STA_ADDR + 4));
1493
1494	/* tx / rx ring */
1495
1496	/* HI base address */
1497	iowrite32((u32) ((adapter->tpd_ring.dma & 0xffffffff00000000ULL) >> 32),
1498		hw->hw_addr + REG_DESC_BASE_ADDR_HI);
1499	/* LO base address */
1500	iowrite32((u32) (adapter->rfd_ring.dma & 0x00000000ffffffffULL),
1501		hw->hw_addr + REG_DESC_RFD_ADDR_LO);
1502	iowrite32((u32) (adapter->rrd_ring.dma & 0x00000000ffffffffULL),
1503		hw->hw_addr + REG_DESC_RRD_ADDR_LO);
1504	iowrite32((u32) (adapter->tpd_ring.dma & 0x00000000ffffffffULL),
1505		hw->hw_addr + REG_DESC_TPD_ADDR_LO);
1506	iowrite32((u32) (adapter->cmb.dma & 0x00000000ffffffffULL),
1507		hw->hw_addr + REG_DESC_CMB_ADDR_LO);
1508	iowrite32((u32) (adapter->smb.dma & 0x00000000ffffffffULL),
1509		hw->hw_addr + REG_DESC_SMB_ADDR_LO);
1510
1511	/* element count */
1512	value = adapter->rrd_ring.count;
1513	value <<= 16;
1514	value += adapter->rfd_ring.count;
1515	iowrite32(value, hw->hw_addr + REG_DESC_RFD_RRD_RING_SIZE);
1516	iowrite32(adapter->tpd_ring.count, hw->hw_addr +
1517		REG_DESC_TPD_RING_SIZE);
1518
1519	/* Load Ptr */
1520	iowrite32(1, hw->hw_addr + REG_LOAD_PTR);
1521
1522	/* config Mailbox */
1523	value = ((atomic_read(&adapter->tpd_ring.next_to_use)
1524		  & MB_TPD_PROD_INDX_MASK) << MB_TPD_PROD_INDX_SHIFT) |
1525		((atomic_read(&adapter->rrd_ring.next_to_clean)
1526		& MB_RRD_CONS_INDX_MASK) << MB_RRD_CONS_INDX_SHIFT) |
1527		((atomic_read(&adapter->rfd_ring.next_to_use)
1528		& MB_RFD_PROD_INDX_MASK) << MB_RFD_PROD_INDX_SHIFT);
1529	iowrite32(value, hw->hw_addr + REG_MAILBOX);
1530
1531	/* config IPG/IFG */
1532	value = (((u32) hw->ipgt & MAC_IPG_IFG_IPGT_MASK)
1533		 << MAC_IPG_IFG_IPGT_SHIFT) |
1534		(((u32) hw->min_ifg & MAC_IPG_IFG_MIFG_MASK)
1535		<< MAC_IPG_IFG_MIFG_SHIFT) |
1536		(((u32) hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK)
1537		<< MAC_IPG_IFG_IPGR1_SHIFT) |
1538		(((u32) hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK)
1539		<< MAC_IPG_IFG_IPGR2_SHIFT);
1540	iowrite32(value, hw->hw_addr + REG_MAC_IPG_IFG);
1541
1542	/* config  Half-Duplex Control */
1543	value = ((u32) hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
1544		(((u32) hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK)
1545		<< MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
1546		MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
1547		(0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
1548		(((u32) hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK)
1549		<< MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
1550	iowrite32(value, hw->hw_addr + REG_MAC_HALF_DUPLX_CTRL);
1551
1552	/* set Interrupt Moderator Timer */
1553	iowrite16(adapter->imt, hw->hw_addr + REG_IRQ_MODU_TIMER_INIT);
1554	iowrite32(MASTER_CTRL_ITIMER_EN, hw->hw_addr + REG_MASTER_CTRL);
1555
1556	/* set Interrupt Clear Timer */
1557	iowrite16(adapter->ict, hw->hw_addr + REG_CMBDISDMA_TIMER);
1558
1559	/* set max frame size hw will accept */
1560	iowrite32(hw->max_frame_size, hw->hw_addr + REG_MTU);
1561
1562	/* jumbo size & rrd retirement timer */
1563	value = (((u32) hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK)
1564		 << RXQ_JMBOSZ_TH_SHIFT) |
1565		(((u32) hw->rx_jumbo_lkah & RXQ_JMBO_LKAH_MASK)
1566		<< RXQ_JMBO_LKAH_SHIFT) |
1567		(((u32) hw->rrd_ret_timer & RXQ_RRD_TIMER_MASK)
1568		<< RXQ_RRD_TIMER_SHIFT);
1569	iowrite32(value, hw->hw_addr + REG_RXQ_JMBOSZ_RRDTIM);
1570
1571	/* Flow Control */
1572	switch (hw->dev_rev) {
1573	case 0x8001:
1574	case 0x9001:
1575	case 0x9002:
1576	case 0x9003:
1577		set_flow_ctrl_old(adapter);
1578		break;
1579	default:
1580		set_flow_ctrl_new(hw);
1581		break;
1582	}
1583
1584	/* config TXQ */
1585	value = (((u32) hw->tpd_burst & TXQ_CTRL_TPD_BURST_NUM_MASK)
1586		 << TXQ_CTRL_TPD_BURST_NUM_SHIFT) |
1587		(((u32) hw->txf_burst & TXQ_CTRL_TXF_BURST_NUM_MASK)
1588		<< TXQ_CTRL_TXF_BURST_NUM_SHIFT) |
1589		(((u32) hw->tpd_fetch_th & TXQ_CTRL_TPD_FETCH_TH_MASK)
1590		<< TXQ_CTRL_TPD_FETCH_TH_SHIFT) | TXQ_CTRL_ENH_MODE |
1591		TXQ_CTRL_EN;
1592	iowrite32(value, hw->hw_addr + REG_TXQ_CTRL);
1593
1594	/* min tpd fetch gap & tx jumbo packet size threshold for taskoffload */
1595	value = (((u32) hw->tx_jumbo_task_th & TX_JUMBO_TASK_TH_MASK)
1596		<< TX_JUMBO_TASK_TH_SHIFT) |
1597		(((u32) hw->tpd_fetch_gap & TX_TPD_MIN_IPG_MASK)
1598		<< TX_TPD_MIN_IPG_SHIFT);
1599	iowrite32(value, hw->hw_addr + REG_TX_JUMBO_TASK_TH_TPD_IPG);
1600
1601	/* config RXQ */
1602	value = (((u32) hw->rfd_burst & RXQ_CTRL_RFD_BURST_NUM_MASK)
1603		<< RXQ_CTRL_RFD_BURST_NUM_SHIFT) |
1604		(((u32) hw->rrd_burst & RXQ_CTRL_RRD_BURST_THRESH_MASK)
1605		<< RXQ_CTRL_RRD_BURST_THRESH_SHIFT) |
1606		(((u32) hw->rfd_fetch_gap & RXQ_CTRL_RFD_PREF_MIN_IPG_MASK)
1607		<< RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT) | RXQ_CTRL_CUT_THRU_EN |
1608		RXQ_CTRL_EN;
1609	iowrite32(value, hw->hw_addr + REG_RXQ_CTRL);
1610
1611	/* config DMA Engine */
1612	value = ((((u32) hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
1613		<< DMA_CTRL_DMAR_BURST_LEN_SHIFT) |
1614		((((u32) hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
1615		<< DMA_CTRL_DMAW_BURST_LEN_SHIFT) | DMA_CTRL_DMAR_EN |
1616		DMA_CTRL_DMAW_EN;
1617	value |= (u32) hw->dma_ord;
1618	if (atl1_rcb_128 == hw->rcb_value)
1619		value |= DMA_CTRL_RCB_VALUE;
1620	iowrite32(value, hw->hw_addr + REG_DMA_CTRL);
1621
1622	/* config CMB / SMB */
1623	value = (hw->cmb_tpd > adapter->tpd_ring.count) ?
1624		hw->cmb_tpd : adapter->tpd_ring.count;
1625	value <<= 16;
1626	value |= hw->cmb_rrd;
1627	iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TH);
1628	value = hw->cmb_rx_timer | ((u32) hw->cmb_tx_timer << 16);
1629	iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TIMER);
1630	iowrite32(hw->smb_timer, hw->hw_addr + REG_SMB_TIMER);
1631
1632	/* --- enable CMB / SMB */
1633	value = CSMB_CTRL_CMB_EN | CSMB_CTRL_SMB_EN;
1634	iowrite32(value, hw->hw_addr + REG_CSMB_CTRL);
1635
1636	value = ioread32(adapter->hw.hw_addr + REG_ISR);
1637	if (unlikely((value & ISR_PHY_LINKDOWN) != 0))
1638		value = 1;	/* config failed */
1639	else
1640		value = 0;
1641
1642	/* clear all interrupt status */
1643	iowrite32(0x3fffffff, adapter->hw.hw_addr + REG_ISR);
1644	iowrite32(0, adapter->hw.hw_addr + REG_ISR);
1645	return value;
1646}
1647
1648/*
1649 * atl1_pcie_patch - Patch for PCIE module
1650 */
1651static void atl1_pcie_patch(struct atl1_adapter *adapter)
1652{
1653	u32 value;
1654
1655	/* much vendor magic here */
1656	value = 0x6500;
1657	iowrite32(value, adapter->hw.hw_addr + 0x12FC);
1658	/* pcie flow control mode change */
1659	value = ioread32(adapter->hw.hw_addr + 0x1008);
1660	value |= 0x8000;
1661	iowrite32(value, adapter->hw.hw_addr + 0x1008);
1662}
1663
1664/*
1665 * When ACPI resume on some VIA MotherBoard, the Interrupt Disable bit/0x400
1666 * on PCI Command register is disable.
1667 * The function enable this bit.
1668 * Brackett, 2006/03/15
1669 */
1670static void atl1_via_workaround(struct atl1_adapter *adapter)
1671{
1672	unsigned long value;
1673
1674	value = ioread16(adapter->hw.hw_addr + PCI_COMMAND);
1675	if (value & PCI_COMMAND_INTX_DISABLE)
1676		value &= ~PCI_COMMAND_INTX_DISABLE;
1677	iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND);
1678}
1679
1680static void atl1_inc_smb(struct atl1_adapter *adapter)
1681{
1682	struct net_device *netdev = adapter->netdev;
1683	struct stats_msg_block *smb = adapter->smb.smb;
1684
1685	/* Fill out the OS statistics structure */
1686	adapter->soft_stats.rx_packets += smb->rx_ok;
1687	adapter->soft_stats.tx_packets += smb->tx_ok;
1688	adapter->soft_stats.rx_bytes += smb->rx_byte_cnt;
1689	adapter->soft_stats.tx_bytes += smb->tx_byte_cnt;
1690	adapter->soft_stats.multicast += smb->rx_mcast;
1691	adapter->soft_stats.collisions += (smb->tx_1_col + smb->tx_2_col * 2 +
1692		smb->tx_late_col + smb->tx_abort_col * adapter->hw.max_retry);
1693
1694	/* Rx Errors */
1695	adapter->soft_stats.rx_errors += (smb->rx_frag + smb->rx_fcs_err +
1696		smb->rx_len_err + smb->rx_sz_ov + smb->rx_rxf_ov +
1697		smb->rx_rrd_ov + smb->rx_align_err);
1698	adapter->soft_stats.rx_fifo_errors += smb->rx_rxf_ov;
1699	adapter->soft_stats.rx_length_errors += smb->rx_len_err;
1700	adapter->soft_stats.rx_crc_errors += smb->rx_fcs_err;
1701	adapter->soft_stats.rx_frame_errors += smb->rx_align_err;
1702	adapter->soft_stats.rx_missed_errors += (smb->rx_rrd_ov +
1703		smb->rx_rxf_ov);
1704
1705	adapter->soft_stats.rx_pause += smb->rx_pause;
1706	adapter->soft_stats.rx_rrd_ov += smb->rx_rrd_ov;
1707	adapter->soft_stats.rx_trunc += smb->rx_sz_ov;
1708
1709	/* Tx Errors */
1710	adapter->soft_stats.tx_errors += (smb->tx_late_col +
1711		smb->tx_abort_col + smb->tx_underrun + smb->tx_trunc);
1712	adapter->soft_stats.tx_fifo_errors += smb->tx_underrun;
1713	adapter->soft_stats.tx_aborted_errors += smb->tx_abort_col;
1714	adapter->soft_stats.tx_window_errors += smb->tx_late_col;
1715
1716	adapter->soft_stats.excecol += smb->tx_abort_col;
1717	adapter->soft_stats.deffer += smb->tx_defer;
1718	adapter->soft_stats.scc += smb->tx_1_col;
1719	adapter->soft_stats.mcc += smb->tx_2_col;
1720	adapter->soft_stats.latecol += smb->tx_late_col;
1721	adapter->soft_stats.tx_underun += smb->tx_underrun;
1722	adapter->soft_stats.tx_trunc += smb->tx_trunc;
1723	adapter->soft_stats.tx_pause += smb->tx_pause;
1724
1725	netdev->stats.rx_packets = adapter->soft_stats.rx_packets;
1726	netdev->stats.tx_packets = adapter->soft_stats.tx_packets;
1727	netdev->stats.rx_bytes = adapter->soft_stats.rx_bytes;
1728	netdev->stats.tx_bytes = adapter->soft_stats.tx_bytes;
1729	netdev->stats.multicast = adapter->soft_stats.multicast;
1730	netdev->stats.collisions = adapter->soft_stats.collisions;
1731	netdev->stats.rx_errors = adapter->soft_stats.rx_errors;
1732	netdev->stats.rx_over_errors =
1733		adapter->soft_stats.rx_missed_errors;
1734	netdev->stats.rx_length_errors =
1735		adapter->soft_stats.rx_length_errors;
1736	netdev->stats.rx_crc_errors = adapter->soft_stats.rx_crc_errors;
1737	netdev->stats.rx_frame_errors =
1738		adapter->soft_stats.rx_frame_errors;
1739	netdev->stats.rx_fifo_errors = adapter->soft_stats.rx_fifo_errors;
1740	netdev->stats.rx_missed_errors =
1741		adapter->soft_stats.rx_missed_errors;
1742	netdev->stats.tx_errors = adapter->soft_stats.tx_errors;
1743	netdev->stats.tx_fifo_errors = adapter->soft_stats.tx_fifo_errors;
1744	netdev->stats.tx_aborted_errors =
1745		adapter->soft_stats.tx_aborted_errors;
1746	netdev->stats.tx_window_errors =
1747		adapter->soft_stats.tx_window_errors;
1748	netdev->stats.tx_carrier_errors =
1749		adapter->soft_stats.tx_carrier_errors;
1750}
1751
1752static void atl1_update_mailbox(struct atl1_adapter *adapter)
1753{
1754	unsigned long flags;
1755	u32 tpd_next_to_use;
1756	u32 rfd_next_to_use;
1757	u32 rrd_next_to_clean;
1758	u32 value;
1759
1760	spin_lock_irqsave(&adapter->mb_lock, flags);
1761
1762	tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
1763	rfd_next_to_use = atomic_read(&adapter->rfd_ring.next_to_use);
1764	rrd_next_to_clean = atomic_read(&adapter->rrd_ring.next_to_clean);
1765
1766	value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
1767		MB_RFD_PROD_INDX_SHIFT) |
1768		((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
1769		MB_RRD_CONS_INDX_SHIFT) |
1770		((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
1771		MB_TPD_PROD_INDX_SHIFT);
1772	iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
1773
1774	spin_unlock_ir

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