/drivers/media/video/tvp7002.c

https://bitbucket.org/ndreys/linux-sunxi · C · 1100 lines · 739 code · 116 blank · 245 comment · 58 complexity · 029656a1d6efe30747738e0d36db4f7a MD5 · raw file

  1. /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics
  2. * Digitizer with Horizontal PLL registers
  3. *
  4. * Copyright (C) 2009 Texas Instruments Inc
  5. * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>
  6. *
  7. * This code is partially based upon the TVP5150 driver
  8. * written by Mauro Carvalho Chehab (mchehab@infradead.org),
  9. * the TVP514x driver written by Vaibhav Hiremath <hvaibhav@ti.com>
  10. * and the TVP7002 driver in the TI LSP 2.10.00.14. Revisions by
  11. * Muralidharan Karicheri and Snehaprabha Narnakaje (TI).
  12. *
  13. * This program is free software; you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License as published by
  15. * the Free Software Foundation; either version 2 of the License, or
  16. * (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  26. */
  27. #include <linux/delay.h>
  28. #include <linux/i2c.h>
  29. #include <linux/slab.h>
  30. #include <linux/videodev2.h>
  31. #include <media/tvp7002.h>
  32. #include <media/v4l2-device.h>
  33. #include <media/v4l2-chip-ident.h>
  34. #include <media/v4l2-common.h>
  35. #include <media/v4l2-ctrls.h>
  36. #include "tvp7002_reg.h"
  37. MODULE_DESCRIPTION("TI TVP7002 Video and Graphics Digitizer driver");
  38. MODULE_AUTHOR("Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>");
  39. MODULE_LICENSE("GPL");
  40. /* Module Name */
  41. #define TVP7002_MODULE_NAME "tvp7002"
  42. /* I2C retry attempts */
  43. #define I2C_RETRY_COUNT (5)
  44. /* End of registers */
  45. #define TVP7002_EOR 0x5c
  46. /* Read write definition for registers */
  47. #define TVP7002_READ 0
  48. #define TVP7002_WRITE 1
  49. #define TVP7002_RESERVED 2
  50. /* Interlaced vs progressive mask and shift */
  51. #define TVP7002_IP_SHIFT 5
  52. #define TVP7002_INPR_MASK (0x01 << TVP7002_IP_SHIFT)
  53. /* Shift for CPL and LPF registers */
  54. #define TVP7002_CL_SHIFT 8
  55. #define TVP7002_CL_MASK 0x0f
  56. /* Debug functions */
  57. static int debug;
  58. module_param(debug, bool, 0644);
  59. MODULE_PARM_DESC(debug, "Debug level (0-2)");
  60. /* Structure for register values */
  61. struct i2c_reg_value {
  62. u8 reg;
  63. u8 value;
  64. u8 type;
  65. };
  66. /*
  67. * Register default values (according to tvp7002 datasheet)
  68. * In the case of read-only registers, the value (0xff) is
  69. * never written. R/W functionality is controlled by the
  70. * writable bit in the register struct definition.
  71. */
  72. static const struct i2c_reg_value tvp7002_init_default[] = {
  73. { TVP7002_CHIP_REV, 0xff, TVP7002_READ },
  74. { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE },
  75. { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE },
  76. { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE },
  77. { TVP7002_HPLL_PHASE_SEL, 0x80, TVP7002_WRITE },
  78. { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
  79. { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
  80. { TVP7002_HSYNC_OUT_W, 0x60, TVP7002_WRITE },
  81. { TVP7002_B_FINE_GAIN, 0x00, TVP7002_WRITE },
  82. { TVP7002_G_FINE_GAIN, 0x00, TVP7002_WRITE },
  83. { TVP7002_R_FINE_GAIN, 0x00, TVP7002_WRITE },
  84. { TVP7002_B_FINE_OFF_MSBS, 0x80, TVP7002_WRITE },
  85. { TVP7002_G_FINE_OFF_MSBS, 0x80, TVP7002_WRITE },
  86. { TVP7002_R_FINE_OFF_MSBS, 0x80, TVP7002_WRITE },
  87. { TVP7002_SYNC_CTL_1, 0x20, TVP7002_WRITE },
  88. { TVP7002_HPLL_AND_CLAMP_CTL, 0x2e, TVP7002_WRITE },
  89. { TVP7002_SYNC_ON_G_THRS, 0x5d, TVP7002_WRITE },
  90. { TVP7002_SYNC_SEPARATOR_THRS, 0x47, TVP7002_WRITE },
  91. { TVP7002_HPLL_PRE_COAST, 0x00, TVP7002_WRITE },
  92. { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
  93. { TVP7002_SYNC_DETECT_STAT, 0xff, TVP7002_READ },
  94. { TVP7002_OUT_FORMATTER, 0x47, TVP7002_WRITE },
  95. { TVP7002_MISC_CTL_1, 0x01, TVP7002_WRITE },
  96. { TVP7002_MISC_CTL_2, 0x00, TVP7002_WRITE },
  97. { TVP7002_MISC_CTL_3, 0x01, TVP7002_WRITE },
  98. { TVP7002_IN_MUX_SEL_1, 0x00, TVP7002_WRITE },
  99. { TVP7002_IN_MUX_SEL_2, 0x67, TVP7002_WRITE },
  100. { TVP7002_B_AND_G_COARSE_GAIN, 0x77, TVP7002_WRITE },
  101. { TVP7002_R_COARSE_GAIN, 0x07, TVP7002_WRITE },
  102. { TVP7002_FINE_OFF_LSBS, 0x00, TVP7002_WRITE },
  103. { TVP7002_B_COARSE_OFF, 0x10, TVP7002_WRITE },
  104. { TVP7002_G_COARSE_OFF, 0x10, TVP7002_WRITE },
  105. { TVP7002_R_COARSE_OFF, 0x10, TVP7002_WRITE },
  106. { TVP7002_HSOUT_OUT_START, 0x08, TVP7002_WRITE },
  107. { TVP7002_MISC_CTL_4, 0x00, TVP7002_WRITE },
  108. { TVP7002_B_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ },
  109. { TVP7002_G_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ },
  110. { TVP7002_R_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ },
  111. { TVP7002_AUTO_LVL_CTL_ENABLE, 0x80, TVP7002_WRITE },
  112. { TVP7002_DGTL_ALC_OUT_MSBS, 0xff, TVP7002_READ },
  113. { TVP7002_AUTO_LVL_CTL_FILTER, 0x53, TVP7002_WRITE },
  114. { 0x29, 0x08, TVP7002_RESERVED },
  115. { TVP7002_FINE_CLAMP_CTL, 0x07, TVP7002_WRITE },
  116. /* PWR_CTL is controlled only by the probe and reset functions */
  117. { TVP7002_PWR_CTL, 0x00, TVP7002_RESERVED },
  118. { TVP7002_ADC_SETUP, 0x50, TVP7002_WRITE },
  119. { TVP7002_COARSE_CLAMP_CTL, 0x00, TVP7002_WRITE },
  120. { TVP7002_SOG_CLAMP, 0x80, TVP7002_WRITE },
  121. { TVP7002_RGB_COARSE_CLAMP_CTL, 0x00, TVP7002_WRITE },
  122. { TVP7002_SOG_COARSE_CLAMP_CTL, 0x04, TVP7002_WRITE },
  123. { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
  124. { 0x32, 0x18, TVP7002_RESERVED },
  125. { 0x33, 0x60, TVP7002_RESERVED },
  126. { TVP7002_MVIS_STRIPPER_W, 0xff, TVP7002_RESERVED },
  127. { TVP7002_VSYNC_ALGN, 0x10, TVP7002_WRITE },
  128. { TVP7002_SYNC_BYPASS, 0x00, TVP7002_WRITE },
  129. { TVP7002_L_FRAME_STAT_LSBS, 0xff, TVP7002_READ },
  130. { TVP7002_L_FRAME_STAT_MSBS, 0xff, TVP7002_READ },
  131. { TVP7002_CLK_L_STAT_LSBS, 0xff, TVP7002_READ },
  132. { TVP7002_CLK_L_STAT_MSBS, 0xff, TVP7002_READ },
  133. { TVP7002_HSYNC_W, 0xff, TVP7002_READ },
  134. { TVP7002_VSYNC_W, 0xff, TVP7002_READ },
  135. { TVP7002_L_LENGTH_TOL, 0x03, TVP7002_WRITE },
  136. { 0x3e, 0x60, TVP7002_RESERVED },
  137. { TVP7002_VIDEO_BWTH_CTL, 0x01, TVP7002_WRITE },
  138. { TVP7002_AVID_START_PIXEL_LSBS, 0x01, TVP7002_WRITE },
  139. { TVP7002_AVID_START_PIXEL_MSBS, 0x2c, TVP7002_WRITE },
  140. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x06, TVP7002_WRITE },
  141. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x2c, TVP7002_WRITE },
  142. { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE },
  143. { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
  144. { TVP7002_VBLK_F_0_DURATION, 0x1e, TVP7002_WRITE },
  145. { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
  146. { TVP7002_FBIT_F_0_START_L_OFF, 0x00, TVP7002_WRITE },
  147. { TVP7002_FBIT_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
  148. { TVP7002_YUV_Y_G_COEF_LSBS, 0xe3, TVP7002_WRITE },
  149. { TVP7002_YUV_Y_G_COEF_MSBS, 0x16, TVP7002_WRITE },
  150. { TVP7002_YUV_Y_B_COEF_LSBS, 0x4f, TVP7002_WRITE },
  151. { TVP7002_YUV_Y_B_COEF_MSBS, 0x02, TVP7002_WRITE },
  152. { TVP7002_YUV_Y_R_COEF_LSBS, 0xce, TVP7002_WRITE },
  153. { TVP7002_YUV_Y_R_COEF_MSBS, 0x06, TVP7002_WRITE },
  154. { TVP7002_YUV_U_G_COEF_LSBS, 0xab, TVP7002_WRITE },
  155. { TVP7002_YUV_U_G_COEF_MSBS, 0xf3, TVP7002_WRITE },
  156. { TVP7002_YUV_U_B_COEF_LSBS, 0x00, TVP7002_WRITE },
  157. { TVP7002_YUV_U_B_COEF_MSBS, 0x10, TVP7002_WRITE },
  158. { TVP7002_YUV_U_R_COEF_LSBS, 0x55, TVP7002_WRITE },
  159. { TVP7002_YUV_U_R_COEF_MSBS, 0xfc, TVP7002_WRITE },
  160. { TVP7002_YUV_V_G_COEF_LSBS, 0x78, TVP7002_WRITE },
  161. { TVP7002_YUV_V_G_COEF_MSBS, 0xf1, TVP7002_WRITE },
  162. { TVP7002_YUV_V_B_COEF_LSBS, 0x88, TVP7002_WRITE },
  163. { TVP7002_YUV_V_B_COEF_MSBS, 0xfe, TVP7002_WRITE },
  164. { TVP7002_YUV_V_R_COEF_LSBS, 0x00, TVP7002_WRITE },
  165. { TVP7002_YUV_V_R_COEF_MSBS, 0x10, TVP7002_WRITE },
  166. /* This signals end of register values */
  167. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  168. };
  169. /* Register parameters for 480P */
  170. static const struct i2c_reg_value tvp7002_parms_480P[] = {
  171. { TVP7002_HPLL_FDBK_DIV_MSBS, 0x35, TVP7002_WRITE },
  172. { TVP7002_HPLL_FDBK_DIV_LSBS, 0xa0, TVP7002_WRITE },
  173. { TVP7002_HPLL_CRTL, 0x02, TVP7002_WRITE },
  174. { TVP7002_HPLL_PHASE_SEL, 0x14, TVP7002_WRITE },
  175. { TVP7002_AVID_START_PIXEL_LSBS, 0x91, TVP7002_WRITE },
  176. { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE },
  177. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0B, TVP7002_WRITE },
  178. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x00, TVP7002_WRITE },
  179. { TVP7002_VBLK_F_0_START_L_OFF, 0x03, TVP7002_WRITE },
  180. { TVP7002_VBLK_F_1_START_L_OFF, 0x01, TVP7002_WRITE },
  181. { TVP7002_VBLK_F_0_DURATION, 0x13, TVP7002_WRITE },
  182. { TVP7002_VBLK_F_1_DURATION, 0x13, TVP7002_WRITE },
  183. { TVP7002_ALC_PLACEMENT, 0x18, TVP7002_WRITE },
  184. { TVP7002_CLAMP_START, 0x06, TVP7002_WRITE },
  185. { TVP7002_CLAMP_W, 0x10, TVP7002_WRITE },
  186. { TVP7002_HPLL_PRE_COAST, 0x03, TVP7002_WRITE },
  187. { TVP7002_HPLL_POST_COAST, 0x03, TVP7002_WRITE },
  188. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  189. };
  190. /* Register parameters for 576P */
  191. static const struct i2c_reg_value tvp7002_parms_576P[] = {
  192. { TVP7002_HPLL_FDBK_DIV_MSBS, 0x36, TVP7002_WRITE },
  193. { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE },
  194. { TVP7002_HPLL_CRTL, 0x18, TVP7002_WRITE },
  195. { TVP7002_HPLL_PHASE_SEL, 0x14, TVP7002_WRITE },
  196. { TVP7002_AVID_START_PIXEL_LSBS, 0x9B, TVP7002_WRITE },
  197. { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE },
  198. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0F, TVP7002_WRITE },
  199. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x00, TVP7002_WRITE },
  200. { TVP7002_VBLK_F_0_START_L_OFF, 0x00, TVP7002_WRITE },
  201. { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
  202. { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE },
  203. { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
  204. { TVP7002_ALC_PLACEMENT, 0x18, TVP7002_WRITE },
  205. { TVP7002_CLAMP_START, 0x06, TVP7002_WRITE },
  206. { TVP7002_CLAMP_W, 0x10, TVP7002_WRITE },
  207. { TVP7002_HPLL_PRE_COAST, 0x03, TVP7002_WRITE },
  208. { TVP7002_HPLL_POST_COAST, 0x03, TVP7002_WRITE },
  209. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  210. };
  211. /* Register parameters for 1080I60 */
  212. static const struct i2c_reg_value tvp7002_parms_1080I60[] = {
  213. { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE },
  214. { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE },
  215. { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
  216. { TVP7002_HPLL_PHASE_SEL, 0x14, TVP7002_WRITE },
  217. { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
  218. { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
  219. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
  220. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE },
  221. { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
  222. { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
  223. { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
  224. { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE },
  225. { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
  226. { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
  227. { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
  228. { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
  229. { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
  230. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  231. };
  232. /* Register parameters for 1080P60 */
  233. static const struct i2c_reg_value tvp7002_parms_1080P60[] = {
  234. { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE },
  235. { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE },
  236. { TVP7002_HPLL_CRTL, 0xE0, TVP7002_WRITE },
  237. { TVP7002_HPLL_PHASE_SEL, 0x14, TVP7002_WRITE },
  238. { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
  239. { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
  240. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
  241. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE },
  242. { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
  243. { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
  244. { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
  245. { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE },
  246. { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
  247. { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
  248. { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
  249. { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
  250. { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
  251. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  252. };
  253. /* Register parameters for 1080I50 */
  254. static const struct i2c_reg_value tvp7002_parms_1080I50[] = {
  255. { TVP7002_HPLL_FDBK_DIV_MSBS, 0xa5, TVP7002_WRITE },
  256. { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE },
  257. { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
  258. { TVP7002_HPLL_PHASE_SEL, 0x14, TVP7002_WRITE },
  259. { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
  260. { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
  261. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
  262. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE },
  263. { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
  264. { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
  265. { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
  266. { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE },
  267. { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
  268. { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
  269. { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
  270. { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
  271. { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
  272. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  273. };
  274. /* Register parameters for 720P60 */
  275. static const struct i2c_reg_value tvp7002_parms_720P60[] = {
  276. { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE },
  277. { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE },
  278. { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE },
  279. { TVP7002_HPLL_PHASE_SEL, 0x16, TVP7002_WRITE },
  280. { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE },
  281. { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
  282. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE },
  283. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x06, TVP7002_WRITE },
  284. { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE },
  285. { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
  286. { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE },
  287. { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
  288. { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
  289. { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
  290. { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
  291. { TVP7002_HPLL_PRE_COAST, 0x00, TVP7002_WRITE },
  292. { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
  293. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  294. };
  295. /* Register parameters for 720P50 */
  296. static const struct i2c_reg_value tvp7002_parms_720P50[] = {
  297. { TVP7002_HPLL_FDBK_DIV_MSBS, 0x7b, TVP7002_WRITE },
  298. { TVP7002_HPLL_FDBK_DIV_LSBS, 0xc0, TVP7002_WRITE },
  299. { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
  300. { TVP7002_HPLL_PHASE_SEL, 0x16, TVP7002_WRITE },
  301. { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE },
  302. { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
  303. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE },
  304. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x06, TVP7002_WRITE },
  305. { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE },
  306. { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
  307. { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE },
  308. { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
  309. { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
  310. { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
  311. { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
  312. { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
  313. { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
  314. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  315. };
  316. /* Preset definition for handling device operation */
  317. struct tvp7002_preset_definition {
  318. u32 preset;
  319. const struct i2c_reg_value *p_settings;
  320. enum v4l2_colorspace color_space;
  321. enum v4l2_field scanmode;
  322. u16 progressive;
  323. u16 lines_per_frame;
  324. u16 cpl_min;
  325. u16 cpl_max;
  326. };
  327. /* Struct list for digital video presets */
  328. static const struct tvp7002_preset_definition tvp7002_presets[] = {
  329. {
  330. V4L2_DV_720P60,
  331. tvp7002_parms_720P60,
  332. V4L2_COLORSPACE_REC709,
  333. V4L2_FIELD_NONE,
  334. 1,
  335. 0x2EE,
  336. 135,
  337. 153
  338. },
  339. {
  340. V4L2_DV_1080I60,
  341. tvp7002_parms_1080I60,
  342. V4L2_COLORSPACE_REC709,
  343. V4L2_FIELD_INTERLACED,
  344. 0,
  345. 0x465,
  346. 181,
  347. 205
  348. },
  349. {
  350. V4L2_DV_1080I50,
  351. tvp7002_parms_1080I50,
  352. V4L2_COLORSPACE_REC709,
  353. V4L2_FIELD_INTERLACED,
  354. 0,
  355. 0x465,
  356. 217,
  357. 245
  358. },
  359. {
  360. V4L2_DV_720P50,
  361. tvp7002_parms_720P50,
  362. V4L2_COLORSPACE_REC709,
  363. V4L2_FIELD_NONE,
  364. 1,
  365. 0x2EE,
  366. 163,
  367. 183
  368. },
  369. {
  370. V4L2_DV_1080P60,
  371. tvp7002_parms_1080P60,
  372. V4L2_COLORSPACE_REC709,
  373. V4L2_FIELD_NONE,
  374. 1,
  375. 0x465,
  376. 90,
  377. 102
  378. },
  379. {
  380. V4L2_DV_480P59_94,
  381. tvp7002_parms_480P,
  382. V4L2_COLORSPACE_SMPTE170M,
  383. V4L2_FIELD_NONE,
  384. 1,
  385. 0x20D,
  386. 0xffff,
  387. 0xffff
  388. },
  389. {
  390. V4L2_DV_576P50,
  391. tvp7002_parms_576P,
  392. V4L2_COLORSPACE_SMPTE170M,
  393. V4L2_FIELD_NONE,
  394. 1,
  395. 0x271,
  396. 0xffff,
  397. 0xffff
  398. }
  399. };
  400. #define NUM_PRESETS ARRAY_SIZE(tvp7002_presets)
  401. /* Device definition */
  402. struct tvp7002 {
  403. struct v4l2_subdev sd;
  404. struct v4l2_ctrl_handler hdl;
  405. const struct tvp7002_config *pdata;
  406. int ver;
  407. int streaming;
  408. const struct tvp7002_preset_definition *current_preset;
  409. };
  410. /*
  411. * to_tvp7002 - Obtain device handler TVP7002
  412. * @sd: ptr to v4l2_subdev struct
  413. *
  414. * Returns device handler tvp7002.
  415. */
  416. static inline struct tvp7002 *to_tvp7002(struct v4l2_subdev *sd)
  417. {
  418. return container_of(sd, struct tvp7002, sd);
  419. }
  420. static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
  421. {
  422. return &container_of(ctrl->handler, struct tvp7002, hdl)->sd;
  423. }
  424. /*
  425. * tvp7002_read - Read a value from a register in an TVP7002
  426. * @sd: ptr to v4l2_subdev struct
  427. * @addr: TVP7002 register address
  428. * @dst: pointer to 8-bit destination
  429. *
  430. * Returns value read if successful, or non-zero (-1) otherwise.
  431. */
  432. static int tvp7002_read(struct v4l2_subdev *sd, u8 addr, u8 *dst)
  433. {
  434. struct i2c_client *c = v4l2_get_subdevdata(sd);
  435. int retry;
  436. int error;
  437. for (retry = 0; retry < I2C_RETRY_COUNT; retry++) {
  438. error = i2c_smbus_read_byte_data(c, addr);
  439. if (error >= 0) {
  440. *dst = (u8)error;
  441. return 0;
  442. }
  443. msleep_interruptible(10);
  444. }
  445. v4l2_err(sd, "TVP7002 read error %d\n", error);
  446. return error;
  447. }
  448. /*
  449. * tvp7002_read_err() - Read a register value with error code
  450. * @sd: pointer to standard V4L2 sub-device structure
  451. * @reg: destination register
  452. * @val: value to be read
  453. * @err: pointer to error value
  454. *
  455. * Read a value in a register and save error value in pointer.
  456. * Also update the register table if successful
  457. */
  458. static inline void tvp7002_read_err(struct v4l2_subdev *sd, u8 reg,
  459. u8 *dst, int *err)
  460. {
  461. if (!*err)
  462. *err = tvp7002_read(sd, reg, dst);
  463. }
  464. /*
  465. * tvp7002_write() - Write a value to a register in TVP7002
  466. * @sd: ptr to v4l2_subdev struct
  467. * @addr: TVP7002 register address
  468. * @value: value to be written to the register
  469. *
  470. * Write a value to a register in an TVP7002 decoder device.
  471. * Returns zero if successful, or non-zero otherwise.
  472. */
  473. static int tvp7002_write(struct v4l2_subdev *sd, u8 addr, u8 value)
  474. {
  475. struct i2c_client *c;
  476. int retry;
  477. int error;
  478. c = v4l2_get_subdevdata(sd);
  479. for (retry = 0; retry < I2C_RETRY_COUNT; retry++) {
  480. error = i2c_smbus_write_byte_data(c, addr, value);
  481. if (error >= 0)
  482. return 0;
  483. v4l2_warn(sd, "Write: retry ... %d\n", retry);
  484. msleep_interruptible(10);
  485. }
  486. v4l2_err(sd, "TVP7002 write error %d\n", error);
  487. return error;
  488. }
  489. /*
  490. * tvp7002_write_err() - Write a register value with error code
  491. * @sd: pointer to standard V4L2 sub-device structure
  492. * @reg: destination register
  493. * @val: value to be written
  494. * @err: pointer to error value
  495. *
  496. * Write a value in a register and save error value in pointer.
  497. * Also update the register table if successful
  498. */
  499. static inline void tvp7002_write_err(struct v4l2_subdev *sd, u8 reg,
  500. u8 val, int *err)
  501. {
  502. if (!*err)
  503. *err = tvp7002_write(sd, reg, val);
  504. }
  505. /*
  506. * tvp7002_g_chip_ident() - Get chip identification number
  507. * @sd: ptr to v4l2_subdev struct
  508. * @chip: ptr to v4l2_dbg_chip_ident struct
  509. *
  510. * Obtains the chip's identification number.
  511. * Returns zero or -EINVAL if read operation fails.
  512. */
  513. static int tvp7002_g_chip_ident(struct v4l2_subdev *sd,
  514. struct v4l2_dbg_chip_ident *chip)
  515. {
  516. u8 rev;
  517. int error;
  518. struct i2c_client *client = v4l2_get_subdevdata(sd);
  519. error = tvp7002_read(sd, TVP7002_CHIP_REV, &rev);
  520. if (error < 0)
  521. return error;
  522. return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_TVP7002, rev);
  523. }
  524. /*
  525. * tvp7002_write_inittab() - Write initialization values
  526. * @sd: ptr to v4l2_subdev struct
  527. * @regs: ptr to i2c_reg_value struct
  528. *
  529. * Write initialization values.
  530. * Returns zero or -EINVAL if read operation fails.
  531. */
  532. static int tvp7002_write_inittab(struct v4l2_subdev *sd,
  533. const struct i2c_reg_value *regs)
  534. {
  535. int error = 0;
  536. /* Initialize the first (defined) registers */
  537. while (TVP7002_EOR != regs->reg) {
  538. if (TVP7002_WRITE == regs->type)
  539. tvp7002_write_err(sd, regs->reg, regs->value, &error);
  540. regs++;
  541. }
  542. return error;
  543. }
  544. /*
  545. * tvp7002_s_dv_preset() - Set digital video preset
  546. * @sd: ptr to v4l2_subdev struct
  547. * @dv_preset: ptr to v4l2_dv_preset struct
  548. *
  549. * Set the digital video preset for a TVP7002 decoder device.
  550. * Returns zero when successful or -EINVAL if register access fails.
  551. */
  552. static int tvp7002_s_dv_preset(struct v4l2_subdev *sd,
  553. struct v4l2_dv_preset *dv_preset)
  554. {
  555. struct tvp7002 *device = to_tvp7002(sd);
  556. u32 preset;
  557. int i;
  558. for (i = 0; i < NUM_PRESETS; i++) {
  559. preset = tvp7002_presets[i].preset;
  560. if (preset == dv_preset->preset) {
  561. device->current_preset = &tvp7002_presets[i];
  562. return tvp7002_write_inittab(sd, tvp7002_presets[i].p_settings);
  563. }
  564. }
  565. return -EINVAL;
  566. }
  567. /*
  568. * tvp7002_s_ctrl() - Set a control
  569. * @ctrl: ptr to v4l2_ctrl struct
  570. *
  571. * Set a control in TVP7002 decoder device.
  572. * Returns zero when successful or -EINVAL if register access fails.
  573. */
  574. static int tvp7002_s_ctrl(struct v4l2_ctrl *ctrl)
  575. {
  576. struct v4l2_subdev *sd = to_sd(ctrl);
  577. int error = 0;
  578. switch (ctrl->id) {
  579. case V4L2_CID_GAIN:
  580. tvp7002_write_err(sd, TVP7002_R_FINE_GAIN, ctrl->val, &error);
  581. tvp7002_write_err(sd, TVP7002_G_FINE_GAIN, ctrl->val, &error);
  582. tvp7002_write_err(sd, TVP7002_B_FINE_GAIN, ctrl->val, &error);
  583. return error;
  584. }
  585. return -EINVAL;
  586. }
  587. /*
  588. * tvp7002_mbus_fmt() - V4L2 decoder interface handler for try/s/g_mbus_fmt
  589. * @sd: pointer to standard V4L2 sub-device structure
  590. * @f: pointer to mediabus format structure
  591. *
  592. * Negotiate the image capture size and mediabus format.
  593. * There is only one possible format, so this single function works for
  594. * get, set and try.
  595. */
  596. static int tvp7002_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *f)
  597. {
  598. struct tvp7002 *device = to_tvp7002(sd);
  599. struct v4l2_dv_enum_preset e_preset;
  600. int error;
  601. /* Calculate height and width based on current standard */
  602. error = v4l_fill_dv_preset_info(device->current_preset->preset, &e_preset);
  603. if (error)
  604. return error;
  605. f->width = e_preset.width;
  606. f->height = e_preset.height;
  607. f->code = V4L2_MBUS_FMT_YUYV10_1X20;
  608. f->field = device->current_preset->scanmode;
  609. f->colorspace = device->current_preset->color_space;
  610. v4l2_dbg(1, debug, sd, "MBUS_FMT: Width - %d, Height - %d",
  611. f->width, f->height);
  612. return 0;
  613. }
  614. /*
  615. * tvp7002_query_dv_preset() - query DV preset
  616. * @sd: pointer to standard V4L2 sub-device structure
  617. * @qpreset: standard V4L2 v4l2_dv_preset structure
  618. *
  619. * Returns the current DV preset by TVP7002. If no active input is
  620. * detected, returns -EINVAL
  621. */
  622. static int tvp7002_query_dv_preset(struct v4l2_subdev *sd,
  623. struct v4l2_dv_preset *qpreset)
  624. {
  625. const struct tvp7002_preset_definition *presets = tvp7002_presets;
  626. struct tvp7002 *device;
  627. u8 progressive;
  628. u32 lpfr;
  629. u32 cpln;
  630. int error = 0;
  631. u8 lpf_lsb;
  632. u8 lpf_msb;
  633. u8 cpl_lsb;
  634. u8 cpl_msb;
  635. int index;
  636. device = to_tvp7002(sd);
  637. /* Read standards from device registers */
  638. tvp7002_read_err(sd, TVP7002_L_FRAME_STAT_LSBS, &lpf_lsb, &error);
  639. tvp7002_read_err(sd, TVP7002_L_FRAME_STAT_MSBS, &lpf_msb, &error);
  640. if (error < 0)
  641. return error;
  642. tvp7002_read_err(sd, TVP7002_CLK_L_STAT_LSBS, &cpl_lsb, &error);
  643. tvp7002_read_err(sd, TVP7002_CLK_L_STAT_MSBS, &cpl_msb, &error);
  644. if (error < 0)
  645. return error;
  646. /* Get lines per frame, clocks per line and interlaced/progresive */
  647. lpfr = lpf_lsb | ((TVP7002_CL_MASK & lpf_msb) << TVP7002_CL_SHIFT);
  648. cpln = cpl_lsb | ((TVP7002_CL_MASK & cpl_msb) << TVP7002_CL_SHIFT);
  649. progressive = (lpf_msb & TVP7002_INPR_MASK) >> TVP7002_IP_SHIFT;
  650. /* Do checking of video modes */
  651. for (index = 0; index < NUM_PRESETS; index++, presets++)
  652. if (lpfr == presets->lines_per_frame &&
  653. progressive == presets->progressive) {
  654. if (presets->cpl_min == 0xffff)
  655. break;
  656. if (cpln >= presets->cpl_min && cpln <= presets->cpl_max)
  657. break;
  658. }
  659. if (index == NUM_PRESETS) {
  660. v4l2_dbg(1, debug, sd, "detection failed: lpf = %x, cpl = %x\n",
  661. lpfr, cpln);
  662. /* Could not detect a signal, so return the 'invalid' preset */
  663. qpreset->preset = V4L2_DV_INVALID;
  664. return 0;
  665. }
  666. /* Set values in found preset */
  667. qpreset->preset = presets->preset;
  668. /* Update lines per frame and clocks per line info */
  669. v4l2_dbg(1, debug, sd, "detected preset: %d\n", presets->preset);
  670. return 0;
  671. }
  672. #ifdef CONFIG_VIDEO_ADV_DEBUG
  673. /*
  674. * tvp7002_g_register() - Get the value of a register
  675. * @sd: ptr to v4l2_subdev struct
  676. * @reg: ptr to v4l2_dbg_register struct
  677. *
  678. * Get the value of a TVP7002 decoder device register.
  679. * Returns zero when successful, -EINVAL if register read fails or
  680. * access to I2C client fails, -EPERM if the call is not allowed
  681. * by disabled CAP_SYS_ADMIN.
  682. */
  683. static int tvp7002_g_register(struct v4l2_subdev *sd,
  684. struct v4l2_dbg_register *reg)
  685. {
  686. struct i2c_client *client = v4l2_get_subdevdata(sd);
  687. u8 val;
  688. int ret;
  689. if (!v4l2_chip_match_i2c_client(client, &reg->match))
  690. return -EINVAL;
  691. if (!capable(CAP_SYS_ADMIN))
  692. return -EPERM;
  693. ret = tvp7002_read(sd, reg->reg & 0xff, &val);
  694. reg->val = val;
  695. return ret;
  696. }
  697. /*
  698. * tvp7002_s_register() - set a control
  699. * @sd: ptr to v4l2_subdev struct
  700. * @reg: ptr to v4l2_dbg_register struct
  701. *
  702. * Get the value of a TVP7002 decoder device register.
  703. * Returns zero when successful, -EINVAL if register read fails or
  704. * -EPERM if call not allowed.
  705. */
  706. static int tvp7002_s_register(struct v4l2_subdev *sd,
  707. struct v4l2_dbg_register *reg)
  708. {
  709. struct i2c_client *client = v4l2_get_subdevdata(sd);
  710. if (!v4l2_chip_match_i2c_client(client, &reg->match))
  711. return -EINVAL;
  712. if (!capable(CAP_SYS_ADMIN))
  713. return -EPERM;
  714. return tvp7002_write(sd, reg->reg & 0xff, reg->val & 0xff);
  715. }
  716. #endif
  717. /*
  718. * tvp7002_enum_mbus_fmt() - Enum supported mediabus formats
  719. * @sd: pointer to standard V4L2 sub-device structure
  720. * @index: format index
  721. * @code: pointer to mediabus format
  722. *
  723. * Enumerate supported mediabus formats.
  724. */
  725. static int tvp7002_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned index,
  726. enum v4l2_mbus_pixelcode *code)
  727. {
  728. /* Check requested format index is within range */
  729. if (index)
  730. return -EINVAL;
  731. *code = V4L2_MBUS_FMT_YUYV10_1X20;
  732. return 0;
  733. }
  734. /*
  735. * tvp7002_s_stream() - V4L2 decoder i/f handler for s_stream
  736. * @sd: pointer to standard V4L2 sub-device structure
  737. * @enable: streaming enable or disable
  738. *
  739. * Sets streaming to enable or disable, if possible.
  740. */
  741. static int tvp7002_s_stream(struct v4l2_subdev *sd, int enable)
  742. {
  743. struct tvp7002 *device = to_tvp7002(sd);
  744. int error = 0;
  745. if (device->streaming == enable)
  746. return 0;
  747. if (enable) {
  748. /* Set output state on (low impedance means stream on) */
  749. error = tvp7002_write(sd, TVP7002_MISC_CTL_2, 0x00);
  750. device->streaming = enable;
  751. } else {
  752. /* Set output state off (high impedance means stream off) */
  753. error = tvp7002_write(sd, TVP7002_MISC_CTL_2, 0x03);
  754. if (error)
  755. v4l2_dbg(1, debug, sd, "Unable to stop streaming\n");
  756. device->streaming = enable;
  757. }
  758. return error;
  759. }
  760. /*
  761. * tvp7002_log_status() - Print information about register settings
  762. * @sd: ptr to v4l2_subdev struct
  763. *
  764. * Log register values of a TVP7002 decoder device.
  765. * Returns zero or -EINVAL if read operation fails.
  766. */
  767. static int tvp7002_log_status(struct v4l2_subdev *sd)
  768. {
  769. const struct tvp7002_preset_definition *presets = tvp7002_presets;
  770. struct tvp7002 *device = to_tvp7002(sd);
  771. struct v4l2_dv_enum_preset e_preset;
  772. struct v4l2_dv_preset detected;
  773. int i;
  774. detected.preset = V4L2_DV_INVALID;
  775. /* Find my current standard*/
  776. tvp7002_query_dv_preset(sd, &detected);
  777. /* Print standard related code values */
  778. for (i = 0; i < NUM_PRESETS; i++, presets++)
  779. if (presets->preset == detected.preset)
  780. break;
  781. if (v4l_fill_dv_preset_info(device->current_preset->preset, &e_preset))
  782. return -EINVAL;
  783. v4l2_info(sd, "Selected DV Preset: %s\n", e_preset.name);
  784. v4l2_info(sd, " Pixels per line: %u\n", e_preset.width);
  785. v4l2_info(sd, " Lines per frame: %u\n\n", e_preset.height);
  786. if (i == NUM_PRESETS) {
  787. v4l2_info(sd, "Detected DV Preset: None\n");
  788. } else {
  789. if (v4l_fill_dv_preset_info(presets->preset, &e_preset))
  790. return -EINVAL;
  791. v4l2_info(sd, "Detected DV Preset: %s\n", e_preset.name);
  792. v4l2_info(sd, " Pixels per line: %u\n", e_preset.width);
  793. v4l2_info(sd, " Lines per frame: %u\n\n", e_preset.height);
  794. }
  795. v4l2_info(sd, "Streaming enabled: %s\n",
  796. device->streaming ? "yes" : "no");
  797. /* Print the current value of the gain control */
  798. v4l2_ctrl_handler_log_status(&device->hdl, sd->name);
  799. return 0;
  800. }
  801. /*
  802. * tvp7002_enum_dv_presets() - Enum supported digital video formats
  803. * @sd: pointer to standard V4L2 sub-device structure
  804. * @preset: pointer to format struct
  805. *
  806. * Enumerate supported digital video formats.
  807. */
  808. static int tvp7002_enum_dv_presets(struct v4l2_subdev *sd,
  809. struct v4l2_dv_enum_preset *preset)
  810. {
  811. /* Check requested format index is within range */
  812. if (preset->index >= NUM_PRESETS)
  813. return -EINVAL;
  814. return v4l_fill_dv_preset_info(tvp7002_presets[preset->index].preset, preset);
  815. }
  816. static const struct v4l2_ctrl_ops tvp7002_ctrl_ops = {
  817. .s_ctrl = tvp7002_s_ctrl,
  818. };
  819. /* V4L2 core operation handlers */
  820. static const struct v4l2_subdev_core_ops tvp7002_core_ops = {
  821. .g_chip_ident = tvp7002_g_chip_ident,
  822. .log_status = tvp7002_log_status,
  823. .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
  824. .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
  825. .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
  826. .g_ctrl = v4l2_subdev_g_ctrl,
  827. .s_ctrl = v4l2_subdev_s_ctrl,
  828. .queryctrl = v4l2_subdev_queryctrl,
  829. .querymenu = v4l2_subdev_querymenu,
  830. #ifdef CONFIG_VIDEO_ADV_DEBUG
  831. .g_register = tvp7002_g_register,
  832. .s_register = tvp7002_s_register,
  833. #endif
  834. };
  835. /* Specific video subsystem operation handlers */
  836. static const struct v4l2_subdev_video_ops tvp7002_video_ops = {
  837. .enum_dv_presets = tvp7002_enum_dv_presets,
  838. .s_dv_preset = tvp7002_s_dv_preset,
  839. .query_dv_preset = tvp7002_query_dv_preset,
  840. .s_stream = tvp7002_s_stream,
  841. .g_mbus_fmt = tvp7002_mbus_fmt,
  842. .try_mbus_fmt = tvp7002_mbus_fmt,
  843. .s_mbus_fmt = tvp7002_mbus_fmt,
  844. .enum_mbus_fmt = tvp7002_enum_mbus_fmt,
  845. };
  846. /* V4L2 top level operation handlers */
  847. static const struct v4l2_subdev_ops tvp7002_ops = {
  848. .core = &tvp7002_core_ops,
  849. .video = &tvp7002_video_ops,
  850. };
  851. /*
  852. * tvp7002_probe - Probe a TVP7002 device
  853. * @c: ptr to i2c_client struct
  854. * @id: ptr to i2c_device_id struct
  855. *
  856. * Initialize the TVP7002 device
  857. * Returns zero when successful, -EINVAL if register read fails or
  858. * -EIO if i2c access is not available.
  859. */
  860. static int tvp7002_probe(struct i2c_client *c, const struct i2c_device_id *id)
  861. {
  862. struct v4l2_subdev *sd;
  863. struct tvp7002 *device;
  864. struct v4l2_dv_preset preset;
  865. int polarity_a;
  866. int polarity_b;
  867. u8 revision;
  868. int error;
  869. /* Check if the adapter supports the needed features */
  870. if (!i2c_check_functionality(c->adapter,
  871. I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
  872. return -EIO;
  873. if (!c->dev.platform_data) {
  874. v4l_err(c, "No platform data!!\n");
  875. return -ENODEV;
  876. }
  877. device = kzalloc(sizeof(struct tvp7002), GFP_KERNEL);
  878. if (!device)
  879. return -ENOMEM;
  880. sd = &device->sd;
  881. device->pdata = c->dev.platform_data;
  882. device->current_preset = tvp7002_presets;
  883. /* Tell v4l2 the device is ready */
  884. v4l2_i2c_subdev_init(sd, c, &tvp7002_ops);
  885. v4l_info(c, "tvp7002 found @ 0x%02x (%s)\n",
  886. c->addr, c->adapter->name);
  887. error = tvp7002_read(sd, TVP7002_CHIP_REV, &revision);
  888. if (error < 0)
  889. goto found_error;
  890. /* Get revision number */
  891. v4l2_info(sd, "Rev. %02x detected.\n", revision);
  892. if (revision != 0x02)
  893. v4l2_info(sd, "Unknown revision detected.\n");
  894. /* Initializes TVP7002 to its default values */
  895. error = tvp7002_write_inittab(sd, tvp7002_init_default);
  896. if (error < 0)
  897. goto found_error;
  898. /* Set polarity information after registers have been set */
  899. polarity_a = 0x20 | device->pdata->hs_polarity << 5
  900. | device->pdata->vs_polarity << 2;
  901. error = tvp7002_write(sd, TVP7002_SYNC_CTL_1, polarity_a);
  902. if (error < 0)
  903. goto found_error;
  904. polarity_b = 0x01 | device->pdata->fid_polarity << 2
  905. | device->pdata->sog_polarity << 1
  906. | device->pdata->clk_polarity;
  907. error = tvp7002_write(sd, TVP7002_MISC_CTL_3, polarity_b);
  908. if (error < 0)
  909. goto found_error;
  910. /* Set registers according to default video mode */
  911. preset.preset = device->current_preset->preset;
  912. error = tvp7002_s_dv_preset(sd, &preset);
  913. v4l2_ctrl_handler_init(&device->hdl, 1);
  914. v4l2_ctrl_new_std(&device->hdl, &tvp7002_ctrl_ops,
  915. V4L2_CID_GAIN, 0, 255, 1, 0);
  916. sd->ctrl_handler = &device->hdl;
  917. if (device->hdl.error) {
  918. int err = device->hdl.error;
  919. v4l2_ctrl_handler_free(&device->hdl);
  920. kfree(device);
  921. return err;
  922. }
  923. v4l2_ctrl_handler_setup(&device->hdl);
  924. found_error:
  925. if (error < 0)
  926. kfree(device);
  927. return error;
  928. }
  929. /*
  930. * tvp7002_remove - Remove TVP7002 device support
  931. * @c: ptr to i2c_client struct
  932. *
  933. * Reset the TVP7002 device
  934. * Returns zero.
  935. */
  936. static int tvp7002_remove(struct i2c_client *c)
  937. {
  938. struct v4l2_subdev *sd = i2c_get_clientdata(c);
  939. struct tvp7002 *device = to_tvp7002(sd);
  940. v4l2_dbg(1, debug, sd, "Removing tvp7002 adapter"
  941. "on address 0x%x\n", c->addr);
  942. v4l2_device_unregister_subdev(sd);
  943. v4l2_ctrl_handler_free(&device->hdl);
  944. kfree(device);
  945. return 0;
  946. }
  947. /* I2C Device ID table */
  948. static const struct i2c_device_id tvp7002_id[] = {
  949. { "tvp7002", 0 },
  950. { }
  951. };
  952. MODULE_DEVICE_TABLE(i2c, tvp7002_id);
  953. /* I2C driver data */
  954. static struct i2c_driver tvp7002_driver = {
  955. .driver = {
  956. .owner = THIS_MODULE,
  957. .name = TVP7002_MODULE_NAME,
  958. },
  959. .probe = tvp7002_probe,
  960. .remove = tvp7002_remove,
  961. .id_table = tvp7002_id,
  962. };
  963. /*
  964. * tvp7002_init - Initialize driver via I2C interface
  965. *
  966. * Register the TVP7002 driver.
  967. * Return 0 on success or error code on failure.
  968. */
  969. static int __init tvp7002_init(void)
  970. {
  971. return i2c_add_driver(&tvp7002_driver);
  972. }
  973. /*
  974. * tvp7002_exit - Remove driver via I2C interface
  975. *
  976. * Unregister the TVP7002 driver.
  977. * Returns nothing.
  978. */
  979. static void __exit tvp7002_exit(void)
  980. {
  981. i2c_del_driver(&tvp7002_driver);
  982. }
  983. module_init(tvp7002_init);
  984. module_exit(tvp7002_exit);