/drivers/media/video/mx3_camera.c

https://bitbucket.org/ndreys/linux-sunxi · C · 1328 lines · 956 code · 232 blank · 140 comment · 131 complexity · e773f3a887482bac6e404bdfa948165f MD5 · raw file

  1. /*
  2. * V4L2 Driver for i.MX3x camera host
  3. *
  4. * Copyright (C) 2008
  5. * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/init.h>
  12. #include <linux/module.h>
  13. #include <linux/version.h>
  14. #include <linux/videodev2.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/clk.h>
  17. #include <linux/vmalloc.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/sched.h>
  20. #include <media/v4l2-common.h>
  21. #include <media/v4l2-dev.h>
  22. #include <media/videobuf2-dma-contig.h>
  23. #include <media/soc_camera.h>
  24. #include <media/soc_mediabus.h>
  25. #include <mach/ipu.h>
  26. #include <mach/mx3_camera.h>
  27. #include <mach/dma.h>
  28. #define MX3_CAM_DRV_NAME "mx3-camera"
  29. /* CMOS Sensor Interface Registers */
  30. #define CSI_REG_START 0x60
  31. #define CSI_SENS_CONF (0x60 - CSI_REG_START)
  32. #define CSI_SENS_FRM_SIZE (0x64 - CSI_REG_START)
  33. #define CSI_ACT_FRM_SIZE (0x68 - CSI_REG_START)
  34. #define CSI_OUT_FRM_CTRL (0x6C - CSI_REG_START)
  35. #define CSI_TST_CTRL (0x70 - CSI_REG_START)
  36. #define CSI_CCIR_CODE_1 (0x74 - CSI_REG_START)
  37. #define CSI_CCIR_CODE_2 (0x78 - CSI_REG_START)
  38. #define CSI_CCIR_CODE_3 (0x7C - CSI_REG_START)
  39. #define CSI_FLASH_STROBE_1 (0x80 - CSI_REG_START)
  40. #define CSI_FLASH_STROBE_2 (0x84 - CSI_REG_START)
  41. #define CSI_SENS_CONF_VSYNC_POL_SHIFT 0
  42. #define CSI_SENS_CONF_HSYNC_POL_SHIFT 1
  43. #define CSI_SENS_CONF_DATA_POL_SHIFT 2
  44. #define CSI_SENS_CONF_PIX_CLK_POL_SHIFT 3
  45. #define CSI_SENS_CONF_SENS_PRTCL_SHIFT 4
  46. #define CSI_SENS_CONF_SENS_CLKSRC_SHIFT 7
  47. #define CSI_SENS_CONF_DATA_FMT_SHIFT 8
  48. #define CSI_SENS_CONF_DATA_WIDTH_SHIFT 10
  49. #define CSI_SENS_CONF_EXT_VSYNC_SHIFT 15
  50. #define CSI_SENS_CONF_DIVRATIO_SHIFT 16
  51. #define CSI_SENS_CONF_DATA_FMT_RGB_YUV444 (0UL << CSI_SENS_CONF_DATA_FMT_SHIFT)
  52. #define CSI_SENS_CONF_DATA_FMT_YUV422 (2UL << CSI_SENS_CONF_DATA_FMT_SHIFT)
  53. #define CSI_SENS_CONF_DATA_FMT_BAYER (3UL << CSI_SENS_CONF_DATA_FMT_SHIFT)
  54. #define MAX_VIDEO_MEM 16
  55. enum csi_buffer_state {
  56. CSI_BUF_NEEDS_INIT,
  57. CSI_BUF_PREPARED,
  58. };
  59. struct mx3_camera_buffer {
  60. /* common v4l buffer stuff -- must be first */
  61. struct vb2_buffer vb;
  62. enum csi_buffer_state state;
  63. struct list_head queue;
  64. /* One descriptot per scatterlist (per frame) */
  65. struct dma_async_tx_descriptor *txd;
  66. /* We have to "build" a scatterlist ourselves - one element per frame */
  67. struct scatterlist sg;
  68. };
  69. /**
  70. * struct mx3_camera_dev - i.MX3x camera (CSI) object
  71. * @dev: camera device, to which the coherent buffer is attached
  72. * @icd: currently attached camera sensor
  73. * @clk: pointer to clock
  74. * @base: remapped register base address
  75. * @pdata: platform data
  76. * @platform_flags: platform flags
  77. * @mclk: master clock frequency in Hz
  78. * @capture: list of capture videobuffers
  79. * @lock: protects video buffer lists
  80. * @active: active video buffer
  81. * @idmac_channel: array of pointers to IPU DMAC DMA channels
  82. * @soc_host: embedded soc_host object
  83. */
  84. struct mx3_camera_dev {
  85. /*
  86. * i.MX3x is only supposed to handle one camera on its Camera Sensor
  87. * Interface. If anyone ever builds hardware to enable more than one
  88. * camera _simultaneously_, they will have to modify this driver too
  89. */
  90. struct soc_camera_device *icd;
  91. struct clk *clk;
  92. void __iomem *base;
  93. struct mx3_camera_pdata *pdata;
  94. unsigned long platform_flags;
  95. unsigned long mclk;
  96. struct list_head capture;
  97. spinlock_t lock; /* Protects video buffer lists */
  98. struct mx3_camera_buffer *active;
  99. struct vb2_alloc_ctx *alloc_ctx;
  100. enum v4l2_field field;
  101. int sequence;
  102. /* IDMAC / dmaengine interface */
  103. struct idmac_channel *idmac_channel[1]; /* We need one channel */
  104. struct soc_camera_host soc_host;
  105. };
  106. struct dma_chan_request {
  107. struct mx3_camera_dev *mx3_cam;
  108. enum ipu_channel id;
  109. };
  110. static u32 csi_reg_read(struct mx3_camera_dev *mx3, off_t reg)
  111. {
  112. return __raw_readl(mx3->base + reg);
  113. }
  114. static void csi_reg_write(struct mx3_camera_dev *mx3, u32 value, off_t reg)
  115. {
  116. __raw_writel(value, mx3->base + reg);
  117. }
  118. static struct mx3_camera_buffer *to_mx3_vb(struct vb2_buffer *vb)
  119. {
  120. return container_of(vb, struct mx3_camera_buffer, vb);
  121. }
  122. /* Called from the IPU IDMAC ISR */
  123. static void mx3_cam_dma_done(void *arg)
  124. {
  125. struct idmac_tx_desc *desc = to_tx_desc(arg);
  126. struct dma_chan *chan = desc->txd.chan;
  127. struct idmac_channel *ichannel = to_idmac_chan(chan);
  128. struct mx3_camera_dev *mx3_cam = ichannel->client;
  129. dev_dbg(chan->device->dev, "callback cookie %d, active DMA 0x%08x\n",
  130. desc->txd.cookie, mx3_cam->active ? sg_dma_address(&mx3_cam->active->sg) : 0);
  131. spin_lock(&mx3_cam->lock);
  132. if (mx3_cam->active) {
  133. struct vb2_buffer *vb = &mx3_cam->active->vb;
  134. struct mx3_camera_buffer *buf = to_mx3_vb(vb);
  135. list_del_init(&buf->queue);
  136. do_gettimeofday(&vb->v4l2_buf.timestamp);
  137. vb->v4l2_buf.field = mx3_cam->field;
  138. vb->v4l2_buf.sequence = mx3_cam->sequence++;
  139. vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
  140. }
  141. if (list_empty(&mx3_cam->capture)) {
  142. mx3_cam->active = NULL;
  143. spin_unlock(&mx3_cam->lock);
  144. /*
  145. * stop capture - without further buffers IPU_CHA_BUF0_RDY will
  146. * not get updated
  147. */
  148. return;
  149. }
  150. mx3_cam->active = list_entry(mx3_cam->capture.next,
  151. struct mx3_camera_buffer, queue);
  152. spin_unlock(&mx3_cam->lock);
  153. }
  154. /*
  155. * Videobuf operations
  156. */
  157. /*
  158. * Calculate the __buffer__ (not data) size and number of buffers.
  159. */
  160. static int mx3_videobuf_setup(struct vb2_queue *vq,
  161. unsigned int *count, unsigned int *num_planes,
  162. unsigned long sizes[], void *alloc_ctxs[])
  163. {
  164. struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
  165. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  166. struct mx3_camera_dev *mx3_cam = ici->priv;
  167. int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
  168. icd->current_fmt->host_fmt);
  169. if (bytes_per_line < 0)
  170. return bytes_per_line;
  171. if (!mx3_cam->idmac_channel[0])
  172. return -EINVAL;
  173. *num_planes = 1;
  174. mx3_cam->sequence = 0;
  175. sizes[0] = bytes_per_line * icd->user_height;
  176. alloc_ctxs[0] = mx3_cam->alloc_ctx;
  177. if (!*count)
  178. *count = 32;
  179. if (sizes[0] * *count > MAX_VIDEO_MEM * 1024 * 1024)
  180. *count = MAX_VIDEO_MEM * 1024 * 1024 / sizes[0];
  181. return 0;
  182. }
  183. static int mx3_videobuf_prepare(struct vb2_buffer *vb)
  184. {
  185. struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
  186. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  187. struct mx3_camera_dev *mx3_cam = ici->priv;
  188. struct idmac_channel *ichan = mx3_cam->idmac_channel[0];
  189. struct scatterlist *sg;
  190. struct mx3_camera_buffer *buf;
  191. size_t new_size;
  192. int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
  193. icd->current_fmt->host_fmt);
  194. if (bytes_per_line < 0)
  195. return bytes_per_line;
  196. buf = to_mx3_vb(vb);
  197. sg = &buf->sg;
  198. new_size = bytes_per_line * icd->user_height;
  199. if (vb2_plane_size(vb, 0) < new_size) {
  200. dev_err(icd->dev.parent, "Buffer too small (%lu < %zu)\n",
  201. vb2_plane_size(vb, 0), new_size);
  202. return -ENOBUFS;
  203. }
  204. if (buf->state == CSI_BUF_NEEDS_INIT) {
  205. sg_dma_address(sg) = vb2_dma_contig_plane_paddr(vb, 0);
  206. sg_dma_len(sg) = new_size;
  207. buf->txd = ichan->dma_chan.device->device_prep_slave_sg(
  208. &ichan->dma_chan, sg, 1, DMA_FROM_DEVICE,
  209. DMA_PREP_INTERRUPT);
  210. if (!buf->txd)
  211. return -EIO;
  212. buf->txd->callback_param = buf->txd;
  213. buf->txd->callback = mx3_cam_dma_done;
  214. buf->state = CSI_BUF_PREPARED;
  215. }
  216. vb2_set_plane_payload(vb, 0, new_size);
  217. return 0;
  218. }
  219. static enum pixel_fmt fourcc_to_ipu_pix(__u32 fourcc)
  220. {
  221. /* Add more formats as need arises and test possibilities appear... */
  222. switch (fourcc) {
  223. case V4L2_PIX_FMT_RGB24:
  224. return IPU_PIX_FMT_RGB24;
  225. case V4L2_PIX_FMT_UYVY:
  226. case V4L2_PIX_FMT_RGB565:
  227. default:
  228. return IPU_PIX_FMT_GENERIC;
  229. }
  230. }
  231. static void mx3_videobuf_queue(struct vb2_buffer *vb)
  232. {
  233. struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
  234. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  235. struct mx3_camera_dev *mx3_cam = ici->priv;
  236. struct mx3_camera_buffer *buf = to_mx3_vb(vb);
  237. struct dma_async_tx_descriptor *txd = buf->txd;
  238. struct idmac_channel *ichan = to_idmac_chan(txd->chan);
  239. struct idmac_video_param *video = &ichan->params.video;
  240. dma_cookie_t cookie;
  241. u32 fourcc = icd->current_fmt->host_fmt->fourcc;
  242. unsigned long flags;
  243. /* This is the configuration of one sg-element */
  244. video->out_pixel_fmt = fourcc_to_ipu_pix(fourcc);
  245. if (video->out_pixel_fmt == IPU_PIX_FMT_GENERIC) {
  246. /*
  247. * If the IPU DMA channel is configured to transport
  248. * generic 8-bit data, we have to set up correctly the
  249. * geometry parameters upon the current pixel format.
  250. * So, since the DMA horizontal parameters are expressed
  251. * in bytes not pixels, convert these in the right unit.
  252. */
  253. int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
  254. icd->current_fmt->host_fmt);
  255. BUG_ON(bytes_per_line <= 0);
  256. video->out_width = bytes_per_line;
  257. video->out_height = icd->user_height;
  258. video->out_stride = bytes_per_line;
  259. } else {
  260. /*
  261. * For IPU known formats the pixel unit will be managed
  262. * successfully by the IPU code
  263. */
  264. video->out_width = icd->user_width;
  265. video->out_height = icd->user_height;
  266. video->out_stride = icd->user_width;
  267. }
  268. #ifdef DEBUG
  269. /* helps to see what DMA actually has written */
  270. if (vb2_plane_vaddr(vb, 0))
  271. memset(vb2_plane_vaddr(vb, 0), 0xaa, vb2_get_plane_payload(vb, 0));
  272. #endif
  273. spin_lock_irqsave(&mx3_cam->lock, flags);
  274. list_add_tail(&buf->queue, &mx3_cam->capture);
  275. if (!mx3_cam->active)
  276. mx3_cam->active = buf;
  277. spin_unlock_irq(&mx3_cam->lock);
  278. cookie = txd->tx_submit(txd);
  279. dev_dbg(icd->dev.parent, "Submitted cookie %d DMA 0x%08x\n",
  280. cookie, sg_dma_address(&buf->sg));
  281. if (cookie >= 0)
  282. return;
  283. spin_lock_irq(&mx3_cam->lock);
  284. /* Submit error */
  285. list_del_init(&buf->queue);
  286. if (mx3_cam->active == buf)
  287. mx3_cam->active = NULL;
  288. spin_unlock_irqrestore(&mx3_cam->lock, flags);
  289. vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
  290. }
  291. static void mx3_videobuf_release(struct vb2_buffer *vb)
  292. {
  293. struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
  294. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  295. struct mx3_camera_dev *mx3_cam = ici->priv;
  296. struct mx3_camera_buffer *buf = to_mx3_vb(vb);
  297. struct dma_async_tx_descriptor *txd = buf->txd;
  298. unsigned long flags;
  299. dev_dbg(icd->dev.parent,
  300. "Release%s DMA 0x%08x, queue %sempty\n",
  301. mx3_cam->active == buf ? " active" : "", sg_dma_address(&buf->sg),
  302. list_empty(&buf->queue) ? "" : "not ");
  303. spin_lock_irqsave(&mx3_cam->lock, flags);
  304. if (mx3_cam->active == buf)
  305. mx3_cam->active = NULL;
  306. /* Doesn't hurt also if the list is empty */
  307. list_del_init(&buf->queue);
  308. buf->state = CSI_BUF_NEEDS_INIT;
  309. if (txd) {
  310. buf->txd = NULL;
  311. if (mx3_cam->idmac_channel[0])
  312. async_tx_ack(txd);
  313. }
  314. spin_unlock_irqrestore(&mx3_cam->lock, flags);
  315. }
  316. static int mx3_videobuf_init(struct vb2_buffer *vb)
  317. {
  318. struct mx3_camera_buffer *buf = to_mx3_vb(vb);
  319. /* This is for locking debugging only */
  320. INIT_LIST_HEAD(&buf->queue);
  321. sg_init_table(&buf->sg, 1);
  322. buf->state = CSI_BUF_NEEDS_INIT;
  323. buf->txd = NULL;
  324. return 0;
  325. }
  326. static int mx3_stop_streaming(struct vb2_queue *q)
  327. {
  328. struct soc_camera_device *icd = soc_camera_from_vb2q(q);
  329. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  330. struct mx3_camera_dev *mx3_cam = ici->priv;
  331. struct idmac_channel *ichan = mx3_cam->idmac_channel[0];
  332. struct dma_chan *chan;
  333. struct mx3_camera_buffer *buf, *tmp;
  334. unsigned long flags;
  335. if (ichan) {
  336. chan = &ichan->dma_chan;
  337. chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
  338. }
  339. spin_lock_irqsave(&mx3_cam->lock, flags);
  340. mx3_cam->active = NULL;
  341. list_for_each_entry_safe(buf, tmp, &mx3_cam->capture, queue) {
  342. buf->state = CSI_BUF_NEEDS_INIT;
  343. list_del_init(&buf->queue);
  344. }
  345. spin_unlock_irqrestore(&mx3_cam->lock, flags);
  346. return 0;
  347. }
  348. static struct vb2_ops mx3_videobuf_ops = {
  349. .queue_setup = mx3_videobuf_setup,
  350. .buf_prepare = mx3_videobuf_prepare,
  351. .buf_queue = mx3_videobuf_queue,
  352. .buf_cleanup = mx3_videobuf_release,
  353. .buf_init = mx3_videobuf_init,
  354. .wait_prepare = soc_camera_unlock,
  355. .wait_finish = soc_camera_lock,
  356. .stop_streaming = mx3_stop_streaming,
  357. };
  358. static int mx3_camera_init_videobuf(struct vb2_queue *q,
  359. struct soc_camera_device *icd)
  360. {
  361. q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  362. q->io_modes = VB2_MMAP | VB2_USERPTR;
  363. q->drv_priv = icd;
  364. q->ops = &mx3_videobuf_ops;
  365. q->mem_ops = &vb2_dma_contig_memops;
  366. q->buf_struct_size = sizeof(struct mx3_camera_buffer);
  367. return vb2_queue_init(q);
  368. }
  369. /* First part of ipu_csi_init_interface() */
  370. static void mx3_camera_activate(struct mx3_camera_dev *mx3_cam,
  371. struct soc_camera_device *icd)
  372. {
  373. u32 conf;
  374. long rate;
  375. /* Set default size: ipu_csi_set_window_size() */
  376. csi_reg_write(mx3_cam, (640 - 1) | ((480 - 1) << 16), CSI_ACT_FRM_SIZE);
  377. /* ...and position to 0:0: ipu_csi_set_window_pos() */
  378. conf = csi_reg_read(mx3_cam, CSI_OUT_FRM_CTRL) & 0xffff0000;
  379. csi_reg_write(mx3_cam, conf, CSI_OUT_FRM_CTRL);
  380. /* We use only gated clock synchronisation mode so far */
  381. conf = 0 << CSI_SENS_CONF_SENS_PRTCL_SHIFT;
  382. /* Set generic data, platform-biggest bus-width */
  383. conf |= CSI_SENS_CONF_DATA_FMT_BAYER;
  384. if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_15)
  385. conf |= 3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
  386. else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_10)
  387. conf |= 2 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
  388. else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_8)
  389. conf |= 1 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
  390. else/* if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_4)*/
  391. conf |= 0 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
  392. if (mx3_cam->platform_flags & MX3_CAMERA_CLK_SRC)
  393. conf |= 1 << CSI_SENS_CONF_SENS_CLKSRC_SHIFT;
  394. if (mx3_cam->platform_flags & MX3_CAMERA_EXT_VSYNC)
  395. conf |= 1 << CSI_SENS_CONF_EXT_VSYNC_SHIFT;
  396. if (mx3_cam->platform_flags & MX3_CAMERA_DP)
  397. conf |= 1 << CSI_SENS_CONF_DATA_POL_SHIFT;
  398. if (mx3_cam->platform_flags & MX3_CAMERA_PCP)
  399. conf |= 1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT;
  400. if (mx3_cam->platform_flags & MX3_CAMERA_HSP)
  401. conf |= 1 << CSI_SENS_CONF_HSYNC_POL_SHIFT;
  402. if (mx3_cam->platform_flags & MX3_CAMERA_VSP)
  403. conf |= 1 << CSI_SENS_CONF_VSYNC_POL_SHIFT;
  404. /* ipu_csi_init_interface() */
  405. csi_reg_write(mx3_cam, conf, CSI_SENS_CONF);
  406. clk_enable(mx3_cam->clk);
  407. rate = clk_round_rate(mx3_cam->clk, mx3_cam->mclk);
  408. dev_dbg(icd->dev.parent, "Set SENS_CONF to %x, rate %ld\n", conf, rate);
  409. if (rate)
  410. clk_set_rate(mx3_cam->clk, rate);
  411. }
  412. /* Called with .video_lock held */
  413. static int mx3_camera_add_device(struct soc_camera_device *icd)
  414. {
  415. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  416. struct mx3_camera_dev *mx3_cam = ici->priv;
  417. if (mx3_cam->icd)
  418. return -EBUSY;
  419. mx3_camera_activate(mx3_cam, icd);
  420. mx3_cam->icd = icd;
  421. dev_info(icd->dev.parent, "MX3 Camera driver attached to camera %d\n",
  422. icd->devnum);
  423. return 0;
  424. }
  425. /* Called with .video_lock held */
  426. static void mx3_camera_remove_device(struct soc_camera_device *icd)
  427. {
  428. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  429. struct mx3_camera_dev *mx3_cam = ici->priv;
  430. struct idmac_channel **ichan = &mx3_cam->idmac_channel[0];
  431. BUG_ON(icd != mx3_cam->icd);
  432. if (*ichan) {
  433. dma_release_channel(&(*ichan)->dma_chan);
  434. *ichan = NULL;
  435. }
  436. clk_disable(mx3_cam->clk);
  437. mx3_cam->icd = NULL;
  438. dev_info(icd->dev.parent, "MX3 Camera driver detached from camera %d\n",
  439. icd->devnum);
  440. }
  441. static int test_platform_param(struct mx3_camera_dev *mx3_cam,
  442. unsigned char buswidth, unsigned long *flags)
  443. {
  444. /*
  445. * Platform specified synchronization and pixel clock polarities are
  446. * only a recommendation and are only used during probing. MX3x
  447. * camera interface only works in master mode, i.e., uses HSYNC and
  448. * VSYNC signals from the sensor
  449. */
  450. *flags = SOCAM_MASTER |
  451. SOCAM_HSYNC_ACTIVE_HIGH |
  452. SOCAM_HSYNC_ACTIVE_LOW |
  453. SOCAM_VSYNC_ACTIVE_HIGH |
  454. SOCAM_VSYNC_ACTIVE_LOW |
  455. SOCAM_PCLK_SAMPLE_RISING |
  456. SOCAM_PCLK_SAMPLE_FALLING |
  457. SOCAM_DATA_ACTIVE_HIGH |
  458. SOCAM_DATA_ACTIVE_LOW;
  459. /*
  460. * If requested data width is supported by the platform, use it or any
  461. * possible lower value - i.MX31 is smart enough to schift bits
  462. */
  463. if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_15)
  464. *flags |= SOCAM_DATAWIDTH_15 | SOCAM_DATAWIDTH_10 |
  465. SOCAM_DATAWIDTH_8 | SOCAM_DATAWIDTH_4;
  466. else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_10)
  467. *flags |= SOCAM_DATAWIDTH_10 | SOCAM_DATAWIDTH_8 |
  468. SOCAM_DATAWIDTH_4;
  469. else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_8)
  470. *flags |= SOCAM_DATAWIDTH_8 | SOCAM_DATAWIDTH_4;
  471. else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_4)
  472. *flags |= SOCAM_DATAWIDTH_4;
  473. switch (buswidth) {
  474. case 15:
  475. if (!(*flags & SOCAM_DATAWIDTH_15))
  476. return -EINVAL;
  477. break;
  478. case 10:
  479. if (!(*flags & SOCAM_DATAWIDTH_10))
  480. return -EINVAL;
  481. break;
  482. case 8:
  483. if (!(*flags & SOCAM_DATAWIDTH_8))
  484. return -EINVAL;
  485. break;
  486. case 4:
  487. if (!(*flags & SOCAM_DATAWIDTH_4))
  488. return -EINVAL;
  489. break;
  490. default:
  491. dev_warn(mx3_cam->soc_host.v4l2_dev.dev,
  492. "Unsupported bus width %d\n", buswidth);
  493. return -EINVAL;
  494. }
  495. return 0;
  496. }
  497. static int mx3_camera_try_bus_param(struct soc_camera_device *icd,
  498. const unsigned int depth)
  499. {
  500. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  501. struct mx3_camera_dev *mx3_cam = ici->priv;
  502. unsigned long bus_flags, camera_flags;
  503. int ret = test_platform_param(mx3_cam, depth, &bus_flags);
  504. dev_dbg(icd->dev.parent, "request bus width %d bit: %d\n", depth, ret);
  505. if (ret < 0)
  506. return ret;
  507. camera_flags = icd->ops->query_bus_param(icd);
  508. ret = soc_camera_bus_param_compatible(camera_flags, bus_flags);
  509. if (ret < 0)
  510. dev_warn(icd->dev.parent,
  511. "Flags incompatible: camera %lx, host %lx\n",
  512. camera_flags, bus_flags);
  513. return ret;
  514. }
  515. static bool chan_filter(struct dma_chan *chan, void *arg)
  516. {
  517. struct dma_chan_request *rq = arg;
  518. struct mx3_camera_pdata *pdata;
  519. if (!imx_dma_is_ipu(chan))
  520. return false;
  521. if (!rq)
  522. return false;
  523. pdata = rq->mx3_cam->soc_host.v4l2_dev.dev->platform_data;
  524. return rq->id == chan->chan_id &&
  525. pdata->dma_dev == chan->device->dev;
  526. }
  527. static const struct soc_mbus_pixelfmt mx3_camera_formats[] = {
  528. {
  529. .fourcc = V4L2_PIX_FMT_SBGGR8,
  530. .name = "Bayer BGGR (sRGB) 8 bit",
  531. .bits_per_sample = 8,
  532. .packing = SOC_MBUS_PACKING_NONE,
  533. .order = SOC_MBUS_ORDER_LE,
  534. }, {
  535. .fourcc = V4L2_PIX_FMT_GREY,
  536. .name = "Monochrome 8 bit",
  537. .bits_per_sample = 8,
  538. .packing = SOC_MBUS_PACKING_NONE,
  539. .order = SOC_MBUS_ORDER_LE,
  540. },
  541. };
  542. /* This will be corrected as we get more formats */
  543. static bool mx3_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt)
  544. {
  545. return fmt->packing == SOC_MBUS_PACKING_NONE ||
  546. (fmt->bits_per_sample == 8 &&
  547. fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) ||
  548. (fmt->bits_per_sample > 8 &&
  549. fmt->packing == SOC_MBUS_PACKING_EXTEND16);
  550. }
  551. static int mx3_camera_get_formats(struct soc_camera_device *icd, unsigned int idx,
  552. struct soc_camera_format_xlate *xlate)
  553. {
  554. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  555. struct device *dev = icd->dev.parent;
  556. int formats = 0, ret;
  557. enum v4l2_mbus_pixelcode code;
  558. const struct soc_mbus_pixelfmt *fmt;
  559. ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
  560. if (ret < 0)
  561. /* No more formats */
  562. return 0;
  563. fmt = soc_mbus_get_fmtdesc(code);
  564. if (!fmt) {
  565. dev_warn(icd->dev.parent,
  566. "Unsupported format code #%u: %d\n", idx, code);
  567. return 0;
  568. }
  569. /* This also checks support for the requested bits-per-sample */
  570. ret = mx3_camera_try_bus_param(icd, fmt->bits_per_sample);
  571. if (ret < 0)
  572. return 0;
  573. switch (code) {
  574. case V4L2_MBUS_FMT_SBGGR10_1X10:
  575. formats++;
  576. if (xlate) {
  577. xlate->host_fmt = &mx3_camera_formats[0];
  578. xlate->code = code;
  579. xlate++;
  580. dev_dbg(dev, "Providing format %s using code %d\n",
  581. mx3_camera_formats[0].name, code);
  582. }
  583. break;
  584. case V4L2_MBUS_FMT_Y10_1X10:
  585. formats++;
  586. if (xlate) {
  587. xlate->host_fmt = &mx3_camera_formats[1];
  588. xlate->code = code;
  589. xlate++;
  590. dev_dbg(dev, "Providing format %s using code %d\n",
  591. mx3_camera_formats[1].name, code);
  592. }
  593. break;
  594. default:
  595. if (!mx3_camera_packing_supported(fmt))
  596. return 0;
  597. }
  598. /* Generic pass-through */
  599. formats++;
  600. if (xlate) {
  601. xlate->host_fmt = fmt;
  602. xlate->code = code;
  603. dev_dbg(dev, "Providing format %c%c%c%c in pass-through mode\n",
  604. (fmt->fourcc >> (0*8)) & 0xFF,
  605. (fmt->fourcc >> (1*8)) & 0xFF,
  606. (fmt->fourcc >> (2*8)) & 0xFF,
  607. (fmt->fourcc >> (3*8)) & 0xFF);
  608. xlate++;
  609. }
  610. return formats;
  611. }
  612. static void configure_geometry(struct mx3_camera_dev *mx3_cam,
  613. unsigned int width, unsigned int height,
  614. const struct soc_mbus_pixelfmt *fmt)
  615. {
  616. u32 ctrl, width_field, height_field;
  617. if (fourcc_to_ipu_pix(fmt->fourcc) == IPU_PIX_FMT_GENERIC) {
  618. /*
  619. * As the CSI will be configured to output BAYER, here
  620. * the width parameter count the number of samples to
  621. * capture to complete the whole image width.
  622. */
  623. unsigned int num, den;
  624. int ret = soc_mbus_samples_per_pixel(fmt, &num, &den);
  625. BUG_ON(ret < 0);
  626. width = width * num / den;
  627. }
  628. /* Setup frame size - this cannot be changed on-the-fly... */
  629. width_field = width - 1;
  630. height_field = height - 1;
  631. csi_reg_write(mx3_cam, width_field | (height_field << 16), CSI_SENS_FRM_SIZE);
  632. csi_reg_write(mx3_cam, width_field << 16, CSI_FLASH_STROBE_1);
  633. csi_reg_write(mx3_cam, (height_field << 16) | 0x22, CSI_FLASH_STROBE_2);
  634. csi_reg_write(mx3_cam, width_field | (height_field << 16), CSI_ACT_FRM_SIZE);
  635. /* ...and position */
  636. ctrl = csi_reg_read(mx3_cam, CSI_OUT_FRM_CTRL) & 0xffff0000;
  637. /* Sensor does the cropping */
  638. csi_reg_write(mx3_cam, ctrl | 0 | (0 << 8), CSI_OUT_FRM_CTRL);
  639. }
  640. static int acquire_dma_channel(struct mx3_camera_dev *mx3_cam)
  641. {
  642. dma_cap_mask_t mask;
  643. struct dma_chan *chan;
  644. struct idmac_channel **ichan = &mx3_cam->idmac_channel[0];
  645. /* We have to use IDMAC_IC_7 for Bayer / generic data */
  646. struct dma_chan_request rq = {.mx3_cam = mx3_cam,
  647. .id = IDMAC_IC_7};
  648. dma_cap_zero(mask);
  649. dma_cap_set(DMA_SLAVE, mask);
  650. dma_cap_set(DMA_PRIVATE, mask);
  651. chan = dma_request_channel(mask, chan_filter, &rq);
  652. if (!chan)
  653. return -EBUSY;
  654. *ichan = to_idmac_chan(chan);
  655. (*ichan)->client = mx3_cam;
  656. return 0;
  657. }
  658. /*
  659. * FIXME: learn to use stride != width, then we can keep stride properly aligned
  660. * and support arbitrary (even) widths.
  661. */
  662. static inline void stride_align(__u32 *width)
  663. {
  664. if (ALIGN(*width, 8) < 4096)
  665. *width = ALIGN(*width, 8);
  666. else
  667. *width = *width & ~7;
  668. }
  669. /*
  670. * As long as we don't implement host-side cropping and scaling, we can use
  671. * default g_crop and cropcap from soc_camera.c
  672. */
  673. static int mx3_camera_set_crop(struct soc_camera_device *icd,
  674. struct v4l2_crop *a)
  675. {
  676. struct v4l2_rect *rect = &a->c;
  677. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  678. struct mx3_camera_dev *mx3_cam = ici->priv;
  679. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  680. struct v4l2_mbus_framefmt mf;
  681. int ret;
  682. soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
  683. soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
  684. ret = v4l2_subdev_call(sd, video, s_crop, a);
  685. if (ret < 0)
  686. return ret;
  687. /* The capture device might have changed its output sizes */
  688. ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
  689. if (ret < 0)
  690. return ret;
  691. if (mf.code != icd->current_fmt->code)
  692. return -EINVAL;
  693. if (mf.width & 7) {
  694. /* Ouch! We can only handle 8-byte aligned width... */
  695. stride_align(&mf.width);
  696. ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
  697. if (ret < 0)
  698. return ret;
  699. }
  700. if (mf.width != icd->user_width || mf.height != icd->user_height)
  701. configure_geometry(mx3_cam, mf.width, mf.height,
  702. icd->current_fmt->host_fmt);
  703. dev_dbg(icd->dev.parent, "Sensor cropped %dx%d\n",
  704. mf.width, mf.height);
  705. icd->user_width = mf.width;
  706. icd->user_height = mf.height;
  707. return ret;
  708. }
  709. static int mx3_camera_set_fmt(struct soc_camera_device *icd,
  710. struct v4l2_format *f)
  711. {
  712. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  713. struct mx3_camera_dev *mx3_cam = ici->priv;
  714. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  715. const struct soc_camera_format_xlate *xlate;
  716. struct v4l2_pix_format *pix = &f->fmt.pix;
  717. struct v4l2_mbus_framefmt mf;
  718. int ret;
  719. xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
  720. if (!xlate) {
  721. dev_warn(icd->dev.parent, "Format %x not found\n",
  722. pix->pixelformat);
  723. return -EINVAL;
  724. }
  725. stride_align(&pix->width);
  726. dev_dbg(icd->dev.parent, "Set format %dx%d\n", pix->width, pix->height);
  727. /*
  728. * Might have to perform a complete interface initialisation like in
  729. * ipu_csi_init_interface() in mxc_v4l2_s_param(). Also consider
  730. * mxc_v4l2_s_fmt()
  731. */
  732. configure_geometry(mx3_cam, pix->width, pix->height, xlate->host_fmt);
  733. mf.width = pix->width;
  734. mf.height = pix->height;
  735. mf.field = pix->field;
  736. mf.colorspace = pix->colorspace;
  737. mf.code = xlate->code;
  738. ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
  739. if (ret < 0)
  740. return ret;
  741. if (mf.code != xlate->code)
  742. return -EINVAL;
  743. if (!mx3_cam->idmac_channel[0]) {
  744. ret = acquire_dma_channel(mx3_cam);
  745. if (ret < 0)
  746. return ret;
  747. }
  748. pix->width = mf.width;
  749. pix->height = mf.height;
  750. pix->field = mf.field;
  751. mx3_cam->field = mf.field;
  752. pix->colorspace = mf.colorspace;
  753. icd->current_fmt = xlate;
  754. pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
  755. xlate->host_fmt);
  756. if (pix->bytesperline < 0)
  757. return pix->bytesperline;
  758. pix->sizeimage = pix->height * pix->bytesperline;
  759. dev_dbg(icd->dev.parent, "Sensor set %dx%d\n", pix->width, pix->height);
  760. return ret;
  761. }
  762. static int mx3_camera_try_fmt(struct soc_camera_device *icd,
  763. struct v4l2_format *f)
  764. {
  765. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  766. const struct soc_camera_format_xlate *xlate;
  767. struct v4l2_pix_format *pix = &f->fmt.pix;
  768. struct v4l2_mbus_framefmt mf;
  769. __u32 pixfmt = pix->pixelformat;
  770. int ret;
  771. xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
  772. if (pixfmt && !xlate) {
  773. dev_warn(icd->dev.parent, "Format %x not found\n", pixfmt);
  774. return -EINVAL;
  775. }
  776. /* limit to MX3 hardware capabilities */
  777. if (pix->height > 4096)
  778. pix->height = 4096;
  779. if (pix->width > 4096)
  780. pix->width = 4096;
  781. pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
  782. xlate->host_fmt);
  783. if (pix->bytesperline < 0)
  784. return pix->bytesperline;
  785. pix->sizeimage = pix->height * pix->bytesperline;
  786. /* limit to sensor capabilities */
  787. mf.width = pix->width;
  788. mf.height = pix->height;
  789. mf.field = pix->field;
  790. mf.colorspace = pix->colorspace;
  791. mf.code = xlate->code;
  792. ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
  793. if (ret < 0)
  794. return ret;
  795. pix->width = mf.width;
  796. pix->height = mf.height;
  797. pix->colorspace = mf.colorspace;
  798. switch (mf.field) {
  799. case V4L2_FIELD_ANY:
  800. pix->field = V4L2_FIELD_NONE;
  801. break;
  802. case V4L2_FIELD_NONE:
  803. break;
  804. default:
  805. dev_err(icd->dev.parent, "Field type %d unsupported.\n",
  806. mf.field);
  807. ret = -EINVAL;
  808. }
  809. return ret;
  810. }
  811. static int mx3_camera_reqbufs(struct soc_camera_device *icd,
  812. struct v4l2_requestbuffers *p)
  813. {
  814. return 0;
  815. }
  816. static unsigned int mx3_camera_poll(struct file *file, poll_table *pt)
  817. {
  818. struct soc_camera_device *icd = file->private_data;
  819. return vb2_poll(&icd->vb2_vidq, file, pt);
  820. }
  821. static int mx3_camera_querycap(struct soc_camera_host *ici,
  822. struct v4l2_capability *cap)
  823. {
  824. /* cap->name is set by the firendly caller:-> */
  825. strlcpy(cap->card, "i.MX3x Camera", sizeof(cap->card));
  826. cap->version = KERNEL_VERSION(0, 2, 2);
  827. cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
  828. return 0;
  829. }
  830. static int mx3_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
  831. {
  832. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  833. struct mx3_camera_dev *mx3_cam = ici->priv;
  834. unsigned long bus_flags, camera_flags, common_flags;
  835. u32 dw, sens_conf;
  836. const struct soc_mbus_pixelfmt *fmt;
  837. int buswidth;
  838. int ret;
  839. const struct soc_camera_format_xlate *xlate;
  840. struct device *dev = icd->dev.parent;
  841. fmt = soc_mbus_get_fmtdesc(icd->current_fmt->code);
  842. if (!fmt)
  843. return -EINVAL;
  844. buswidth = fmt->bits_per_sample;
  845. ret = test_platform_param(mx3_cam, buswidth, &bus_flags);
  846. xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
  847. if (!xlate) {
  848. dev_warn(dev, "Format %x not found\n", pixfmt);
  849. return -EINVAL;
  850. }
  851. dev_dbg(dev, "requested bus width %d bit: %d\n", buswidth, ret);
  852. if (ret < 0)
  853. return ret;
  854. camera_flags = icd->ops->query_bus_param(icd);
  855. common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags);
  856. dev_dbg(dev, "Flags cam: 0x%lx host: 0x%lx common: 0x%lx\n",
  857. camera_flags, bus_flags, common_flags);
  858. if (!common_flags) {
  859. dev_dbg(dev, "no common flags");
  860. return -EINVAL;
  861. }
  862. /* Make choices, based on platform preferences */
  863. if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
  864. (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
  865. if (mx3_cam->platform_flags & MX3_CAMERA_HSP)
  866. common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
  867. else
  868. common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
  869. }
  870. if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) &&
  871. (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) {
  872. if (mx3_cam->platform_flags & MX3_CAMERA_VSP)
  873. common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH;
  874. else
  875. common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW;
  876. }
  877. if ((common_flags & SOCAM_DATA_ACTIVE_HIGH) &&
  878. (common_flags & SOCAM_DATA_ACTIVE_LOW)) {
  879. if (mx3_cam->platform_flags & MX3_CAMERA_DP)
  880. common_flags &= ~SOCAM_DATA_ACTIVE_HIGH;
  881. else
  882. common_flags &= ~SOCAM_DATA_ACTIVE_LOW;
  883. }
  884. if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
  885. (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
  886. if (mx3_cam->platform_flags & MX3_CAMERA_PCP)
  887. common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
  888. else
  889. common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
  890. }
  891. /*
  892. * Make the camera work in widest common mode, we'll take care of
  893. * the rest
  894. */
  895. if (common_flags & SOCAM_DATAWIDTH_15)
  896. common_flags = (common_flags & ~SOCAM_DATAWIDTH_MASK) |
  897. SOCAM_DATAWIDTH_15;
  898. else if (common_flags & SOCAM_DATAWIDTH_10)
  899. common_flags = (common_flags & ~SOCAM_DATAWIDTH_MASK) |
  900. SOCAM_DATAWIDTH_10;
  901. else if (common_flags & SOCAM_DATAWIDTH_8)
  902. common_flags = (common_flags & ~SOCAM_DATAWIDTH_MASK) |
  903. SOCAM_DATAWIDTH_8;
  904. else
  905. common_flags = (common_flags & ~SOCAM_DATAWIDTH_MASK) |
  906. SOCAM_DATAWIDTH_4;
  907. ret = icd->ops->set_bus_param(icd, common_flags);
  908. if (ret < 0) {
  909. dev_dbg(dev, "camera set_bus_param(%lx) returned %d\n",
  910. common_flags, ret);
  911. return ret;
  912. }
  913. /*
  914. * So far only gated clock mode is supported. Add a line
  915. * (3 << CSI_SENS_CONF_SENS_PRTCL_SHIFT) |
  916. * below and select the required mode when supporting other
  917. * synchronisation protocols.
  918. */
  919. sens_conf = csi_reg_read(mx3_cam, CSI_SENS_CONF) &
  920. ~((1 << CSI_SENS_CONF_VSYNC_POL_SHIFT) |
  921. (1 << CSI_SENS_CONF_HSYNC_POL_SHIFT) |
  922. (1 << CSI_SENS_CONF_DATA_POL_SHIFT) |
  923. (1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT) |
  924. (3 << CSI_SENS_CONF_DATA_FMT_SHIFT) |
  925. (3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT));
  926. /* TODO: Support RGB and YUV formats */
  927. /* This has been set in mx3_camera_activate(), but we clear it above */
  928. sens_conf |= CSI_SENS_CONF_DATA_FMT_BAYER;
  929. if (common_flags & SOCAM_PCLK_SAMPLE_FALLING)
  930. sens_conf |= 1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT;
  931. if (common_flags & SOCAM_HSYNC_ACTIVE_LOW)
  932. sens_conf |= 1 << CSI_SENS_CONF_HSYNC_POL_SHIFT;
  933. if (common_flags & SOCAM_VSYNC_ACTIVE_LOW)
  934. sens_conf |= 1 << CSI_SENS_CONF_VSYNC_POL_SHIFT;
  935. if (common_flags & SOCAM_DATA_ACTIVE_LOW)
  936. sens_conf |= 1 << CSI_SENS_CONF_DATA_POL_SHIFT;
  937. /* Just do what we're asked to do */
  938. switch (xlate->host_fmt->bits_per_sample) {
  939. case 4:
  940. dw = 0 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
  941. break;
  942. case 8:
  943. dw = 1 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
  944. break;
  945. case 10:
  946. dw = 2 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
  947. break;
  948. default:
  949. /*
  950. * Actually it can only be 15 now, default is just to silence
  951. * compiler warnings
  952. */
  953. case 15:
  954. dw = 3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
  955. }
  956. csi_reg_write(mx3_cam, sens_conf | dw, CSI_SENS_CONF);
  957. dev_dbg(dev, "Set SENS_CONF to %x\n", sens_conf | dw);
  958. return 0;
  959. }
  960. static struct soc_camera_host_ops mx3_soc_camera_host_ops = {
  961. .owner = THIS_MODULE,
  962. .add = mx3_camera_add_device,
  963. .remove = mx3_camera_remove_device,
  964. .set_crop = mx3_camera_set_crop,
  965. .set_fmt = mx3_camera_set_fmt,
  966. .try_fmt = mx3_camera_try_fmt,
  967. .get_formats = mx3_camera_get_formats,
  968. .init_videobuf2 = mx3_camera_init_videobuf,
  969. .reqbufs = mx3_camera_reqbufs,
  970. .poll = mx3_camera_poll,
  971. .querycap = mx3_camera_querycap,
  972. .set_bus_param = mx3_camera_set_bus_param,
  973. };
  974. static int __devinit mx3_camera_probe(struct platform_device *pdev)
  975. {
  976. struct mx3_camera_dev *mx3_cam;
  977. struct resource *res;
  978. void __iomem *base;
  979. int err = 0;
  980. struct soc_camera_host *soc_host;
  981. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  982. if (!res) {
  983. err = -ENODEV;
  984. goto egetres;
  985. }
  986. mx3_cam = vzalloc(sizeof(*mx3_cam));
  987. if (!mx3_cam) {
  988. dev_err(&pdev->dev, "Could not allocate mx3 camera object\n");
  989. err = -ENOMEM;
  990. goto ealloc;
  991. }
  992. mx3_cam->clk = clk_get(&pdev->dev, NULL);
  993. if (IS_ERR(mx3_cam->clk)) {
  994. err = PTR_ERR(mx3_cam->clk);
  995. goto eclkget;
  996. }
  997. mx3_cam->pdata = pdev->dev.platform_data;
  998. mx3_cam->platform_flags = mx3_cam->pdata->flags;
  999. if (!(mx3_cam->platform_flags & (MX3_CAMERA_DATAWIDTH_4 |
  1000. MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10 |
  1001. MX3_CAMERA_DATAWIDTH_15))) {
  1002. /*
  1003. * Platform hasn't set available data widths. This is bad.
  1004. * Warn and use a default.
  1005. */
  1006. dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
  1007. "data widths, using default 8 bit\n");
  1008. mx3_cam->platform_flags |= MX3_CAMERA_DATAWIDTH_8;
  1009. }
  1010. mx3_cam->mclk = mx3_cam->pdata->mclk_10khz * 10000;
  1011. if (!mx3_cam->mclk) {
  1012. dev_warn(&pdev->dev,
  1013. "mclk_10khz == 0! Please, fix your platform data. "
  1014. "Using default 20MHz\n");
  1015. mx3_cam->mclk = 20000000;
  1016. }
  1017. /* list of video-buffers */
  1018. INIT_LIST_HEAD(&mx3_cam->capture);
  1019. spin_lock_init(&mx3_cam->lock);
  1020. base = ioremap(res->start, resource_size(res));
  1021. if (!base) {
  1022. pr_err("Couldn't map %x@%x\n", resource_size(res), res->start);
  1023. err = -ENOMEM;
  1024. goto eioremap;
  1025. }
  1026. mx3_cam->base = base;
  1027. soc_host = &mx3_cam->soc_host;
  1028. soc_host->drv_name = MX3_CAM_DRV_NAME;
  1029. soc_host->ops = &mx3_soc_camera_host_ops;
  1030. soc_host->priv = mx3_cam;
  1031. soc_host->v4l2_dev.dev = &pdev->dev;
  1032. soc_host->nr = pdev->id;
  1033. mx3_cam->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
  1034. if (IS_ERR(mx3_cam->alloc_ctx)) {
  1035. err = PTR_ERR(mx3_cam->alloc_ctx);
  1036. goto eallocctx;
  1037. }
  1038. err = soc_camera_host_register(soc_host);
  1039. if (err)
  1040. goto ecamhostreg;
  1041. /* IDMAC interface */
  1042. dmaengine_get();
  1043. return 0;
  1044. ecamhostreg:
  1045. vb2_dma_contig_cleanup_ctx(mx3_cam->alloc_ctx);
  1046. eallocctx:
  1047. iounmap(base);
  1048. eioremap:
  1049. clk_put(mx3_cam->clk);
  1050. eclkget:
  1051. vfree(mx3_cam);
  1052. ealloc:
  1053. egetres:
  1054. return err;
  1055. }
  1056. static int __devexit mx3_camera_remove(struct platform_device *pdev)
  1057. {
  1058. struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
  1059. struct mx3_camera_dev *mx3_cam = container_of(soc_host,
  1060. struct mx3_camera_dev, soc_host);
  1061. clk_put(mx3_cam->clk);
  1062. soc_camera_host_unregister(soc_host);
  1063. iounmap(mx3_cam->base);
  1064. /*
  1065. * The channel has either not been allocated,
  1066. * or should have been released
  1067. */
  1068. if (WARN_ON(mx3_cam->idmac_channel[0]))
  1069. dma_release_channel(&mx3_cam->idmac_channel[0]->dma_chan);
  1070. vb2_dma_contig_cleanup_ctx(mx3_cam->alloc_ctx);
  1071. vfree(mx3_cam);
  1072. dmaengine_put();
  1073. dev_info(&pdev->dev, "i.MX3x Camera driver unloaded\n");
  1074. return 0;
  1075. }
  1076. static struct platform_driver mx3_camera_driver = {
  1077. .driver = {
  1078. .name = MX3_CAM_DRV_NAME,
  1079. },
  1080. .probe = mx3_camera_probe,
  1081. .remove = __devexit_p(mx3_camera_remove),
  1082. };
  1083. static int __init mx3_camera_init(void)
  1084. {
  1085. return platform_driver_register(&mx3_camera_driver);
  1086. }
  1087. static void __exit mx3_camera_exit(void)
  1088. {
  1089. platform_driver_unregister(&mx3_camera_driver);
  1090. }
  1091. module_init(mx3_camera_init);
  1092. module_exit(mx3_camera_exit);
  1093. MODULE_DESCRIPTION("i.MX3x SoC Camera Host driver");
  1094. MODULE_AUTHOR("Guennadi Liakhovetski <lg@denx.de>");
  1095. MODULE_LICENSE("GPL v2");
  1096. MODULE_ALIAS("platform:" MX3_CAM_DRV_NAME);