/drivers/media/video/sun5i/sun5i_cedar.h
C Header | 127 lines | 70 code | 15 blank | 42 comment | 0 complexity | a3ef7996d287acaef81d2ce96a90aa68 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
1/* 2 * drivers/media/video/sun5i/sun5i_cedar.h 3 * 4 * (C) Copyright 2007-2012 5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23/* 24************************************************************************************************************** 25* eLDK 26* the Easy Portable/Player Develop Kits 27* desktop system 28* 29* (c) Copyright 2009-2012, ,HUANGXIN China 30* All Rights Reserved 31* 32* File : sun4i_cedar.h 33* By : HUANGXIN 34* Func : 35* Version : v1.0 36* ============================================================================================================ 37* 2011-5-25 9:57:05 HUANGXIN create this file, implements the fundemental interface; 38************************************************************************************************************** 39*/ 40#ifndef _SUN4I_CEDAR_H_ 41#define _SUN4I_CEDAR_H_ 42 43enum IOCTL_CMD { 44 IOCTL_UNKOWN = 0x100, 45 IOCTL_GET_ENV_INFO, 46 IOCTL_WAIT_VE, 47 IOCTL_RESET_VE, 48 IOCTL_ENABLE_VE, 49 IOCTL_DISABLE_VE, 50 IOCTL_SET_VE_FREQ, 51 52 IOCTL_CONFIG_AVS2 = 0x200, 53 IOCTL_GETVALUE_AVS2 , 54 IOCTL_PAUSE_AVS2 , 55 IOCTL_START_AVS2 , 56 IOCTL_RESET_AVS2 , 57 IOCTL_ADJUST_AVS2, 58 IOCTL_ENGINE_REQ, 59 IOCTL_ENGINE_REL, 60 IOCTL_ENGINE_CHECK_DELAY, 61 IOCTL_GET_IC_VER, 62 63 IOCTL_ADJUST_AVS2_ABS, 64}; 65 66struct cedarv_env_infomation{ 67 unsigned int phymem_start; 68 int phymem_total_size; 69 unsigned int address_macc; 70}; 71 72struct __cedarv_task { 73 int task_prio; 74 int ID; 75 unsigned long timeout; 76 unsigned int frametime; 77 unsigned int block_mode; 78}; 79 80struct cedarv_engine_task { 81 struct __cedarv_task t; 82 struct list_head list; 83 struct task_struct *task_handle; 84 unsigned int status; 85 unsigned int running; 86 unsigned int is_first_task; 87}; 88 89/*?????task_prio??????task?frametime??????task_prio??task????????total_time*/ 90struct cedarv_engine_task_info { 91 int task_prio; 92 unsigned int frametime; 93 unsigned int total_time; 94}; 95 96/*--------------------------------------------------------------------------------*/ 97#define REGS_pBASE (0x01C00000) // register base addr 98 99#define SRAM_REGS_pBASE (REGS_pBASE + 0x00000) // SRAM Controller 100#define CCMU_REGS_pBASE (REGS_pBASE + 0x20000) // clock manager unit 101#define MACC_REGS_pBASE (REGS_pBASE + 0x0E000) // media accelerate VE 102#define SS_REGS_pBASE (REGS_pBASE + 0x15000) // Security System 103#define SDRAM_REGS_pBASE (REGS_pBASE + 0x01000) // SDRAM Controller 104#define AVS_REGS_pBASE (REGS_pBASE + 0x20c00) 105 106#define SRAM_REGS_BASE SRAM_REGS_pBASE // SRAM Controller 107#define CCMU_REGS_BASE CCMU_REGS_pBASE // Clock Control manager unit OK 108#define MACC_REGS_BASE MACC_REGS_pBASE // Media ACCelerate 109#define SS_REGS_BASE SS_REGS_pBASE // Security System 110#define SDRAM_REGS_BASE SDRAM_REGS_pBASE //SDRAM Controller OK 111#define AVS_REGS_BASE AVS_REGS_pBASE 112 113#define MPEG_REGS_BASE (MACC_REGS_BASE + 0x100) // MPEG engine 114#define H264_REGS_BASE (MACC_REGS_BASE + 0x200) // H264 engine 115#define VC1_REGS_BASE (MACC_REGS_BASE + 0x300) // VC-1 engine 116 117#define SRAM_REGS_SIZE (4096) // 4K 118#define CCMU_REGS_SIZE (1024) // 1K 119#define MACC_REGS_SIZE (4096) // 4K 120#define SS_REGS_SIZE (4096) // 4K 121/*--------------------------------------------------------------------------------*/ 122 123#define SRAM_REG_o_CFG (0x00) 124#define SRAM_REG_ADDR_CFG (SRAM_REGS_BASE + SRAM_REG_o_CFG) // SRAM MAP Cfg Reg 0 125/*--------------------------------------------------------------------------------*/ 126 127#endif