/drivers/media/video/cx231xx/cx231xx-avcore.c

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  1. /*
  2. cx231xx_avcore.c - driver for Conexant Cx23100/101/102
  3. USB video capture devices
  4. Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
  5. This program contains the specific code to control the avdecoder chip and
  6. other related usb control functions for cx231xx based chipset.
  7. This program is free software; you can redistribute it and/or modify
  8. it under the terms of the GNU General Public License as published by
  9. the Free Software Foundation; either version 2 of the License, or
  10. (at your option) any later version.
  11. This program is distributed in the hope that it will be useful,
  12. but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License
  16. along with this program; if not, write to the Free Software
  17. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. */
  19. #include <linux/init.h>
  20. #include <linux/list.h>
  21. #include <linux/module.h>
  22. #include <linux/kernel.h>
  23. #include <linux/bitmap.h>
  24. #include <linux/usb.h>
  25. #include <linux/i2c.h>
  26. #include <linux/mm.h>
  27. #include <linux/mutex.h>
  28. #include <media/tuner.h>
  29. #include <media/v4l2-common.h>
  30. #include <media/v4l2-ioctl.h>
  31. #include <media/v4l2-chip-ident.h>
  32. #include "cx231xx.h"
  33. #include "cx231xx-dif.h"
  34. #define TUNER_MODE_FM_RADIO 0
  35. /******************************************************************************
  36. -: BLOCK ARRANGEMENT :-
  37. I2S block ----------------------|
  38. [I2S audio] |
  39. |
  40. Analog Front End --> Direct IF -|-> Cx25840 --> Audio
  41. [video & audio] | [Audio]
  42. |
  43. |-> Cx25840 --> Video
  44. [Video]
  45. *******************************************************************************/
  46. /******************************************************************************
  47. * VERVE REGISTER *
  48. * *
  49. ******************************************************************************/
  50. static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data)
  51. {
  52. return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS,
  53. saddr, 1, data, 1);
  54. }
  55. static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data)
  56. {
  57. int status;
  58. u32 temp = 0;
  59. status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS,
  60. saddr, 1, &temp, 1);
  61. *data = (u8) temp;
  62. return status;
  63. }
  64. void initGPIO(struct cx231xx *dev)
  65. {
  66. u32 _gpio_direction = 0;
  67. u32 value = 0;
  68. u8 val = 0;
  69. _gpio_direction = _gpio_direction & 0xFC0003FF;
  70. _gpio_direction = _gpio_direction | 0x03FDFC00;
  71. cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0);
  72. verve_read_byte(dev, 0x07, &val);
  73. cx231xx_info(" verve_read_byte address0x07=0x%x\n", val);
  74. verve_write_byte(dev, 0x07, 0xF4);
  75. verve_read_byte(dev, 0x07, &val);
  76. cx231xx_info(" verve_read_byte address0x07=0x%x\n", val);
  77. cx231xx_capture_start(dev, 1, 2);
  78. cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00);
  79. cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF);
  80. }
  81. void uninitGPIO(struct cx231xx *dev)
  82. {
  83. u8 value[4] = { 0, 0, 0, 0 };
  84. cx231xx_capture_start(dev, 0, 2);
  85. verve_write_byte(dev, 0x07, 0x14);
  86. cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
  87. 0x68, value, 4);
  88. }
  89. /******************************************************************************
  90. * A F E - B L O C K C O N T R O L functions *
  91. * [ANALOG FRONT END] *
  92. ******************************************************************************/
  93. static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
  94. {
  95. return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS,
  96. saddr, 2, data, 1);
  97. }
  98. static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
  99. {
  100. int status;
  101. u32 temp = 0;
  102. status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
  103. saddr, 2, &temp, 1);
  104. *data = (u8) temp;
  105. return status;
  106. }
  107. int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count)
  108. {
  109. int status = 0;
  110. u8 temp = 0;
  111. u8 afe_power_status = 0;
  112. int i = 0;
  113. /* super block initialize */
  114. temp = (u8) (ref_count & 0xff);
  115. status = afe_write_byte(dev, SUP_BLK_TUNE2, temp);
  116. if (status < 0)
  117. return status;
  118. status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status);
  119. if (status < 0)
  120. return status;
  121. temp = (u8) ((ref_count & 0x300) >> 8);
  122. temp |= 0x40;
  123. status = afe_write_byte(dev, SUP_BLK_TUNE1, temp);
  124. if (status < 0)
  125. return status;
  126. status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f);
  127. if (status < 0)
  128. return status;
  129. /* enable pll */
  130. while (afe_power_status != 0x18) {
  131. status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18);
  132. if (status < 0) {
  133. cx231xx_info(
  134. ": Init Super Block failed in send cmd\n");
  135. break;
  136. }
  137. status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status);
  138. afe_power_status &= 0xff;
  139. if (status < 0) {
  140. cx231xx_info(
  141. ": Init Super Block failed in receive cmd\n");
  142. break;
  143. }
  144. i++;
  145. if (i == 10) {
  146. cx231xx_info(
  147. ": Init Super Block force break in loop !!!!\n");
  148. status = -1;
  149. break;
  150. }
  151. }
  152. if (status < 0)
  153. return status;
  154. /* start tuning filter */
  155. status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40);
  156. if (status < 0)
  157. return status;
  158. msleep(5);
  159. /* exit tuning */
  160. status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00);
  161. return status;
  162. }
  163. int cx231xx_afe_init_channels(struct cx231xx *dev)
  164. {
  165. int status = 0;
  166. /* power up all 3 channels, clear pd_buffer */
  167. status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00);
  168. status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00);
  169. status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00);
  170. /* Enable quantizer calibration */
  171. status = afe_write_byte(dev, ADC_COM_QUANT, 0x02);
  172. /* channel initialize, force modulator (fb) reset */
  173. status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17);
  174. status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17);
  175. status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17);
  176. /* start quantilizer calibration */
  177. status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10);
  178. status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10);
  179. status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10);
  180. msleep(5);
  181. /* exit modulator (fb) reset */
  182. status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07);
  183. status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07);
  184. status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07);
  185. /* enable the pre_clamp in each channel for single-ended input */
  186. status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0);
  187. status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0);
  188. status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0);
  189. /* use diode instead of resistor, so set term_en to 0, res_en to 0 */
  190. status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
  191. ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00);
  192. status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
  193. ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00);
  194. status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
  195. ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00);
  196. /* dynamic element matching off */
  197. status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03);
  198. status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03);
  199. status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03);
  200. return status;
  201. }
  202. int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev)
  203. {
  204. u8 c_value = 0;
  205. int status = 0;
  206. status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value);
  207. c_value &= (~(0x50));
  208. status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value);
  209. return status;
  210. }
  211. /*
  212. The Analog Front End in Cx231xx has 3 channels. These
  213. channels are used to share between different inputs
  214. like tuner, s-video and composite inputs.
  215. channel 1 ----- pin 1 to pin4(in reg is 1-4)
  216. channel 2 ----- pin 5 to pin8(in reg is 5-8)
  217. channel 3 ----- pin 9 to pin 12(in reg is 9-11)
  218. */
  219. int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux)
  220. {
  221. u8 ch1_setting = (u8) input_mux;
  222. u8 ch2_setting = (u8) (input_mux >> 8);
  223. u8 ch3_setting = (u8) (input_mux >> 16);
  224. int status = 0;
  225. u8 value = 0;
  226. if (ch1_setting != 0) {
  227. status = afe_read_byte(dev, ADC_INPUT_CH1, &value);
  228. value &= ~INPUT_SEL_MASK;
  229. value |= (ch1_setting - 1) << 4;
  230. value &= 0xff;
  231. status = afe_write_byte(dev, ADC_INPUT_CH1, value);
  232. }
  233. if (ch2_setting != 0) {
  234. status = afe_read_byte(dev, ADC_INPUT_CH2, &value);
  235. value &= ~INPUT_SEL_MASK;
  236. value |= (ch2_setting - 1) << 4;
  237. value &= 0xff;
  238. status = afe_write_byte(dev, ADC_INPUT_CH2, value);
  239. }
  240. /* For ch3_setting, the value to put in the register is
  241. 7 less than the input number */
  242. if (ch3_setting != 0) {
  243. status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
  244. value &= ~INPUT_SEL_MASK;
  245. value |= (ch3_setting - 1) << 4;
  246. value &= 0xff;
  247. status = afe_write_byte(dev, ADC_INPUT_CH3, value);
  248. }
  249. return status;
  250. }
  251. int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
  252. {
  253. int status = 0;
  254. /*
  255. * FIXME: We need to implement the AFE code for LOW IF and for HI IF.
  256. * Currently, only baseband works.
  257. */
  258. switch (mode) {
  259. case AFE_MODE_LOW_IF:
  260. cx231xx_Setup_AFE_for_LowIF(dev);
  261. break;
  262. case AFE_MODE_BASEBAND:
  263. status = cx231xx_afe_setup_AFE_for_baseband(dev);
  264. break;
  265. case AFE_MODE_EU_HI_IF:
  266. /* SetupAFEforEuHiIF(); */
  267. break;
  268. case AFE_MODE_US_HI_IF:
  269. /* SetupAFEforUsHiIF(); */
  270. break;
  271. case AFE_MODE_JAPAN_HI_IF:
  272. /* SetupAFEforJapanHiIF(); */
  273. break;
  274. }
  275. if ((mode != dev->afe_mode) &&
  276. (dev->video_input == CX231XX_VMUX_TELEVISION))
  277. status = cx231xx_afe_adjust_ref_count(dev,
  278. CX231XX_VMUX_TELEVISION);
  279. dev->afe_mode = mode;
  280. return status;
  281. }
  282. int cx231xx_afe_update_power_control(struct cx231xx *dev,
  283. enum AV_MODE avmode)
  284. {
  285. u8 afe_power_status = 0;
  286. int status = 0;
  287. switch (dev->model) {
  288. case CX231XX_BOARD_CNXT_CARRAERA:
  289. case CX231XX_BOARD_CNXT_RDE_250:
  290. case CX231XX_BOARD_CNXT_SHELBY:
  291. case CX231XX_BOARD_CNXT_RDU_250:
  292. case CX231XX_BOARD_CNXT_RDE_253S:
  293. case CX231XX_BOARD_CNXT_RDU_253S:
  294. case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
  295. case CX231XX_BOARD_HAUPPAUGE_EXETER:
  296. case CX231XX_BOARD_HAUPPAUGE_USBLIVE2:
  297. case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID:
  298. if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
  299. while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
  300. FLD_PWRDN_ENABLE_PLL)) {
  301. status = afe_write_byte(dev, SUP_BLK_PWRDN,
  302. FLD_PWRDN_TUNING_BIAS |
  303. FLD_PWRDN_ENABLE_PLL);
  304. status |= afe_read_byte(dev, SUP_BLK_PWRDN,
  305. &afe_power_status);
  306. if (status < 0)
  307. break;
  308. }
  309. status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
  310. 0x00);
  311. status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
  312. 0x00);
  313. status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
  314. 0x00);
  315. } else if (avmode == POLARIS_AVMODE_DIGITAL) {
  316. status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
  317. 0x70);
  318. status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
  319. 0x70);
  320. status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
  321. 0x70);
  322. status |= afe_read_byte(dev, SUP_BLK_PWRDN,
  323. &afe_power_status);
  324. afe_power_status |= FLD_PWRDN_PD_BANDGAP |
  325. FLD_PWRDN_PD_BIAS |
  326. FLD_PWRDN_PD_TUNECK;
  327. status |= afe_write_byte(dev, SUP_BLK_PWRDN,
  328. afe_power_status);
  329. } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
  330. while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
  331. FLD_PWRDN_ENABLE_PLL)) {
  332. status = afe_write_byte(dev, SUP_BLK_PWRDN,
  333. FLD_PWRDN_TUNING_BIAS |
  334. FLD_PWRDN_ENABLE_PLL);
  335. status |= afe_read_byte(dev, SUP_BLK_PWRDN,
  336. &afe_power_status);
  337. if (status < 0)
  338. break;
  339. }
  340. status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
  341. 0x00);
  342. status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
  343. 0x00);
  344. status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
  345. 0x00);
  346. } else {
  347. cx231xx_info("Invalid AV mode input\n");
  348. status = -1;
  349. }
  350. break;
  351. default:
  352. if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
  353. while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
  354. FLD_PWRDN_ENABLE_PLL)) {
  355. status = afe_write_byte(dev, SUP_BLK_PWRDN,
  356. FLD_PWRDN_TUNING_BIAS |
  357. FLD_PWRDN_ENABLE_PLL);
  358. status |= afe_read_byte(dev, SUP_BLK_PWRDN,
  359. &afe_power_status);
  360. if (status < 0)
  361. break;
  362. }
  363. status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
  364. 0x40);
  365. status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
  366. 0x40);
  367. status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
  368. 0x00);
  369. } else if (avmode == POLARIS_AVMODE_DIGITAL) {
  370. status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
  371. 0x70);
  372. status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
  373. 0x70);
  374. status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
  375. 0x70);
  376. status |= afe_read_byte(dev, SUP_BLK_PWRDN,
  377. &afe_power_status);
  378. afe_power_status |= FLD_PWRDN_PD_BANDGAP |
  379. FLD_PWRDN_PD_BIAS |
  380. FLD_PWRDN_PD_TUNECK;
  381. status |= afe_write_byte(dev, SUP_BLK_PWRDN,
  382. afe_power_status);
  383. } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
  384. while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
  385. FLD_PWRDN_ENABLE_PLL)) {
  386. status = afe_write_byte(dev, SUP_BLK_PWRDN,
  387. FLD_PWRDN_TUNING_BIAS |
  388. FLD_PWRDN_ENABLE_PLL);
  389. status |= afe_read_byte(dev, SUP_BLK_PWRDN,
  390. &afe_power_status);
  391. if (status < 0)
  392. break;
  393. }
  394. status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
  395. 0x00);
  396. status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
  397. 0x00);
  398. status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
  399. 0x40);
  400. } else {
  401. cx231xx_info("Invalid AV mode input\n");
  402. status = -1;
  403. }
  404. } /* switch */
  405. return status;
  406. }
  407. int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input)
  408. {
  409. u8 input_mode = 0;
  410. u8 ntf_mode = 0;
  411. int status = 0;
  412. dev->video_input = video_input;
  413. if (video_input == CX231XX_VMUX_TELEVISION) {
  414. status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode);
  415. status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3,
  416. &ntf_mode);
  417. } else {
  418. status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode);
  419. status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1,
  420. &ntf_mode);
  421. }
  422. input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1);
  423. switch (input_mode) {
  424. case SINGLE_ENDED:
  425. dev->afe_ref_count = 0x23C;
  426. break;
  427. case LOW_IF:
  428. dev->afe_ref_count = 0x24C;
  429. break;
  430. case EU_IF:
  431. dev->afe_ref_count = 0x258;
  432. break;
  433. case US_IF:
  434. dev->afe_ref_count = 0x260;
  435. break;
  436. default:
  437. break;
  438. }
  439. status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count);
  440. return status;
  441. }
  442. /******************************************************************************
  443. * V I D E O / A U D I O D E C O D E R C O N T R O L functions *
  444. ******************************************************************************/
  445. static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
  446. {
  447. return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
  448. saddr, 2, data, 1);
  449. }
  450. static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
  451. {
  452. int status;
  453. u32 temp = 0;
  454. status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
  455. saddr, 2, &temp, 1);
  456. *data = (u8) temp;
  457. return status;
  458. }
  459. static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data)
  460. {
  461. return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
  462. saddr, 2, data, 4);
  463. }
  464. static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data)
  465. {
  466. return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
  467. saddr, 2, data, 4);
  468. }
  469. int cx231xx_check_fw(struct cx231xx *dev)
  470. {
  471. u8 temp = 0;
  472. int status = 0;
  473. status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp);
  474. if (status < 0)
  475. return status;
  476. else
  477. return temp;
  478. }
  479. int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
  480. {
  481. int status = 0;
  482. switch (INPUT(input)->type) {
  483. case CX231XX_VMUX_COMPOSITE1:
  484. case CX231XX_VMUX_SVIDEO:
  485. if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
  486. (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) {
  487. /* External AV */
  488. status = cx231xx_set_power_mode(dev,
  489. POLARIS_AVMODE_ENXTERNAL_AV);
  490. if (status < 0) {
  491. cx231xx_errdev("%s: set_power_mode : Failed to"
  492. " set Power - errCode [%d]!\n",
  493. __func__, status);
  494. return status;
  495. }
  496. }
  497. status = cx231xx_set_decoder_video_input(dev,
  498. INPUT(input)->type,
  499. INPUT(input)->vmux);
  500. break;
  501. case CX231XX_VMUX_TELEVISION:
  502. case CX231XX_VMUX_CABLE:
  503. if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
  504. (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) {
  505. /* Tuner */
  506. status = cx231xx_set_power_mode(dev,
  507. POLARIS_AVMODE_ANALOGT_TV);
  508. if (status < 0) {
  509. cx231xx_errdev("%s: set_power_mode:Failed"
  510. " to set Power - errCode [%d]!\n",
  511. __func__, status);
  512. return status;
  513. }
  514. }
  515. if (dev->tuner_type == TUNER_NXP_TDA18271)
  516. status = cx231xx_set_decoder_video_input(dev,
  517. CX231XX_VMUX_TELEVISION,
  518. INPUT(input)->vmux);
  519. else
  520. status = cx231xx_set_decoder_video_input(dev,
  521. CX231XX_VMUX_COMPOSITE1,
  522. INPUT(input)->vmux);
  523. break;
  524. default:
  525. cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n",
  526. __func__, INPUT(input)->type);
  527. break;
  528. }
  529. /* save the selection */
  530. dev->video_input = input;
  531. return status;
  532. }
  533. int cx231xx_set_decoder_video_input(struct cx231xx *dev,
  534. u8 pin_type, u8 input)
  535. {
  536. int status = 0;
  537. u32 value = 0;
  538. if (pin_type != dev->video_input) {
  539. status = cx231xx_afe_adjust_ref_count(dev, pin_type);
  540. if (status < 0) {
  541. cx231xx_errdev("%s: adjust_ref_count :Failed to set"
  542. "AFE input mux - errCode [%d]!\n",
  543. __func__, status);
  544. return status;
  545. }
  546. }
  547. /* call afe block to set video inputs */
  548. status = cx231xx_afe_set_input_mux(dev, input);
  549. if (status < 0) {
  550. cx231xx_errdev("%s: set_input_mux :Failed to set"
  551. " AFE input mux - errCode [%d]!\n",
  552. __func__, status);
  553. return status;
  554. }
  555. switch (pin_type) {
  556. case CX231XX_VMUX_COMPOSITE1:
  557. status = vid_blk_read_word(dev, AFE_CTRL, &value);
  558. value |= (0 << 13) | (1 << 4);
  559. value &= ~(1 << 5);
  560. /* set [24:23] [22:15] to 0 */
  561. value &= (~(0x1ff8000));
  562. /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
  563. value |= 0x1000000;
  564. status = vid_blk_write_word(dev, AFE_CTRL, value);
  565. status = vid_blk_read_word(dev, OUT_CTRL1, &value);
  566. value |= (1 << 7);
  567. status = vid_blk_write_word(dev, OUT_CTRL1, value);
  568. /* Set output mode */
  569. status = cx231xx_read_modify_write_i2c_dword(dev,
  570. VID_BLK_I2C_ADDRESS,
  571. OUT_CTRL1,
  572. FLD_OUT_MODE,
  573. dev->board.output_mode);
  574. /* Tell DIF object to go to baseband mode */
  575. status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
  576. if (status < 0) {
  577. cx231xx_errdev("%s: cx231xx_dif set to By pass"
  578. " mode- errCode [%d]!\n",
  579. __func__, status);
  580. return status;
  581. }
  582. /* Read the DFE_CTRL1 register */
  583. status = vid_blk_read_word(dev, DFE_CTRL1, &value);
  584. /* enable the VBI_GATE_EN */
  585. value |= FLD_VBI_GATE_EN;
  586. /* Enable the auto-VGA enable */
  587. value |= FLD_VGA_AUTO_EN;
  588. /* Write it back */
  589. status = vid_blk_write_word(dev, DFE_CTRL1, value);
  590. /* Disable auto config of registers */
  591. status = cx231xx_read_modify_write_i2c_dword(dev,
  592. VID_BLK_I2C_ADDRESS,
  593. MODE_CTRL, FLD_ACFG_DIS,
  594. cx231xx_set_field(FLD_ACFG_DIS, 1));
  595. /* Set CVBS input mode */
  596. status = cx231xx_read_modify_write_i2c_dword(dev,
  597. VID_BLK_I2C_ADDRESS,
  598. MODE_CTRL, FLD_INPUT_MODE,
  599. cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
  600. break;
  601. case CX231XX_VMUX_SVIDEO:
  602. /* Disable the use of DIF */
  603. status = vid_blk_read_word(dev, AFE_CTRL, &value);
  604. /* set [24:23] [22:15] to 0 */
  605. value &= (~(0x1ff8000));
  606. /* set FUNC_MODE[24:23] = 2
  607. IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */
  608. value |= 0x1000010;
  609. status = vid_blk_write_word(dev, AFE_CTRL, value);
  610. /* Tell DIF object to go to baseband mode */
  611. status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
  612. if (status < 0) {
  613. cx231xx_errdev("%s: cx231xx_dif set to By pass"
  614. " mode- errCode [%d]!\n",
  615. __func__, status);
  616. return status;
  617. }
  618. /* Read the DFE_CTRL1 register */
  619. status = vid_blk_read_word(dev, DFE_CTRL1, &value);
  620. /* enable the VBI_GATE_EN */
  621. value |= FLD_VBI_GATE_EN;
  622. /* Enable the auto-VGA enable */
  623. value |= FLD_VGA_AUTO_EN;
  624. /* Write it back */
  625. status = vid_blk_write_word(dev, DFE_CTRL1, value);
  626. /* Disable auto config of registers */
  627. status = cx231xx_read_modify_write_i2c_dword(dev,
  628. VID_BLK_I2C_ADDRESS,
  629. MODE_CTRL, FLD_ACFG_DIS,
  630. cx231xx_set_field(FLD_ACFG_DIS, 1));
  631. /* Set YC input mode */
  632. status = cx231xx_read_modify_write_i2c_dword(dev,
  633. VID_BLK_I2C_ADDRESS,
  634. MODE_CTRL,
  635. FLD_INPUT_MODE,
  636. cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1));
  637. /* Chroma to ADC2 */
  638. status = vid_blk_read_word(dev, AFE_CTRL, &value);
  639. value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */
  640. /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8)
  641. This sets them to use video
  642. rather than audio. Only one of the two will be in use. */
  643. value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3);
  644. status = vid_blk_write_word(dev, AFE_CTRL, value);
  645. status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND);
  646. break;
  647. case CX231XX_VMUX_TELEVISION:
  648. case CX231XX_VMUX_CABLE:
  649. default:
  650. /* TODO: Test if this is also needed for xc2028/xc3028 */
  651. if (dev->board.tuner_type == TUNER_XC5000) {
  652. /* Disable the use of DIF */
  653. status = vid_blk_read_word(dev, AFE_CTRL, &value);
  654. value |= (0 << 13) | (1 << 4);
  655. value &= ~(1 << 5);
  656. /* set [24:23] [22:15] to 0 */
  657. value &= (~(0x1FF8000));
  658. /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
  659. value |= 0x1000000;
  660. status = vid_blk_write_word(dev, AFE_CTRL, value);
  661. status = vid_blk_read_word(dev, OUT_CTRL1, &value);
  662. value |= (1 << 7);
  663. status = vid_blk_write_word(dev, OUT_CTRL1, value);
  664. /* Set output mode */
  665. status = cx231xx_read_modify_write_i2c_dword(dev,
  666. VID_BLK_I2C_ADDRESS,
  667. OUT_CTRL1, FLD_OUT_MODE,
  668. dev->board.output_mode);
  669. /* Tell DIF object to go to baseband mode */
  670. status = cx231xx_dif_set_standard(dev,
  671. DIF_USE_BASEBAND);
  672. if (status < 0) {
  673. cx231xx_errdev("%s: cx231xx_dif set to By pass"
  674. " mode- errCode [%d]!\n",
  675. __func__, status);
  676. return status;
  677. }
  678. /* Read the DFE_CTRL1 register */
  679. status = vid_blk_read_word(dev, DFE_CTRL1, &value);
  680. /* enable the VBI_GATE_EN */
  681. value |= FLD_VBI_GATE_EN;
  682. /* Enable the auto-VGA enable */
  683. value |= FLD_VGA_AUTO_EN;
  684. /* Write it back */
  685. status = vid_blk_write_word(dev, DFE_CTRL1, value);
  686. /* Disable auto config of registers */
  687. status = cx231xx_read_modify_write_i2c_dword(dev,
  688. VID_BLK_I2C_ADDRESS,
  689. MODE_CTRL, FLD_ACFG_DIS,
  690. cx231xx_set_field(FLD_ACFG_DIS, 1));
  691. /* Set CVBS input mode */
  692. status = cx231xx_read_modify_write_i2c_dword(dev,
  693. VID_BLK_I2C_ADDRESS,
  694. MODE_CTRL, FLD_INPUT_MODE,
  695. cx231xx_set_field(FLD_INPUT_MODE,
  696. INPUT_MODE_CVBS_0));
  697. } else {
  698. /* Enable the DIF for the tuner */
  699. /* Reinitialize the DIF */
  700. status = cx231xx_dif_set_standard(dev, dev->norm);
  701. if (status < 0) {
  702. cx231xx_errdev("%s: cx231xx_dif set to By pass"
  703. " mode- errCode [%d]!\n",
  704. __func__, status);
  705. return status;
  706. }
  707. /* Make sure bypass is cleared */
  708. status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value);
  709. /* Clear the bypass bit */
  710. value &= ~FLD_DIF_DIF_BYPASS;
  711. /* Enable the use of the DIF block */
  712. status = vid_blk_write_word(dev, DIF_MISC_CTRL, value);
  713. /* Read the DFE_CTRL1 register */
  714. status = vid_blk_read_word(dev, DFE_CTRL1, &value);
  715. /* Disable the VBI_GATE_EN */
  716. value &= ~FLD_VBI_GATE_EN;
  717. /* Enable the auto-VGA enable, AGC, and
  718. set the skip count to 2 */
  719. value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000;
  720. /* Write it back */
  721. status = vid_blk_write_word(dev, DFE_CTRL1, value);
  722. /* Wait until AGC locks up */
  723. msleep(1);
  724. /* Disable the auto-VGA enable AGC */
  725. value &= ~(FLD_VGA_AUTO_EN);
  726. /* Write it back */
  727. status = vid_blk_write_word(dev, DFE_CTRL1, value);
  728. /* Enable Polaris B0 AGC output */
  729. status = vid_blk_read_word(dev, PIN_CTRL, &value);
  730. value |= (FLD_OEF_AGC_RF) |
  731. (FLD_OEF_AGC_IFVGA) |
  732. (FLD_OEF_AGC_IF);
  733. status = vid_blk_write_word(dev, PIN_CTRL, value);
  734. /* Set output mode */
  735. status = cx231xx_read_modify_write_i2c_dword(dev,
  736. VID_BLK_I2C_ADDRESS,
  737. OUT_CTRL1, FLD_OUT_MODE,
  738. dev->board.output_mode);
  739. /* Disable auto config of registers */
  740. status = cx231xx_read_modify_write_i2c_dword(dev,
  741. VID_BLK_I2C_ADDRESS,
  742. MODE_CTRL, FLD_ACFG_DIS,
  743. cx231xx_set_field(FLD_ACFG_DIS, 1));
  744. /* Set CVBS input mode */
  745. status = cx231xx_read_modify_write_i2c_dword(dev,
  746. VID_BLK_I2C_ADDRESS,
  747. MODE_CTRL, FLD_INPUT_MODE,
  748. cx231xx_set_field(FLD_INPUT_MODE,
  749. INPUT_MODE_CVBS_0));
  750. /* Set some bits in AFE_CTRL so that channel 2 or 3
  751. * is ready to receive audio */
  752. /* Clear clamp for channels 2 and 3 (bit 16-17) */
  753. /* Clear droop comp (bit 19-20) */
  754. /* Set VGA_SEL (for audio control) (bit 7-8) */
  755. status = vid_blk_read_word(dev, AFE_CTRL, &value);
  756. /*Set Func mode:01-DIF 10-baseband 11-YUV*/
  757. value &= (~(FLD_FUNC_MODE));
  758. value |= 0x800000;
  759. value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;
  760. status = vid_blk_write_word(dev, AFE_CTRL, value);
  761. if (dev->tuner_type == TUNER_NXP_TDA18271) {
  762. status = vid_blk_read_word(dev, PIN_CTRL,
  763. &value);
  764. status = vid_blk_write_word(dev, PIN_CTRL,
  765. (value & 0xFFFFFFEF));
  766. }
  767. break;
  768. }
  769. break;
  770. }
  771. /* Set raw VBI mode */
  772. status = cx231xx_read_modify_write_i2c_dword(dev,
  773. VID_BLK_I2C_ADDRESS,
  774. OUT_CTRL1, FLD_VBIHACTRAW_EN,
  775. cx231xx_set_field(FLD_VBIHACTRAW_EN, 1));
  776. status = vid_blk_read_word(dev, OUT_CTRL1, &value);
  777. if (value & 0x02) {
  778. value |= (1 << 19);
  779. status = vid_blk_write_word(dev, OUT_CTRL1, value);
  780. }
  781. return status;
  782. }
  783. void cx231xx_enable656(struct cx231xx *dev)
  784. {
  785. u8 temp = 0;
  786. int status;
  787. /*enable TS1 data[0:7] as output to export 656*/
  788. status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF);
  789. /*enable TS1 clock as output to export 656*/
  790. status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
  791. temp = temp|0x04;
  792. status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
  793. }
  794. EXPORT_SYMBOL_GPL(cx231xx_enable656);
  795. void cx231xx_disable656(struct cx231xx *dev)
  796. {
  797. u8 temp = 0;
  798. int status;
  799. status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00);
  800. status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
  801. temp = temp&0xFB;
  802. status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
  803. }
  804. EXPORT_SYMBOL_GPL(cx231xx_disable656);
  805. /*
  806. * Handle any video-mode specific overrides that are different
  807. * on a per video standards basis after touching the MODE_CTRL
  808. * register which resets many values for autodetect
  809. */
  810. int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
  811. {
  812. int status = 0;
  813. cx231xx_info("do_mode_ctrl_overrides : 0x%x\n",
  814. (unsigned int)dev->norm);
  815. /* Change the DFE_CTRL3 bp_percent to fix flagging */
  816. status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280);
  817. if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) {
  818. cx231xx_info("do_mode_ctrl_overrides NTSC\n");
  819. /* Move the close caption lines out of active video,
  820. adjust the active video start point */
  821. status = cx231xx_read_modify_write_i2c_dword(dev,
  822. VID_BLK_I2C_ADDRESS,
  823. VERT_TIM_CTRL,
  824. FLD_VBLANK_CNT, 0x18);
  825. status = cx231xx_read_modify_write_i2c_dword(dev,
  826. VID_BLK_I2C_ADDRESS,
  827. VERT_TIM_CTRL,
  828. FLD_VACTIVE_CNT,
  829. 0x1E7000);
  830. status = cx231xx_read_modify_write_i2c_dword(dev,
  831. VID_BLK_I2C_ADDRESS,
  832. VERT_TIM_CTRL,
  833. FLD_V656BLANK_CNT,
  834. 0x1C000000);
  835. status = cx231xx_read_modify_write_i2c_dword(dev,
  836. VID_BLK_I2C_ADDRESS,
  837. HORIZ_TIM_CTRL,
  838. FLD_HBLANK_CNT,
  839. cx231xx_set_field
  840. (FLD_HBLANK_CNT, 0x79));
  841. } else if (dev->norm & V4L2_STD_SECAM) {
  842. cx231xx_info("do_mode_ctrl_overrides SECAM\n");
  843. status = cx231xx_read_modify_write_i2c_dword(dev,
  844. VID_BLK_I2C_ADDRESS,
  845. VERT_TIM_CTRL,
  846. FLD_VBLANK_CNT, 0x20);
  847. status = cx231xx_read_modify_write_i2c_dword(dev,
  848. VID_BLK_I2C_ADDRESS,
  849. VERT_TIM_CTRL,
  850. FLD_VACTIVE_CNT,
  851. cx231xx_set_field
  852. (FLD_VACTIVE_CNT,
  853. 0x244));
  854. status = cx231xx_read_modify_write_i2c_dword(dev,
  855. VID_BLK_I2C_ADDRESS,
  856. VERT_TIM_CTRL,
  857. FLD_V656BLANK_CNT,
  858. cx231xx_set_field
  859. (FLD_V656BLANK_CNT,
  860. 0x24));
  861. /* Adjust the active video horizontal start point */
  862. status = cx231xx_read_modify_write_i2c_dword(dev,
  863. VID_BLK_I2C_ADDRESS,
  864. HORIZ_TIM_CTRL,
  865. FLD_HBLANK_CNT,
  866. cx231xx_set_field
  867. (FLD_HBLANK_CNT, 0x85));
  868. } else {
  869. cx231xx_info("do_mode_ctrl_overrides PAL\n");
  870. status = cx231xx_read_modify_write_i2c_dword(dev,
  871. VID_BLK_I2C_ADDRESS,
  872. VERT_TIM_CTRL,
  873. FLD_VBLANK_CNT, 0x20);
  874. status = cx231xx_read_modify_write_i2c_dword(dev,
  875. VID_BLK_I2C_ADDRESS,
  876. VERT_TIM_CTRL,
  877. FLD_VACTIVE_CNT,
  878. cx231xx_set_field
  879. (FLD_VACTIVE_CNT,
  880. 0x244));
  881. status = cx231xx_read_modify_write_i2c_dword(dev,
  882. VID_BLK_I2C_ADDRESS,
  883. VERT_TIM_CTRL,
  884. FLD_V656BLANK_CNT,
  885. cx231xx_set_field
  886. (FLD_V656BLANK_CNT,
  887. 0x24));
  888. /* Adjust the active video horizontal start point */
  889. status = cx231xx_read_modify_write_i2c_dword(dev,
  890. VID_BLK_I2C_ADDRESS,
  891. HORIZ_TIM_CTRL,
  892. FLD_HBLANK_CNT,
  893. cx231xx_set_field
  894. (FLD_HBLANK_CNT, 0x85));
  895. }
  896. return status;
  897. }
  898. int cx231xx_unmute_audio(struct cx231xx *dev)
  899. {
  900. return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24);
  901. }
  902. EXPORT_SYMBOL_GPL(cx231xx_unmute_audio);
  903. int stopAudioFirmware(struct cx231xx *dev)
  904. {
  905. return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03);
  906. }
  907. int restartAudioFirmware(struct cx231xx *dev)
  908. {
  909. return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13);
  910. }
  911. int cx231xx_set_audio_input(struct cx231xx *dev, u8 input)
  912. {
  913. int status = 0;
  914. enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE;
  915. switch (INPUT(input)->amux) {
  916. case CX231XX_AMUX_VIDEO:
  917. ainput = AUDIO_INPUT_TUNER_TV;
  918. break;
  919. case CX231XX_AMUX_LINE_IN:
  920. status = cx231xx_i2s_blk_set_audio_input(dev, input);
  921. ainput = AUDIO_INPUT_LINE;
  922. break;
  923. default:
  924. break;
  925. }
  926. status = cx231xx_set_audio_decoder_input(dev, ainput);
  927. return status;
  928. }
  929. int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
  930. enum AUDIO_INPUT audio_input)
  931. {
  932. u32 dwval;
  933. int status;
  934. u8 gen_ctrl;
  935. u32 value = 0;
  936. /* Put it in soft reset */
  937. status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
  938. gen_ctrl |= 1;
  939. status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
  940. switch (audio_input) {
  941. case AUDIO_INPUT_LINE:
  942. /* setup AUD_IO control from Merlin paralle output */
  943. value = cx231xx_set_field(FLD_AUD_CHAN1_SRC,
  944. AUD_CHAN_SRC_PARALLEL);
  945. status = vid_blk_write_word(dev, AUD_IO_CTRL, value);
  946. /* setup input to Merlin, SRC2 connect to AC97
  947. bypass upsample-by-2, slave mode, sony mode, left justify
  948. adr 091c, dat 01000000 */
  949. status = vid_blk_read_word(dev, AC97_CTL, &dwval);
  950. status = vid_blk_write_word(dev, AC97_CTL,
  951. (dwval | FLD_AC97_UP2X_BYPASS));
  952. /* select the parallel1 and SRC3 */
  953. status = vid_blk_write_word(dev, BAND_OUT_SEL,
  954. cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) |
  955. cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) |
  956. cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0));
  957. /* unmute all, AC97 in, independence mode
  958. adr 08d0, data 0x00063073 */
  959. status = vid_blk_write_word(dev, DL_CTL, 0x3000001);
  960. status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073);
  961. /* set AVC maximum threshold, adr 08d4, dat ffff0024 */
  962. status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval);
  963. status = vid_blk_write_word(dev, PATH1_VOL_CTL,
  964. (dwval | FLD_PATH1_AVC_THRESHOLD));
  965. /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */
  966. status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval);
  967. status = vid_blk_write_word(dev, PATH1_SC_CTL,
  968. (dwval | FLD_PATH1_SC_THRESHOLD));
  969. break;
  970. case AUDIO_INPUT_TUNER_TV:
  971. default:
  972. status = stopAudioFirmware(dev);
  973. /* Setup SRC sources and clocks */
  974. status = vid_blk_write_word(dev, BAND_OUT_SEL,
  975. cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) |
  976. cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) |
  977. cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) |
  978. cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) |
  979. cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) |
  980. cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) |
  981. cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) |
  982. cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) |
  983. cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) |
  984. cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) |
  985. cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) |
  986. cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) |
  987. cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01));
  988. /* Setup the AUD_IO control */
  989. status = vid_blk_write_word(dev, AUD_IO_CTRL,
  990. cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) |
  991. cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) |
  992. cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) |
  993. cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) |
  994. cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03));
  995. status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870);
  996. /* setAudioStandard(_audio_standard); */
  997. status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870);
  998. status = restartAudioFirmware(dev);
  999. switch (dev->board.tuner_type) {
  1000. case TUNER_XC5000:
  1001. /* SIF passthrough at 28.6363 MHz sample rate */
  1002. status = cx231xx_read_modify_write_i2c_dword(dev,
  1003. VID_BLK_I2C_ADDRESS,
  1004. CHIP_CTRL,
  1005. FLD_SIF_EN,
  1006. cx231xx_set_field(FLD_SIF_EN, 1));
  1007. break;
  1008. case TUNER_NXP_TDA18271:
  1009. /* Normal mode: SIF passthrough at 14.32 MHz */
  1010. status = cx231xx_read_modify_write_i2c_dword(dev,
  1011. VID_BLK_I2C_ADDRESS,
  1012. CHIP_CTRL,
  1013. FLD_SIF_EN,
  1014. cx231xx_set_field(FLD_SIF_EN, 0));
  1015. break;
  1016. default:
  1017. /* This is just a casual suggestion to people adding
  1018. new boards in case they use a tuner type we don't
  1019. currently know about */
  1020. printk(KERN_INFO "Unknown tuner type configuring SIF");
  1021. break;
  1022. }
  1023. break;
  1024. case AUDIO_INPUT_TUNER_FM:
  1025. /* use SIF for FM radio
  1026. setupFM();
  1027. setAudioStandard(_audio_standard);
  1028. */
  1029. break;
  1030. case AUDIO_INPUT_MUTE:
  1031. status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012);
  1032. break;
  1033. }
  1034. /* Take it out of soft reset */
  1035. status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
  1036. gen_ctrl &= ~1;
  1037. status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
  1038. return status;
  1039. }
  1040. /******************************************************************************
  1041. * C H I P Specific C O N T R O L functions *
  1042. ******************************************************************************/
  1043. int cx231xx_init_ctrl_pin_status(struct cx231xx *dev)
  1044. {
  1045. u32 value;
  1046. int status = 0;
  1047. status = vid_blk_read_word(dev, PIN_CTRL, &value);
  1048. value |= (~dev->board.ctl_pin_status_mask);
  1049. status = vid_blk_write_word(dev, PIN_CTRL, value);
  1050. return status;
  1051. }
  1052. int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
  1053. u8 analog_or_digital)
  1054. {
  1055. int status = 0;
  1056. /* first set the direction to output */
  1057. status = cx231xx_set_gpio_direction(dev,
  1058. dev->board.
  1059. agc_analog_digital_select_gpio, 1);
  1060. /* 0 - demod ; 1 - Analog mode */
  1061. status = cx231xx_set_gpio_value(dev,
  1062. dev->board.agc_analog_digital_select_gpio,
  1063. analog_or_digital);
  1064. return status;
  1065. }
  1066. int cx231xx_enable_i2c_port_3(struct cx231xx *dev, bool is_port_3)
  1067. {
  1068. u8 value[4] = { 0, 0, 0, 0 };
  1069. int status = 0;
  1070. bool current_is_port_3;
  1071. if (dev->board.dont_use_port_3)
  1072. is_port_3 = false;
  1073. status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
  1074. PWR_CTL_EN, value, 4);
  1075. if (status < 0)
  1076. return status;
  1077. current_is_port_3 = value[0] & I2C_DEMOD_EN ? true : false;
  1078. /* Just return, if already using the right port */
  1079. if (current_is_port_3 == is_port_3)
  1080. return 0;
  1081. if (is_port_3)
  1082. value[0] |= I2C_DEMOD_EN;
  1083. else
  1084. value[0] &= ~I2C_DEMOD_EN;
  1085. cx231xx_info("Changing the i2c master port to %d\n",
  1086. is_port_3 ? 3 : 1);
  1087. status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
  1088. PWR_CTL_EN, value, 4);
  1089. return status;
  1090. }
  1091. EXPORT_SYMBOL_GPL(cx231xx_enable_i2c_port_3);
  1092. void update_HH_register_after_set_DIF(struct cx231xx *dev)
  1093. {
  1094. /*
  1095. u8 status = 0;
  1096. u32 value = 0;
  1097. vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F);
  1098. vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11);
  1099. vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06);
  1100. status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
  1101. vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
  1102. status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
  1103. */
  1104. }
  1105. void cx231xx_dump_HH_reg(struct cx231xx *dev)
  1106. {
  1107. u8 status = 0;
  1108. u32 value = 0;
  1109. u16 i = 0;
  1110. value = 0x45005390;
  1111. status = vid_blk_write_word(dev, 0x104, value);
  1112. for (i = 0x100; i < 0x140; i++) {
  1113. status = vid_blk_read_word(dev, i, &value);
  1114. cx231xx_info("reg0x%x=0x%x\n", i, value);
  1115. i = i+3;
  1116. }
  1117. for (i = 0x300; i < 0x400; i++) {
  1118. status = vid_blk_read_word(dev, i, &value);
  1119. cx231xx_info("reg0x%x=0x%x\n", i, value);
  1120. i = i+3;
  1121. }
  1122. for (i = 0x400; i < 0x440; i++) {
  1123. status = vid_blk_read_word(dev, i, &value);
  1124. cx231xx_info("reg0x%x=0x%x\n", i, value);
  1125. i = i+3;
  1126. }
  1127. status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
  1128. cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
  1129. vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
  1130. status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
  1131. cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
  1132. }
  1133. void cx231xx_dump_SC_reg(struct cx231xx *dev)
  1134. {
  1135. u8 value[4] = { 0, 0, 0, 0 };
  1136. int status = 0;
  1137. cx231xx_info("cx231xx_dump_SC_reg!\n");
  1138. status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT,
  1139. value, 4);
  1140. cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0],
  1141. value[1], value[2], value[3]);
  1142. status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG,
  1143. value, 4);
  1144. cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0],
  1145. value[1], value[2], value[3]);
  1146. status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG,
  1147. value, 4);
  1148. cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0],
  1149. value[1], value[2], value[3]);
  1150. status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG,
  1151. value, 4);
  1152. cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0],
  1153. value[1], value[2], value[3]);
  1154. status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG,
  1155. value, 4);
  1156. cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0],
  1157. value[1], value[2], value[3]);
  1158. status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG,
  1159. value, 4);
  1160. cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0],
  1161. value[1], value[2], value[3]);
  1162. status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
  1163. value, 4);
  1164. cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0],
  1165. value[1], value[2], value[3]);
  1166. status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1,
  1167. value, 4);
  1168. cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0],
  1169. value[1], value[2], value[3]);
  1170. status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2,
  1171. value, 4);
  1172. cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0],
  1173. value[1], value[2], value[3]);
  1174. status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3,
  1175. value, 4);
  1176. cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0],
  1177. value[1], value[2], value[3]);
  1178. status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0,
  1179. value, 4);
  1180. cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0],
  1181. value[1], value[2], value[3]);
  1182. status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1,
  1183. value, 4);
  1184. cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0],
  1185. value[1], value[2], value[3]);
  1186. status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2,
  1187. value, 4);
  1188. cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0],
  1189. value[1], value[2], value[3]);
  1190. status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN,
  1191. value, 4);
  1192. cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0],
  1193. value[1], value[2], value[3]);
  1194. status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG,
  1195. value, 4);
  1196. cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0],
  1197. value[1], value[2], value[3]);
  1198. status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1,
  1199. value, 4);
  1200. cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0],
  1201. value[1], value[2], value[3]);
  1202. status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2,
  1203. value, 4);
  1204. cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0],
  1205. value[1], value[2], value[3]);
  1206. status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
  1207. value, 4);
  1208. cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0],
  1209. value[1], value[2], value[3]);
  1210. }
  1211. void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev)
  1212. {
  1213. u8 status = 0;
  1214. u8 value = 0;
  1215. status = afe_read_byte(dev, ADC_STATUS2_CH3, &value);
  1216. value = (value & 0xFE)|0x01;
  1217. status = afe_write_byte(dev, ADC_STATUS2_CH3, value);
  1218. status = afe_read_byte(dev, ADC_STATUS2_CH3, &value);
  1219. value = (value & 0xFE)|0x00;
  1220. status = afe_write_byte(dev, ADC_STATUS2_CH3, value);
  1221. /*
  1222. config colibri to lo-if mode
  1223. FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce
  1224. the diff IF input by half,
  1225. for low-if agc defect
  1226. */
  1227. status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value);
  1228. value = (value & 0xFC)|0x00;
  1229. status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value);
  1230. status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
  1231. value = (value & 0xF9)|0x02;
  1232. status = afe_write_byte(dev, ADC_INPUT_CH3, value);
  1233. status = afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value);
  1234. value = (value & 0xFB)|0x04;
  1235. status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, value);
  1236. status = afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value);
  1237. value = (value & 0xFC)|0x03;
  1238. status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value);
  1239. status = afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value);
  1240. value = (value & 0xFB)|0x04;
  1241. status = afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value);
  1242. status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
  1243. value = (value & 0xF8)|0x06;
  1244. status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
  1245. status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
  1246. value = (value & 0x8F)|0x40;
  1247. status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
  1248. status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value);
  1249. value = (value & 0xDF)|0x20;
  1250. status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value);
  1251. }
  1252. void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq,
  1253. u8 spectral_invert, u32 mode)
  1254. {
  1255. u32 colibri_carrier_offset = 0;
  1256. u8 status = 0;
  1257. u32 func_mode = 0x01; /* Device has a DIF if this function is called */
  1258. u32 standard = 0;
  1259. u8 value[4] = { 0, 0, 0, 0 };
  1260. cx231xx_info("Enter cx231xx_set_Colibri_For_LowIF()\n");
  1261. value[0] = (u8) 0x6F;
  1262. value[1] = (u8) 0x6F;
  1263. value[2] = (u8) 0x6F;
  1264. value[3] = (u8) 0x6F;
  1265. status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
  1266. PWR_CTL_EN, value, 4);
  1267. /*Set colibri for low IF*/
  1268. status = cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF);
  1269. /* Set C2HH for low IF operation.*/
  1270. standard = dev->norm;
  1271. status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
  1272. func_mode, standard);
  1273. /* Get colibri offsets.*/
  1274. colibri_carrier_offset = cx231xx_Get_Colibri_CarrierOffset(mode,
  1275. standard);
  1276. cx231xx_info("colibri_carrier_offset=%d, standard=0x%x\n",
  1277. colibri_carrier_offset, standard);
  1278. /* Set the band Pass filter for DIF*/
  1279. cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset),
  1280. spectral_invert, mode);
  1281. }
  1282. u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd)
  1283. {
  1284. u32 colibri_carrier_offset = 0;
  1285. if (mode == TUNER_MODE_FM_RADIO) {
  1286. colibri_carrier_offset = 1100000;
  1287. } else if (standerd & (V4L2_STD_MN | V4L2_STD_NTSC_M_JP)) {
  1288. colibri_carrier_offset = 4832000; /*4.83MHz */
  1289. } else if (standerd & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) {
  1290. colibri_carrier_offset = 2700000; /*2.70MHz */
  1291. } else if (standerd & (V4L2_STD_PAL_D | V4L2_STD_PAL_I
  1292. | V4L2_STD_SECAM)) {
  1293. colibri_carrier_offset = 2100000; /*2.10MHz */
  1294. }
  1295. return colibri_carrier_offset;
  1296. }
  1297. void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq,
  1298. u8 spectral_invert, u32 mode)
  1299. {
  1300. unsigned long pll_freq_word;
  1301. int status = 0;
  1302. u32 dif_misc_ctrl_value = 0;
  1303. u64 pll_freq_u64 = 0;
  1304. u32 i = 0;
  1305. cx231xx_info("if_freq=%d;spectral_invert=0x%x;mode=0x%x\n",
  1306. if_freq, spectral_invert, mode);
  1307. if (mode == TUNER_MODE_FM_RADIO) {
  1308. pll_freq_word = 0x905A1CAC;
  1309. status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
  1310. } else /*KSPROPERTY_TUNER_MODE_TV*/{
  1311. /* Calculate the PLL frequency word based on the adjusted if_freq*/
  1312. pll_freq_word = if_freq;
  1313. pll_freq_u64 = (u64)pll_freq_word << 28L;
  1314. do_div(pll_freq_u64, 50000000);
  1315. pll_freq_word = (u32)pll_freq_u64;
  1316. /*pll_freq_word = 0x3463497;*/
  1317. status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
  1318. if (spectral_invert) {
  1319. if_freq -= 400000;
  1320. /* Enable Spectral Invert*/
  1321. status = vid_blk_read_word(dev, DIF_MISC_CTRL,
  1322. &dif_misc_ctrl_value);
  1323. dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000;
  1324. status = vid_blk_write_word(dev, DIF_MISC_CTRL,
  1325. dif_misc_ctrl_value);
  1326. } else {
  1327. if_freq += 400000;
  1328. /* Disable Spectral Invert*/
  1329. status = vid_blk_read_word(dev, DIF_MISC_CTRL,
  1330. &dif_misc_ctrl_value);
  1331. dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF;
  1332. status = vid_blk_write_word(dev, DIF_MISC_CTRL,
  1333. dif_misc_ctrl_value);
  1334. }
  1335. if_freq = (if_freq/100000)*100000;
  1336. if (if_freq < 3000000)
  1337. if_freq = 3000000;
  1338. if (if_freq > 16000000)
  1339. if_freq = 16000000;
  1340. }
  1341. cx231xx_info("Enter IF=%zd\n",
  1342. sizeof(Dif_set_array)/sizeof(struct dif_settings));
  1343. for (i = 0; i < sizeof(Dif_set_array)/sizeof(struct dif_settings); i++) {
  1344. if (Dif_set_array[i].if_freq == if_freq) {
  1345. status = vid_blk_write_word(dev,
  1346. Dif_set_array[i].register_address, Dif_set_array[i].value);
  1347. }
  1348. }
  1349. }
  1350. /******************************************************************************
  1351. * D I F - B L O C K C O N T R O L functions *
  1352. ******************************************************************************/
  1353. int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
  1354. u32 function_mode, u32 standard)
  1355. {
  1356. int status = 0;
  1357. if (mode == V4L2_TUNER_RADIO) {
  1358. /* C2HH */
  1359. /* lo if big signal */
  1360. status = cx231xx_reg_mask_write(dev,
  1361. VID_BLK_I2C_ADDRESS, 32,
  1362. AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
  1363. /* FUNC_MODE = DIF */
  1364. status = cx231xx_reg_mask_write(dev,
  1365. VID_BLK_I2C_ADDRESS, 32,
  1366. AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode);
  1367. /* IF_MODE */
  1368. status = cx231xx_reg_mask_write(dev,
  1369. VID_BLK_I2C_ADDRESS, 32,
  1370. AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF);
  1371. /* no inv */
  1372. status = cx231xx_reg_mask_write(dev,
  1373. VID_BLK_I2C_ADDRESS, 32,
  1374. AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
  1375. } else if (standard != DIF_USE_BASEBAND) {
  1376. if (standard & V4L2_STD_MN) {
  1377. /* lo if big signal */
  1378. status = cx231xx_reg_mask_write(dev,
  1379. VID_BLK_I2C_ADDRESS, 32,
  1380. AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
  1381. /* FUNC_MODE = DIF */
  1382. status = cx231xx_reg_mask_write(dev,
  1383. VID_BLK_I2C_ADDRESS, 32,
  1384. AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
  1385. function_mode);
  1386. /* IF_MODE */
  1387. status = cx231xx_reg_mask_write(dev,
  1388. VID_BLK_I2C_ADDRESS, 32,
  1389. AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb);
  1390. /* no inv */
  1391. status = cx231xx_reg_mask_write(dev,
  1392. VID_BLK_I2C_ADDRESS, 32,
  1393. AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
  1394. /* 0x124, AUD_CHAN1_SRC = 0x3 */
  1395. status = cx231xx_reg_mask_write(dev,
  1396. VID_BLK_I2C_ADDRESS, 32,
  1397. AUD_IO_CTRL, 0, 31, 0x00000003);
  1398. } else if ((standard == V4L2_STD_PAL_I) |
  1399. (standard & V4L2_STD_PAL_D) |
  1400. (standard & V4L2_STD_SECAM)) {
  1401. /* C2HH setup */
  1402. /* lo if big signal */
  1403. status = cx231xx_reg_mask_write(dev,
  1404. VID_BLK_I2C_ADDRESS, 32,
  1405. AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
  1406. /* FUNC_MODE = DIF */
  1407. status = cx231xx_reg_mask_write(dev,
  1408. VID_BLK_I2C_ADDRESS, 32,
  1409. AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
  1410. function_mode);
  1411. /* IF_MODE */
  1412. status = cx231xx_reg_mask_write(dev,
  1413. VID_BLK_I2C_ADDRESS, 32,
  1414. AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF);
  1415. /* no inv */
  1416. status = cx231xx_reg_mask_write(dev,
  1417. VID_BLK_I2C_ADDRESS, 32,
  1418. AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
  1419. } else {
  1420. /* default PAL BG */
  1421. /* C2HH setup */
  1422. /* lo if big signal */
  1423. status = cx231xx_reg_mask_write(dev,
  1424. VID_BLK_I2C_ADDRESS, 32,
  1425. AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
  1426. /* FUNC_MODE = DIF */
  1427. status = cx231xx_reg_mask_write(dev,
  1428. VID_BLK_I2C_ADDRESS, 32,
  1429. AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
  1430. function_mode);
  1431. /* IF_MODE */
  1432. status = cx231xx_reg_mask_write(dev,
  1433. VID_BLK_I2C_ADDRESS, 32,
  1434. AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE);
  1435. /* no inv */
  1436. status = cx231xx_reg_mask_write(dev,
  1437. VID_BLK_I2C_ADDRESS, 32,
  1438. AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
  1439. }
  1440. }
  1441. return status;
  1442. }
  1443. int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
  1444. {
  1445. int status = 0;
  1446. u32 dif_misc_ctrl_value = 0;
  1447. u32 func_mode = 0;
  1448. cx231xx_info("%s: setStandard to %x\n", __func__, standard);
  1449. status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value);
  1450. if (standard != DIF_USE_BASEBAND)
  1451. dev->norm = standard;
  1452. switch (dev->model) {
  1453. case CX231XX_BOARD_CNXT_CARRAERA:
  1454. case CX231XX_BOARD_CNXT_RDE_250:
  1455. case CX231XX_BOARD_CNXT_SHELBY:
  1456. case CX231XX_BOARD_CNXT_RDU_250:
  1457. case CX231XX_BOARD_CNXT_VIDEO_GRABBER: