/drivers/media/video/cx231xx/cx231xx-avcore.c
C | 3119 lines | 2267 code | 459 blank | 393 comment | 238 complexity | 22a07687d37e45e6dbe4313587beed1e MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
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1/* 2 cx231xx_avcore.c - driver for Conexant Cx23100/101/102 3 USB video capture devices 4 5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com> 6 7 This program contains the specific code to control the avdecoder chip and 8 other related usb control functions for cx231xx based chipset. 9 10 This program is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 2 of the License, or 13 (at your option) any later version. 14 15 This program is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with this program; if not, write to the Free Software 22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24 25#include <linux/init.h> 26#include <linux/list.h> 27#include <linux/module.h> 28#include <linux/kernel.h> 29#include <linux/bitmap.h> 30#include <linux/usb.h> 31#include <linux/i2c.h> 32#include <linux/mm.h> 33#include <linux/mutex.h> 34#include <media/tuner.h> 35 36#include <media/v4l2-common.h> 37#include <media/v4l2-ioctl.h> 38#include <media/v4l2-chip-ident.h> 39 40#include "cx231xx.h" 41#include "cx231xx-dif.h" 42 43#define TUNER_MODE_FM_RADIO 0 44/****************************************************************************** 45 -: BLOCK ARRANGEMENT :- 46 I2S block ----------------------| 47 [I2S audio] | 48 | 49 Analog Front End --> Direct IF -|-> Cx25840 --> Audio 50 [video & audio] | [Audio] 51 | 52 |-> Cx25840 --> Video 53 [Video] 54 55*******************************************************************************/ 56/****************************************************************************** 57 * VERVE REGISTER * 58 * * 59 ******************************************************************************/ 60static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data) 61{ 62 return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS, 63 saddr, 1, data, 1); 64} 65 66static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data) 67{ 68 int status; 69 u32 temp = 0; 70 71 status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS, 72 saddr, 1, &temp, 1); 73 *data = (u8) temp; 74 return status; 75} 76void initGPIO(struct cx231xx *dev) 77{ 78 u32 _gpio_direction = 0; 79 u32 value = 0; 80 u8 val = 0; 81 82 _gpio_direction = _gpio_direction & 0xFC0003FF; 83 _gpio_direction = _gpio_direction | 0x03FDFC00; 84 cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0); 85 86 verve_read_byte(dev, 0x07, &val); 87 cx231xx_info(" verve_read_byte address0x07=0x%x\n", val); 88 verve_write_byte(dev, 0x07, 0xF4); 89 verve_read_byte(dev, 0x07, &val); 90 cx231xx_info(" verve_read_byte address0x07=0x%x\n", val); 91 92 cx231xx_capture_start(dev, 1, 2); 93 94 cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00); 95 cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF); 96 97} 98void uninitGPIO(struct cx231xx *dev) 99{ 100 u8 value[4] = { 0, 0, 0, 0 }; 101 102 cx231xx_capture_start(dev, 0, 2); 103 verve_write_byte(dev, 0x07, 0x14); 104 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 105 0x68, value, 4); 106} 107 108/****************************************************************************** 109 * A F E - B L O C K C O N T R O L functions * 110 * [ANALOG FRONT END] * 111 ******************************************************************************/ 112static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data) 113{ 114 return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS, 115 saddr, 2, data, 1); 116} 117 118static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data) 119{ 120 int status; 121 u32 temp = 0; 122 123 status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS, 124 saddr, 2, &temp, 1); 125 *data = (u8) temp; 126 return status; 127} 128 129int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count) 130{ 131 int status = 0; 132 u8 temp = 0; 133 u8 afe_power_status = 0; 134 int i = 0; 135 136 /* super block initialize */ 137 temp = (u8) (ref_count & 0xff); 138 status = afe_write_byte(dev, SUP_BLK_TUNE2, temp); 139 if (status < 0) 140 return status; 141 142 status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status); 143 if (status < 0) 144 return status; 145 146 temp = (u8) ((ref_count & 0x300) >> 8); 147 temp |= 0x40; 148 status = afe_write_byte(dev, SUP_BLK_TUNE1, temp); 149 if (status < 0) 150 return status; 151 152 status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f); 153 if (status < 0) 154 return status; 155 156 /* enable pll */ 157 while (afe_power_status != 0x18) { 158 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18); 159 if (status < 0) { 160 cx231xx_info( 161 ": Init Super Block failed in send cmd\n"); 162 break; 163 } 164 165 status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status); 166 afe_power_status &= 0xff; 167 if (status < 0) { 168 cx231xx_info( 169 ": Init Super Block failed in receive cmd\n"); 170 break; 171 } 172 i++; 173 if (i == 10) { 174 cx231xx_info( 175 ": Init Super Block force break in loop !!!!\n"); 176 status = -1; 177 break; 178 } 179 } 180 181 if (status < 0) 182 return status; 183 184 /* start tuning filter */ 185 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40); 186 if (status < 0) 187 return status; 188 189 msleep(5); 190 191 /* exit tuning */ 192 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00); 193 194 return status; 195} 196 197int cx231xx_afe_init_channels(struct cx231xx *dev) 198{ 199 int status = 0; 200 201 /* power up all 3 channels, clear pd_buffer */ 202 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00); 203 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00); 204 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00); 205 206 /* Enable quantizer calibration */ 207 status = afe_write_byte(dev, ADC_COM_QUANT, 0x02); 208 209 /* channel initialize, force modulator (fb) reset */ 210 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17); 211 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17); 212 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17); 213 214 /* start quantilizer calibration */ 215 status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10); 216 status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10); 217 status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10); 218 msleep(5); 219 220 /* exit modulator (fb) reset */ 221 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07); 222 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07); 223 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07); 224 225 /* enable the pre_clamp in each channel for single-ended input */ 226 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0); 227 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0); 228 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0); 229 230 /* use diode instead of resistor, so set term_en to 0, res_en to 0 */ 231 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 232 ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00); 233 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 234 ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00); 235 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 236 ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00); 237 238 /* dynamic element matching off */ 239 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03); 240 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03); 241 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03); 242 243 return status; 244} 245 246int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev) 247{ 248 u8 c_value = 0; 249 int status = 0; 250 251 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value); 252 c_value &= (~(0x50)); 253 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value); 254 255 return status; 256} 257 258/* 259 The Analog Front End in Cx231xx has 3 channels. These 260 channels are used to share between different inputs 261 like tuner, s-video and composite inputs. 262 263 channel 1 ----- pin 1 to pin4(in reg is 1-4) 264 channel 2 ----- pin 5 to pin8(in reg is 5-8) 265 channel 3 ----- pin 9 to pin 12(in reg is 9-11) 266*/ 267int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux) 268{ 269 u8 ch1_setting = (u8) input_mux; 270 u8 ch2_setting = (u8) (input_mux >> 8); 271 u8 ch3_setting = (u8) (input_mux >> 16); 272 int status = 0; 273 u8 value = 0; 274 275 if (ch1_setting != 0) { 276 status = afe_read_byte(dev, ADC_INPUT_CH1, &value); 277 value &= ~INPUT_SEL_MASK; 278 value |= (ch1_setting - 1) << 4; 279 value &= 0xff; 280 status = afe_write_byte(dev, ADC_INPUT_CH1, value); 281 } 282 283 if (ch2_setting != 0) { 284 status = afe_read_byte(dev, ADC_INPUT_CH2, &value); 285 value &= ~INPUT_SEL_MASK; 286 value |= (ch2_setting - 1) << 4; 287 value &= 0xff; 288 status = afe_write_byte(dev, ADC_INPUT_CH2, value); 289 } 290 291 /* For ch3_setting, the value to put in the register is 292 7 less than the input number */ 293 if (ch3_setting != 0) { 294 status = afe_read_byte(dev, ADC_INPUT_CH3, &value); 295 value &= ~INPUT_SEL_MASK; 296 value |= (ch3_setting - 1) << 4; 297 value &= 0xff; 298 status = afe_write_byte(dev, ADC_INPUT_CH3, value); 299 } 300 301 return status; 302} 303 304int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode) 305{ 306 int status = 0; 307 308 /* 309 * FIXME: We need to implement the AFE code for LOW IF and for HI IF. 310 * Currently, only baseband works. 311 */ 312 313 switch (mode) { 314 case AFE_MODE_LOW_IF: 315 cx231xx_Setup_AFE_for_LowIF(dev); 316 break; 317 case AFE_MODE_BASEBAND: 318 status = cx231xx_afe_setup_AFE_for_baseband(dev); 319 break; 320 case AFE_MODE_EU_HI_IF: 321 /* SetupAFEforEuHiIF(); */ 322 break; 323 case AFE_MODE_US_HI_IF: 324 /* SetupAFEforUsHiIF(); */ 325 break; 326 case AFE_MODE_JAPAN_HI_IF: 327 /* SetupAFEforJapanHiIF(); */ 328 break; 329 } 330 331 if ((mode != dev->afe_mode) && 332 (dev->video_input == CX231XX_VMUX_TELEVISION)) 333 status = cx231xx_afe_adjust_ref_count(dev, 334 CX231XX_VMUX_TELEVISION); 335 336 dev->afe_mode = mode; 337 338 return status; 339} 340 341int cx231xx_afe_update_power_control(struct cx231xx *dev, 342 enum AV_MODE avmode) 343{ 344 u8 afe_power_status = 0; 345 int status = 0; 346 347 switch (dev->model) { 348 case CX231XX_BOARD_CNXT_CARRAERA: 349 case CX231XX_BOARD_CNXT_RDE_250: 350 case CX231XX_BOARD_CNXT_SHELBY: 351 case CX231XX_BOARD_CNXT_RDU_250: 352 case CX231XX_BOARD_CNXT_RDE_253S: 353 case CX231XX_BOARD_CNXT_RDU_253S: 354 case CX231XX_BOARD_CNXT_VIDEO_GRABBER: 355 case CX231XX_BOARD_HAUPPAUGE_EXETER: 356 case CX231XX_BOARD_HAUPPAUGE_USBLIVE2: 357 case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID: 358 if (avmode == POLARIS_AVMODE_ANALOGT_TV) { 359 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 360 FLD_PWRDN_ENABLE_PLL)) { 361 status = afe_write_byte(dev, SUP_BLK_PWRDN, 362 FLD_PWRDN_TUNING_BIAS | 363 FLD_PWRDN_ENABLE_PLL); 364 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 365 &afe_power_status); 366 if (status < 0) 367 break; 368 } 369 370 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 371 0x00); 372 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 373 0x00); 374 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 375 0x00); 376 } else if (avmode == POLARIS_AVMODE_DIGITAL) { 377 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 378 0x70); 379 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 380 0x70); 381 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 382 0x70); 383 384 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 385 &afe_power_status); 386 afe_power_status |= FLD_PWRDN_PD_BANDGAP | 387 FLD_PWRDN_PD_BIAS | 388 FLD_PWRDN_PD_TUNECK; 389 status |= afe_write_byte(dev, SUP_BLK_PWRDN, 390 afe_power_status); 391 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { 392 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 393 FLD_PWRDN_ENABLE_PLL)) { 394 status = afe_write_byte(dev, SUP_BLK_PWRDN, 395 FLD_PWRDN_TUNING_BIAS | 396 FLD_PWRDN_ENABLE_PLL); 397 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 398 &afe_power_status); 399 if (status < 0) 400 break; 401 } 402 403 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 404 0x00); 405 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 406 0x00); 407 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 408 0x00); 409 } else { 410 cx231xx_info("Invalid AV mode input\n"); 411 status = -1; 412 } 413 break; 414 default: 415 if (avmode == POLARIS_AVMODE_ANALOGT_TV) { 416 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 417 FLD_PWRDN_ENABLE_PLL)) { 418 status = afe_write_byte(dev, SUP_BLK_PWRDN, 419 FLD_PWRDN_TUNING_BIAS | 420 FLD_PWRDN_ENABLE_PLL); 421 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 422 &afe_power_status); 423 if (status < 0) 424 break; 425 } 426 427 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 428 0x40); 429 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 430 0x40); 431 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 432 0x00); 433 } else if (avmode == POLARIS_AVMODE_DIGITAL) { 434 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 435 0x70); 436 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 437 0x70); 438 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 439 0x70); 440 441 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 442 &afe_power_status); 443 afe_power_status |= FLD_PWRDN_PD_BANDGAP | 444 FLD_PWRDN_PD_BIAS | 445 FLD_PWRDN_PD_TUNECK; 446 status |= afe_write_byte(dev, SUP_BLK_PWRDN, 447 afe_power_status); 448 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { 449 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 450 FLD_PWRDN_ENABLE_PLL)) { 451 status = afe_write_byte(dev, SUP_BLK_PWRDN, 452 FLD_PWRDN_TUNING_BIAS | 453 FLD_PWRDN_ENABLE_PLL); 454 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 455 &afe_power_status); 456 if (status < 0) 457 break; 458 } 459 460 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 461 0x00); 462 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 463 0x00); 464 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 465 0x40); 466 } else { 467 cx231xx_info("Invalid AV mode input\n"); 468 status = -1; 469 } 470 } /* switch */ 471 472 return status; 473} 474 475int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input) 476{ 477 u8 input_mode = 0; 478 u8 ntf_mode = 0; 479 int status = 0; 480 481 dev->video_input = video_input; 482 483 if (video_input == CX231XX_VMUX_TELEVISION) { 484 status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode); 485 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 486 &ntf_mode); 487 } else { 488 status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode); 489 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 490 &ntf_mode); 491 } 492 493 input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1); 494 495 switch (input_mode) { 496 case SINGLE_ENDED: 497 dev->afe_ref_count = 0x23C; 498 break; 499 case LOW_IF: 500 dev->afe_ref_count = 0x24C; 501 break; 502 case EU_IF: 503 dev->afe_ref_count = 0x258; 504 break; 505 case US_IF: 506 dev->afe_ref_count = 0x260; 507 break; 508 default: 509 break; 510 } 511 512 status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count); 513 514 return status; 515} 516 517/****************************************************************************** 518 * V I D E O / A U D I O D E C O D E R C O N T R O L functions * 519 ******************************************************************************/ 520static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data) 521{ 522 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS, 523 saddr, 2, data, 1); 524} 525 526static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data) 527{ 528 int status; 529 u32 temp = 0; 530 531 status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS, 532 saddr, 2, &temp, 1); 533 *data = (u8) temp; 534 return status; 535} 536 537static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data) 538{ 539 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS, 540 saddr, 2, data, 4); 541} 542 543static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data) 544{ 545 return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS, 546 saddr, 2, data, 4); 547} 548int cx231xx_check_fw(struct cx231xx *dev) 549{ 550 u8 temp = 0; 551 int status = 0; 552 status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp); 553 if (status < 0) 554 return status; 555 else 556 return temp; 557 558} 559 560int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input) 561{ 562 int status = 0; 563 564 switch (INPUT(input)->type) { 565 case CX231XX_VMUX_COMPOSITE1: 566 case CX231XX_VMUX_SVIDEO: 567 if ((dev->current_pcb_config.type == USB_BUS_POWER) && 568 (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) { 569 /* External AV */ 570 status = cx231xx_set_power_mode(dev, 571 POLARIS_AVMODE_ENXTERNAL_AV); 572 if (status < 0) { 573 cx231xx_errdev("%s: set_power_mode : Failed to" 574 " set Power - errCode [%d]!\n", 575 __func__, status); 576 return status; 577 } 578 } 579 status = cx231xx_set_decoder_video_input(dev, 580 INPUT(input)->type, 581 INPUT(input)->vmux); 582 break; 583 case CX231XX_VMUX_TELEVISION: 584 case CX231XX_VMUX_CABLE: 585 if ((dev->current_pcb_config.type == USB_BUS_POWER) && 586 (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) { 587 /* Tuner */ 588 status = cx231xx_set_power_mode(dev, 589 POLARIS_AVMODE_ANALOGT_TV); 590 if (status < 0) { 591 cx231xx_errdev("%s: set_power_mode:Failed" 592 " to set Power - errCode [%d]!\n", 593 __func__, status); 594 return status; 595 } 596 } 597 if (dev->tuner_type == TUNER_NXP_TDA18271) 598 status = cx231xx_set_decoder_video_input(dev, 599 CX231XX_VMUX_TELEVISION, 600 INPUT(input)->vmux); 601 else 602 status = cx231xx_set_decoder_video_input(dev, 603 CX231XX_VMUX_COMPOSITE1, 604 INPUT(input)->vmux); 605 606 break; 607 default: 608 cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n", 609 __func__, INPUT(input)->type); 610 break; 611 } 612 613 /* save the selection */ 614 dev->video_input = input; 615 616 return status; 617} 618 619int cx231xx_set_decoder_video_input(struct cx231xx *dev, 620 u8 pin_type, u8 input) 621{ 622 int status = 0; 623 u32 value = 0; 624 625 if (pin_type != dev->video_input) { 626 status = cx231xx_afe_adjust_ref_count(dev, pin_type); 627 if (status < 0) { 628 cx231xx_errdev("%s: adjust_ref_count :Failed to set" 629 "AFE input mux - errCode [%d]!\n", 630 __func__, status); 631 return status; 632 } 633 } 634 635 /* call afe block to set video inputs */ 636 status = cx231xx_afe_set_input_mux(dev, input); 637 if (status < 0) { 638 cx231xx_errdev("%s: set_input_mux :Failed to set" 639 " AFE input mux - errCode [%d]!\n", 640 __func__, status); 641 return status; 642 } 643 644 switch (pin_type) { 645 case CX231XX_VMUX_COMPOSITE1: 646 status = vid_blk_read_word(dev, AFE_CTRL, &value); 647 value |= (0 << 13) | (1 << 4); 648 value &= ~(1 << 5); 649 650 /* set [24:23] [22:15] to 0 */ 651 value &= (~(0x1ff8000)); 652 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ 653 value |= 0x1000000; 654 status = vid_blk_write_word(dev, AFE_CTRL, value); 655 656 status = vid_blk_read_word(dev, OUT_CTRL1, &value); 657 value |= (1 << 7); 658 status = vid_blk_write_word(dev, OUT_CTRL1, value); 659 660 /* Set output mode */ 661 status = cx231xx_read_modify_write_i2c_dword(dev, 662 VID_BLK_I2C_ADDRESS, 663 OUT_CTRL1, 664 FLD_OUT_MODE, 665 dev->board.output_mode); 666 667 /* Tell DIF object to go to baseband mode */ 668 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); 669 if (status < 0) { 670 cx231xx_errdev("%s: cx231xx_dif set to By pass" 671 " mode- errCode [%d]!\n", 672 __func__, status); 673 return status; 674 } 675 676 /* Read the DFE_CTRL1 register */ 677 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 678 679 /* enable the VBI_GATE_EN */ 680 value |= FLD_VBI_GATE_EN; 681 682 /* Enable the auto-VGA enable */ 683 value |= FLD_VGA_AUTO_EN; 684 685 /* Write it back */ 686 status = vid_blk_write_word(dev, DFE_CTRL1, value); 687 688 /* Disable auto config of registers */ 689 status = cx231xx_read_modify_write_i2c_dword(dev, 690 VID_BLK_I2C_ADDRESS, 691 MODE_CTRL, FLD_ACFG_DIS, 692 cx231xx_set_field(FLD_ACFG_DIS, 1)); 693 694 /* Set CVBS input mode */ 695 status = cx231xx_read_modify_write_i2c_dword(dev, 696 VID_BLK_I2C_ADDRESS, 697 MODE_CTRL, FLD_INPUT_MODE, 698 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0)); 699 break; 700 case CX231XX_VMUX_SVIDEO: 701 /* Disable the use of DIF */ 702 703 status = vid_blk_read_word(dev, AFE_CTRL, &value); 704 705 /* set [24:23] [22:15] to 0 */ 706 value &= (~(0x1ff8000)); 707 /* set FUNC_MODE[24:23] = 2 708 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */ 709 value |= 0x1000010; 710 status = vid_blk_write_word(dev, AFE_CTRL, value); 711 712 /* Tell DIF object to go to baseband mode */ 713 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); 714 if (status < 0) { 715 cx231xx_errdev("%s: cx231xx_dif set to By pass" 716 " mode- errCode [%d]!\n", 717 __func__, status); 718 return status; 719 } 720 721 /* Read the DFE_CTRL1 register */ 722 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 723 724 /* enable the VBI_GATE_EN */ 725 value |= FLD_VBI_GATE_EN; 726 727 /* Enable the auto-VGA enable */ 728 value |= FLD_VGA_AUTO_EN; 729 730 /* Write it back */ 731 status = vid_blk_write_word(dev, DFE_CTRL1, value); 732 733 /* Disable auto config of registers */ 734 status = cx231xx_read_modify_write_i2c_dword(dev, 735 VID_BLK_I2C_ADDRESS, 736 MODE_CTRL, FLD_ACFG_DIS, 737 cx231xx_set_field(FLD_ACFG_DIS, 1)); 738 739 /* Set YC input mode */ 740 status = cx231xx_read_modify_write_i2c_dword(dev, 741 VID_BLK_I2C_ADDRESS, 742 MODE_CTRL, 743 FLD_INPUT_MODE, 744 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1)); 745 746 /* Chroma to ADC2 */ 747 status = vid_blk_read_word(dev, AFE_CTRL, &value); 748 value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */ 749 750 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8) 751 This sets them to use video 752 rather than audio. Only one of the two will be in use. */ 753 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3); 754 755 status = vid_blk_write_word(dev, AFE_CTRL, value); 756 757 status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND); 758 break; 759 case CX231XX_VMUX_TELEVISION: 760 case CX231XX_VMUX_CABLE: 761 default: 762 /* TODO: Test if this is also needed for xc2028/xc3028 */ 763 if (dev->board.tuner_type == TUNER_XC5000) { 764 /* Disable the use of DIF */ 765 766 status = vid_blk_read_word(dev, AFE_CTRL, &value); 767 value |= (0 << 13) | (1 << 4); 768 value &= ~(1 << 5); 769 770 /* set [24:23] [22:15] to 0 */ 771 value &= (~(0x1FF8000)); 772 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ 773 value |= 0x1000000; 774 status = vid_blk_write_word(dev, AFE_CTRL, value); 775 776 status = vid_blk_read_word(dev, OUT_CTRL1, &value); 777 value |= (1 << 7); 778 status = vid_blk_write_word(dev, OUT_CTRL1, value); 779 780 /* Set output mode */ 781 status = cx231xx_read_modify_write_i2c_dword(dev, 782 VID_BLK_I2C_ADDRESS, 783 OUT_CTRL1, FLD_OUT_MODE, 784 dev->board.output_mode); 785 786 /* Tell DIF object to go to baseband mode */ 787 status = cx231xx_dif_set_standard(dev, 788 DIF_USE_BASEBAND); 789 if (status < 0) { 790 cx231xx_errdev("%s: cx231xx_dif set to By pass" 791 " mode- errCode [%d]!\n", 792 __func__, status); 793 return status; 794 } 795 796 /* Read the DFE_CTRL1 register */ 797 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 798 799 /* enable the VBI_GATE_EN */ 800 value |= FLD_VBI_GATE_EN; 801 802 /* Enable the auto-VGA enable */ 803 value |= FLD_VGA_AUTO_EN; 804 805 /* Write it back */ 806 status = vid_blk_write_word(dev, DFE_CTRL1, value); 807 808 /* Disable auto config of registers */ 809 status = cx231xx_read_modify_write_i2c_dword(dev, 810 VID_BLK_I2C_ADDRESS, 811 MODE_CTRL, FLD_ACFG_DIS, 812 cx231xx_set_field(FLD_ACFG_DIS, 1)); 813 814 /* Set CVBS input mode */ 815 status = cx231xx_read_modify_write_i2c_dword(dev, 816 VID_BLK_I2C_ADDRESS, 817 MODE_CTRL, FLD_INPUT_MODE, 818 cx231xx_set_field(FLD_INPUT_MODE, 819 INPUT_MODE_CVBS_0)); 820 } else { 821 /* Enable the DIF for the tuner */ 822 823 /* Reinitialize the DIF */ 824 status = cx231xx_dif_set_standard(dev, dev->norm); 825 if (status < 0) { 826 cx231xx_errdev("%s: cx231xx_dif set to By pass" 827 " mode- errCode [%d]!\n", 828 __func__, status); 829 return status; 830 } 831 832 /* Make sure bypass is cleared */ 833 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value); 834 835 /* Clear the bypass bit */ 836 value &= ~FLD_DIF_DIF_BYPASS; 837 838 /* Enable the use of the DIF block */ 839 status = vid_blk_write_word(dev, DIF_MISC_CTRL, value); 840 841 /* Read the DFE_CTRL1 register */ 842 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 843 844 /* Disable the VBI_GATE_EN */ 845 value &= ~FLD_VBI_GATE_EN; 846 847 /* Enable the auto-VGA enable, AGC, and 848 set the skip count to 2 */ 849 value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000; 850 851 /* Write it back */ 852 status = vid_blk_write_word(dev, DFE_CTRL1, value); 853 854 /* Wait until AGC locks up */ 855 msleep(1); 856 857 /* Disable the auto-VGA enable AGC */ 858 value &= ~(FLD_VGA_AUTO_EN); 859 860 /* Write it back */ 861 status = vid_blk_write_word(dev, DFE_CTRL1, value); 862 863 /* Enable Polaris B0 AGC output */ 864 status = vid_blk_read_word(dev, PIN_CTRL, &value); 865 value |= (FLD_OEF_AGC_RF) | 866 (FLD_OEF_AGC_IFVGA) | 867 (FLD_OEF_AGC_IF); 868 status = vid_blk_write_word(dev, PIN_CTRL, value); 869 870 /* Set output mode */ 871 status = cx231xx_read_modify_write_i2c_dword(dev, 872 VID_BLK_I2C_ADDRESS, 873 OUT_CTRL1, FLD_OUT_MODE, 874 dev->board.output_mode); 875 876 /* Disable auto config of registers */ 877 status = cx231xx_read_modify_write_i2c_dword(dev, 878 VID_BLK_I2C_ADDRESS, 879 MODE_CTRL, FLD_ACFG_DIS, 880 cx231xx_set_field(FLD_ACFG_DIS, 1)); 881 882 /* Set CVBS input mode */ 883 status = cx231xx_read_modify_write_i2c_dword(dev, 884 VID_BLK_I2C_ADDRESS, 885 MODE_CTRL, FLD_INPUT_MODE, 886 cx231xx_set_field(FLD_INPUT_MODE, 887 INPUT_MODE_CVBS_0)); 888 889 /* Set some bits in AFE_CTRL so that channel 2 or 3 890 * is ready to receive audio */ 891 /* Clear clamp for channels 2 and 3 (bit 16-17) */ 892 /* Clear droop comp (bit 19-20) */ 893 /* Set VGA_SEL (for audio control) (bit 7-8) */ 894 status = vid_blk_read_word(dev, AFE_CTRL, &value); 895 896 /*Set Func mode:01-DIF 10-baseband 11-YUV*/ 897 value &= (~(FLD_FUNC_MODE)); 898 value |= 0x800000; 899 900 value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2; 901 902 status = vid_blk_write_word(dev, AFE_CTRL, value); 903 904 if (dev->tuner_type == TUNER_NXP_TDA18271) { 905 status = vid_blk_read_word(dev, PIN_CTRL, 906 &value); 907 status = vid_blk_write_word(dev, PIN_CTRL, 908 (value & 0xFFFFFFEF)); 909 } 910 911 break; 912 913 } 914 break; 915 } 916 917 /* Set raw VBI mode */ 918 status = cx231xx_read_modify_write_i2c_dword(dev, 919 VID_BLK_I2C_ADDRESS, 920 OUT_CTRL1, FLD_VBIHACTRAW_EN, 921 cx231xx_set_field(FLD_VBIHACTRAW_EN, 1)); 922 923 status = vid_blk_read_word(dev, OUT_CTRL1, &value); 924 if (value & 0x02) { 925 value |= (1 << 19); 926 status = vid_blk_write_word(dev, OUT_CTRL1, value); 927 } 928 929 return status; 930} 931 932void cx231xx_enable656(struct cx231xx *dev) 933{ 934 u8 temp = 0; 935 int status; 936 /*enable TS1 data[0:7] as output to export 656*/ 937 938 status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF); 939 940 /*enable TS1 clock as output to export 656*/ 941 942 status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp); 943 temp = temp|0x04; 944 945 status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp); 946 947} 948EXPORT_SYMBOL_GPL(cx231xx_enable656); 949 950void cx231xx_disable656(struct cx231xx *dev) 951{ 952 u8 temp = 0; 953 int status; 954 955 956 status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00); 957 958 status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp); 959 temp = temp&0xFB; 960 961 status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp); 962} 963EXPORT_SYMBOL_GPL(cx231xx_disable656); 964 965/* 966 * Handle any video-mode specific overrides that are different 967 * on a per video standards basis after touching the MODE_CTRL 968 * register which resets many values for autodetect 969 */ 970int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev) 971{ 972 int status = 0; 973 974 cx231xx_info("do_mode_ctrl_overrides : 0x%x\n", 975 (unsigned int)dev->norm); 976 977 /* Change the DFE_CTRL3 bp_percent to fix flagging */ 978 status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280); 979 980 if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) { 981 cx231xx_info("do_mode_ctrl_overrides NTSC\n"); 982 983 /* Move the close caption lines out of active video, 984 adjust the active video start point */ 985 status = cx231xx_read_modify_write_i2c_dword(dev, 986 VID_BLK_I2C_ADDRESS, 987 VERT_TIM_CTRL, 988 FLD_VBLANK_CNT, 0x18); 989 status = cx231xx_read_modify_write_i2c_dword(dev, 990 VID_BLK_I2C_ADDRESS, 991 VERT_TIM_CTRL, 992 FLD_VACTIVE_CNT, 993 0x1E7000); 994 status = cx231xx_read_modify_write_i2c_dword(dev, 995 VID_BLK_I2C_ADDRESS, 996 VERT_TIM_CTRL, 997 FLD_V656BLANK_CNT, 998 0x1C000000); 999 1000 status = cx231xx_read_modify_write_i2c_dword(dev, 1001 VID_BLK_I2C_ADDRESS, 1002 HORIZ_TIM_CTRL, 1003 FLD_HBLANK_CNT, 1004 cx231xx_set_field 1005 (FLD_HBLANK_CNT, 0x79)); 1006 1007 } else if (dev->norm & V4L2_STD_SECAM) { 1008 cx231xx_info("do_mode_ctrl_overrides SECAM\n"); 1009 status = cx231xx_read_modify_write_i2c_dword(dev, 1010 VID_BLK_I2C_ADDRESS, 1011 VERT_TIM_CTRL, 1012 FLD_VBLANK_CNT, 0x20); 1013 status = cx231xx_read_modify_write_i2c_dword(dev, 1014 VID_BLK_I2C_ADDRESS, 1015 VERT_TIM_CTRL, 1016 FLD_VACTIVE_CNT, 1017 cx231xx_set_field 1018 (FLD_VACTIVE_CNT, 1019 0x244)); 1020 status = cx231xx_read_modify_write_i2c_dword(dev, 1021 VID_BLK_I2C_ADDRESS, 1022 VERT_TIM_CTRL, 1023 FLD_V656BLANK_CNT, 1024 cx231xx_set_field 1025 (FLD_V656BLANK_CNT, 1026 0x24)); 1027 /* Adjust the active video horizontal start point */ 1028 status = cx231xx_read_modify_write_i2c_dword(dev, 1029 VID_BLK_I2C_ADDRESS, 1030 HORIZ_TIM_CTRL, 1031 FLD_HBLANK_CNT, 1032 cx231xx_set_field 1033 (FLD_HBLANK_CNT, 0x85)); 1034 } else { 1035 cx231xx_info("do_mode_ctrl_overrides PAL\n"); 1036 status = cx231xx_read_modify_write_i2c_dword(dev, 1037 VID_BLK_I2C_ADDRESS, 1038 VERT_TIM_CTRL, 1039 FLD_VBLANK_CNT, 0x20); 1040 status = cx231xx_read_modify_write_i2c_dword(dev, 1041 VID_BLK_I2C_ADDRESS, 1042 VERT_TIM_CTRL, 1043 FLD_VACTIVE_CNT, 1044 cx231xx_set_field 1045 (FLD_VACTIVE_CNT, 1046 0x244)); 1047 status = cx231xx_read_modify_write_i2c_dword(dev, 1048 VID_BLK_I2C_ADDRESS, 1049 VERT_TIM_CTRL, 1050 FLD_V656BLANK_CNT, 1051 cx231xx_set_field 1052 (FLD_V656BLANK_CNT, 1053 0x24)); 1054 /* Adjust the active video horizontal start point */ 1055 status = cx231xx_read_modify_write_i2c_dword(dev, 1056 VID_BLK_I2C_ADDRESS, 1057 HORIZ_TIM_CTRL, 1058 FLD_HBLANK_CNT, 1059 cx231xx_set_field 1060 (FLD_HBLANK_CNT, 0x85)); 1061 1062 } 1063 1064 return status; 1065} 1066 1067int cx231xx_unmute_audio(struct cx231xx *dev) 1068{ 1069 return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24); 1070} 1071EXPORT_SYMBOL_GPL(cx231xx_unmute_audio); 1072 1073int stopAudioFirmware(struct cx231xx *dev) 1074{ 1075 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03); 1076} 1077 1078int restartAudioFirmware(struct cx231xx *dev) 1079{ 1080 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13); 1081} 1082 1083int cx231xx_set_audio_input(struct cx231xx *dev, u8 input) 1084{ 1085 int status = 0; 1086 enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE; 1087 1088 switch (INPUT(input)->amux) { 1089 case CX231XX_AMUX_VIDEO: 1090 ainput = AUDIO_INPUT_TUNER_TV; 1091 break; 1092 case CX231XX_AMUX_LINE_IN: 1093 status = cx231xx_i2s_blk_set_audio_input(dev, input); 1094 ainput = AUDIO_INPUT_LINE; 1095 break; 1096 default: 1097 break; 1098 } 1099 1100 status = cx231xx_set_audio_decoder_input(dev, ainput); 1101 1102 return status; 1103} 1104 1105int cx231xx_set_audio_decoder_input(struct cx231xx *dev, 1106 enum AUDIO_INPUT audio_input) 1107{ 1108 u32 dwval; 1109 int status; 1110 u8 gen_ctrl; 1111 u32 value = 0; 1112 1113 /* Put it in soft reset */ 1114 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl); 1115 gen_ctrl |= 1; 1116 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl); 1117 1118 switch (audio_input) { 1119 case AUDIO_INPUT_LINE: 1120 /* setup AUD_IO control from Merlin paralle output */ 1121 value = cx231xx_set_field(FLD_AUD_CHAN1_SRC, 1122 AUD_CHAN_SRC_PARALLEL); 1123 status = vid_blk_write_word(dev, AUD_IO_CTRL, value); 1124 1125 /* setup input to Merlin, SRC2 connect to AC97 1126 bypass upsample-by-2, slave mode, sony mode, left justify 1127 adr 091c, dat 01000000 */ 1128 status = vid_blk_read_word(dev, AC97_CTL, &dwval); 1129 1130 status = vid_blk_write_word(dev, AC97_CTL, 1131 (dwval | FLD_AC97_UP2X_BYPASS)); 1132 1133 /* select the parallel1 and SRC3 */ 1134 status = vid_blk_write_word(dev, BAND_OUT_SEL, 1135 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) | 1136 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) | 1137 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0)); 1138 1139 /* unmute all, AC97 in, independence mode 1140 adr 08d0, data 0x00063073 */ 1141 status = vid_blk_write_word(dev, DL_CTL, 0x3000001); 1142 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073); 1143 1144 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */ 1145 status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval); 1146 status = vid_blk_write_word(dev, PATH1_VOL_CTL, 1147 (dwval | FLD_PATH1_AVC_THRESHOLD)); 1148 1149 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */ 1150 status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval); 1151 status = vid_blk_write_word(dev, PATH1_SC_CTL, 1152 (dwval | FLD_PATH1_SC_THRESHOLD)); 1153 break; 1154 1155 case AUDIO_INPUT_TUNER_TV: 1156 default: 1157 status = stopAudioFirmware(dev); 1158 /* Setup SRC sources and clocks */ 1159 status = vid_blk_write_word(dev, BAND_OUT_SEL, 1160 cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) | 1161 cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) | 1162 cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) | 1163 cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) | 1164 cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) | 1165 cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) | 1166 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) | 1167 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) | 1168 cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) | 1169 cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) | 1170 cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) | 1171 cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) | 1172 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01)); 1173 1174 /* Setup the AUD_IO control */ 1175 status = vid_blk_write_word(dev, AUD_IO_CTRL, 1176 cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) | 1177 cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) | 1178 cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) | 1179 cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) | 1180 cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03)); 1181 1182 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870); 1183 1184 /* setAudioStandard(_audio_standard); */ 1185 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870); 1186 1187 status = restartAudioFirmware(dev); 1188 1189 switch (dev->board.tuner_type) { 1190 case TUNER_XC5000: 1191 /* SIF passthrough at 28.6363 MHz sample rate */ 1192 status = cx231xx_read_modify_write_i2c_dword(dev, 1193 VID_BLK_I2C_ADDRESS, 1194 CHIP_CTRL, 1195 FLD_SIF_EN, 1196 cx231xx_set_field(FLD_SIF_EN, 1)); 1197 break; 1198 case TUNER_NXP_TDA18271: 1199 /* Normal mode: SIF passthrough at 14.32 MHz */ 1200 status = cx231xx_read_modify_write_i2c_dword(dev, 1201 VID_BLK_I2C_ADDRESS, 1202 CHIP_CTRL, 1203 FLD_SIF_EN, 1204 cx231xx_set_field(FLD_SIF_EN, 0)); 1205 break; 1206 default: 1207 /* This is just a casual suggestion to people adding 1208 new boards in case they use a tuner type we don't 1209 currently know about */ 1210 printk(KERN_INFO "Unknown tuner type configuring SIF"); 1211 break; 1212 } 1213 break; 1214 1215 case AUDIO_INPUT_TUNER_FM: 1216 /* use SIF for FM radio 1217 setupFM(); 1218 setAudioStandard(_audio_standard); 1219 */ 1220 break; 1221 1222 case AUDIO_INPUT_MUTE: 1223 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012); 1224 break; 1225 } 1226 1227 /* Take it out of soft reset */ 1228 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl); 1229 gen_ctrl &= ~1; 1230 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl); 1231 1232 return status; 1233} 1234 1235/****************************************************************************** 1236 * C H I P Specific C O N T R O L functions * 1237 ******************************************************************************/ 1238int cx231xx_init_ctrl_pin_status(struct cx231xx *dev) 1239{ 1240 u32 value; 1241 int status = 0; 1242 1243 status = vid_blk_read_word(dev, PIN_CTRL, &value); 1244 value |= (~dev->board.ctl_pin_status_mask); 1245 status = vid_blk_write_word(dev, PIN_CTRL, value); 1246 1247 return status; 1248} 1249 1250int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev, 1251 u8 analog_or_digital) 1252{ 1253 int status = 0; 1254 1255 /* first set the direction to output */ 1256 status = cx231xx_set_gpio_direction(dev, 1257 dev->board. 1258 agc_analog_digital_select_gpio, 1); 1259 1260 /* 0 - demod ; 1 - Analog mode */ 1261 status = cx231xx_set_gpio_value(dev, 1262 dev->board.agc_analog_digital_select_gpio, 1263 analog_or_digital); 1264 1265 return status; 1266} 1267 1268int cx231xx_enable_i2c_port_3(struct cx231xx *dev, bool is_port_3) 1269{ 1270 u8 value[4] = { 0, 0, 0, 0 }; 1271 int status = 0; 1272 bool current_is_port_3; 1273 1274 if (dev->board.dont_use_port_3) 1275 is_port_3 = false; 1276 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, 1277 PWR_CTL_EN, value, 4); 1278 if (status < 0) 1279 return status; 1280 1281 current_is_port_3 = value[0] & I2C_DEMOD_EN ? true : false; 1282 1283 /* Just return, if already using the right port */ 1284 if (current_is_port_3 == is_port_3) 1285 return 0; 1286 1287 if (is_port_3) 1288 value[0] |= I2C_DEMOD_EN; 1289 else 1290 value[0] &= ~I2C_DEMOD_EN; 1291 1292 cx231xx_info("Changing the i2c master port to %d\n", 1293 is_port_3 ? 3 : 1); 1294 1295 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1296 PWR_CTL_EN, value, 4); 1297 1298 return status; 1299 1300} 1301EXPORT_SYMBOL_GPL(cx231xx_enable_i2c_port_3); 1302 1303void update_HH_register_after_set_DIF(struct cx231xx *dev) 1304{ 1305/* 1306 u8 status = 0; 1307 u32 value = 0; 1308 1309 vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F); 1310 vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11); 1311 vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06); 1312 1313 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1314 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390); 1315 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1316*/ 1317} 1318 1319void cx231xx_dump_HH_reg(struct cx231xx *dev) 1320{ 1321 u8 status = 0; 1322 u32 value = 0; 1323 u16 i = 0; 1324 1325 value = 0x45005390; 1326 status = vid_blk_write_word(dev, 0x104, value); 1327 1328 for (i = 0x100; i < 0x140; i++) { 1329 status = vid_blk_read_word(dev, i, &value); 1330 cx231xx_info("reg0x%x=0x%x\n", i, value); 1331 i = i+3; 1332 } 1333 1334 for (i = 0x300; i < 0x400; i++) { 1335 status = vid_blk_read_word(dev, i, &value); 1336 cx231xx_info("reg0x%x=0x%x\n", i, value); 1337 i = i+3; 1338 } 1339 1340 for (i = 0x400; i < 0x440; i++) { 1341 status = vid_blk_read_word(dev, i, &value); 1342 cx231xx_info("reg0x%x=0x%x\n", i, value); 1343 i = i+3; 1344 } 1345 1346 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1347 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value); 1348 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390); 1349 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1350 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value); 1351} 1352 1353void cx231xx_dump_SC_reg(struct cx231xx *dev) 1354{ 1355 u8 value[4] = { 0, 0, 0, 0 }; 1356 int status = 0; 1357 cx231xx_info("cx231xx_dump_SC_reg!\n"); 1358 1359 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT, 1360 value, 4); 1361 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0], 1362 value[1], value[2], value[3]); 1363 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG, 1364 value, 4); 1365 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0], 1366 value[1], value[2], value[3]); 1367 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG, 1368 value, 4); 1369 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0], 1370 value[1], value[2], value[3]); 1371 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG, 1372 value, 4); 1373 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0], 1374 value[1], value[2], value[3]); 1375 1376 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG, 1377 value, 4); 1378 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0], 1379 value[1], value[2], value[3]); 1380 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG, 1381 value, 4); 1382 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0], 1383 value[1], value[2], value[3]); 1384 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, 1385 value, 4); 1386 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0], 1387 value[1], value[2], value[3]); 1388 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1, 1389 value, 4); 1390 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0], 1391 value[1], value[2], value[3]); 1392 1393 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2, 1394 value, 4); 1395 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0], 1396 value[1], value[2], value[3]); 1397 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3, 1398 value, 4); 1399 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0], 1400 value[1], value[2], value[3]); 1401 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0, 1402 value, 4); 1403 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0], 1404 value[1], value[2], value[3]); 1405 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1, 1406 value, 4); 1407 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0], 1408 value[1], value[2], value[3]); 1409 1410 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2, 1411 value, 4); 1412 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0], 1413 value[1], value[2], value[3]); 1414 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN, 1415 value, 4); 1416 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0], 1417 value[1], value[2], value[3]); 1418 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG, 1419 value, 4); 1420 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0], 1421 value[1], value[2], value[3]); 1422 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1, 1423 value, 4); 1424 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0], 1425 value[1], value[2], value[3]); 1426 1427 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2, 1428 value, 4); 1429 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0], 1430 value[1], value[2], value[3]); 1431 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, 1432 value, 4); 1433 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0], 1434 value[1], value[2], value[3]); 1435 1436 1437} 1438 1439void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev) 1440 1441{ 1442 u8 status = 0; 1443 u8 value = 0; 1444 1445 1446 1447 status = afe_read_byte(dev, ADC_STATUS2_CH3, &value); 1448 value = (value & 0xFE)|0x01; 1449 status = afe_write_byte(dev, ADC_STATUS2_CH3, value); 1450 1451 status = afe_read_byte(dev, ADC_STATUS2_CH3, &value); 1452 value = (value & 0xFE)|0x00; 1453 status = afe_write_byte(dev, ADC_STATUS2_CH3, value); 1454 1455 1456/* 1457 config colibri to lo-if mode 1458 1459 FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce 1460 the diff IF input by half, 1461 1462 for low-if agc defect 1463*/ 1464 1465 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value); 1466 value = (value & 0xFC)|0x00; 1467 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value); 1468 1469 status = afe_read_byte(dev, ADC_INPUT_CH3, &value); 1470 value = (value & 0xF9)|0x02; 1471 status = afe_write_byte(dev, ADC_INPUT_CH3, value); 1472 1473 status = afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value); 1474 value = (value & 0xFB)|0x04; 1475 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, value); 1476 1477 status = afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value); 1478 value = (value & 0xFC)|0x03; 1479 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value); 1480 1481 status = afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value); 1482 value = (value & 0xFB)|0x04; 1483 status = afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value); 1484 1485 status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value); 1486 value = (value & 0xF8)|0x06; 1487 status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value); 1488 1489 status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value); 1490 value = (value & 0x8F)|0x40; 1491 status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value); 1492 1493 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value); 1494 value = (value & 0xDF)|0x20; 1495 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value); 1496} 1497 1498void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq, 1499 u8 spectral_invert, u32 mode) 1500{ 1501 u32 colibri_carrier_offset = 0; 1502 u8 status = 0; 1503 u32 func_mode = 0x01; /* Device has a DIF if this function is called */ 1504 u32 standard = 0; 1505 u8 value[4] = { 0, 0, 0, 0 }; 1506 1507 cx231xx_info("Enter cx231xx_set_Colibri_For_LowIF()\n"); 1508 value[0] = (u8) 0x6F; 1509 value[1] = (u8) 0x6F; 1510 value[2] = (u8) 0x6F; 1511 value[3] = (u8) 0x6F; 1512 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1513 PWR_CTL_EN, value, 4); 1514 1515 /*Set colibri for low IF*/ 1516 status = cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF); 1517 1518 /* Set C2HH for low IF operation.*/ 1519 standard = dev->norm; 1520 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode, 1521 func_mode, standard); 1522 1523 /* Get colibri offsets.*/ 1524 colibri_carrier_offset = cx231xx_Get_Colibri_CarrierOffset(mode, 1525 standard); 1526 1527 cx231xx_info("colibri_carrier_offset=%d, standard=0x%x\n", 1528 colibri_carrier_offset, standard); 1529 1530 /* Set the band Pass filter for DIF*/ 1531 cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset), 1532 spectral_invert, mode); 1533} 1534 1535u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd) 1536{ 1537 u32 colibri_carrier_offset = 0; 1538 1539 if (mode == TUNER_MODE_FM_RADIO) { 1540 colibri_carrier_offset = 1100000; 1541 } else if (standerd & (V4L2_STD_MN | V4L2_STD_NTSC_M_JP)) { 1542 colibri_carrier_offset = 4832000; /*4.83MHz */ 1543 } else if (standerd & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) { 1544 colibri_carrier_offset = 2700000; /*2.70MHz */ 1545 } else if (standerd & (V4L2_STD_PAL_D | V4L2_STD_PAL_I 1546 | V4L2_STD_SECAM)) { 1547 colibri_carrier_offset = 2100000; /*2.10MHz */ 1548 } 1549 1550 return colibri_carrier_offset; 1551} 1552 1553void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq, 1554 u8 spectral_invert, u32 mode) 1555{ 1556 unsigned long pll_freq_word; 1557 int status = 0; 1558 u32 dif_misc_ctrl_value = 0; 1559 u64 pll_freq_u64 = 0; 1560 u32 i = 0; 1561 1562 cx231xx_info("if_freq=%d;spectral_invert=0x%x;mode=0x%x\n", 1563 if_freq, spectral_invert, mode); 1564 1565 1566 if (mode == TUNER_MODE_FM_RADIO) { 1567 pll_freq_word = 0x905A1CAC; 1568 status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word); 1569 1570 } else /*KSPROPERTY_TUNER_MODE_TV*/{ 1571 /* Calculate the PLL frequency word based on the adjusted if_freq*/ 1572 pll_freq_word = if_freq; 1573 pll_freq_u64 = (u64)pll_freq_word << 28L; 1574 do_div(pll_freq_u64, 50000000); 1575 pll_freq_word = (u32)pll_freq_u64; 1576 /*pll_freq_word = 0x3463497;*/ 1577 status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word); 1578 1579 if (spectral_invert) { 1580 if_freq -= 400000; 1581 /* Enable Spectral Invert*/ 1582 status = vid_blk_read_word(dev, DIF_MISC_CTRL, 1583 &dif_misc_ctrl_value); 1584 dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000; 1585 status = vid_blk_write_word(dev, DIF_MISC_CTRL, 1586 dif_misc_ctrl_value); 1587 } else { 1588 if_freq += 400000; 1589 /* Disable Spectral Invert*/ 1590 status = vid_blk_read_word(dev, DIF_MISC_CTRL, 1591 &dif_misc_ctrl_value); 1592 dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF; 1593 status = vid_blk_write_word(dev, DIF_MISC_CTRL, 1594 dif_misc_ctrl_value); 1595 } 1596 1597 if_freq = (if_freq/100000)*100000; 1598 1599 if (if_freq < 3000000) 1600 if_freq = 3000000; 1601 1602 if (if_freq > 16000000) 1603 if_freq = 16000000; 1604 } 1605 1606 cx231xx_info("Enter IF=%zd\n", 1607 sizeof(Dif_set_array)/sizeof(struct dif_settings)); 1608 for (i = 0; i < sizeof(Dif_set_array)/sizeof(struct dif_settings); i++) { 1609 if (Dif_set_array[i].if_freq == if_freq) { 1610 status = vid_blk_write_word(dev, 1611 Dif_set_array[i].register_address, Dif_set_array[i].value); 1612 } 1613 } 1614} 1615 1616/****************************************************************************** 1617 * D I F - B L O C K C O N T R O L functions * 1618 ******************************************************************************/ 1619int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, 1620 u32 function_mode, u32 standard) 1621{ 1622 int status = 0; 1623 1624 1625 if (mode == V4L2_TUNER_RADIO) { 1626 /* C2HH */ 1627 /* lo if big signal */ 1628 status = cx231xx_reg_mask_write(dev, 1629 VID_BLK_I2C_ADDRESS, 32, 1630 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1631 /* FUNC_MODE = DIF */ 1632 status = cx231xx_reg_mask_write(dev, 1633 VID_BLK_I2C_ADDRESS, 32, 1634 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); 1635 /* IF_MODE */ 1636 status = cx231xx_reg_mask_write(dev, 1637 VID_BLK_I2C_ADDRESS, 32, 1638 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF); 1639 /* no inv */ 1640 status = cx231xx_reg_mask_write(dev, 1641 VID_BLK_I2C_ADDRESS, 32, 1642 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1643 } else if (standard != DIF_USE_BASEBAND) { 1644 if (standard & V4L2_STD_MN) { 1645 /* lo if big signal */ 1646 status = cx231xx_reg_mask_write(dev, 1647 VID_BLK_I2C_ADDRESS, 32, 1648 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1649 /* FUNC_MODE = DIF */ 1650 status = cx231xx_reg_mask_write(dev, 1651 VID_BLK_I2C_ADDRESS, 32, 1652 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 1653 function_mode); 1654 /* IF_MODE */ 1655 status = cx231xx_reg_mask_write(dev, 1656 VID_BLK_I2C_ADDRESS, 32, 1657 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb); 1658 /* no inv */ 1659 status = cx231xx_reg_mask_write(dev, 1660 VID_BLK_I2C_ADDRESS, 32, 1661 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1662 /* 0x124, AUD_CHAN1_SRC = 0x3 */ 1663 status = cx231xx_reg_mask_write(dev, 1664 VID_BLK_I2C_ADDRESS, 32, 1665 AUD_IO_CTRL, 0, 31, 0x00000003); 1666 } else if ((standard == V4L2_STD_PAL_I) | 1667 (standard & V4L2_STD_PAL_D) | 1668 (standard & V4L2_STD_SECAM)) { 1669 /* C2HH setup */ 1670 /* lo if big signal */ 1671 status = cx231xx_reg_mask_write(dev, 1672 VID_BLK_I2C_ADDRESS, 32, 1673 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1674 /* FUNC_MODE = DIF */ 1675 status = cx231xx_reg_mask_write(dev, 1676 VID_BLK_I2C_ADDRESS, 32, 1677 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 1678 function_mode); 1679 /* IF_MODE */ 1680 status = cx231xx_reg_mask_write(dev, 1681 VID_BLK_I2C_ADDRESS, 32, 1682 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); 1683 /* no inv */ 1684 status = cx231xx_reg_mask_write(dev, 1685 VID_BLK_I2C_ADDRESS, 32, 1686 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1687 } else { 1688 /* default PAL BG */ 1689 /* C2HH setup */ 1690 /* lo if big signal */ 1691 status = cx231xx_reg_mask_write(dev, 1692 VID_BLK_I2C_ADDRESS, 32, 1693 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1694 /* FUNC_MODE = DIF */ 1695 status = cx231xx_reg_mask_write(dev, 1696 VID_BLK_I2C_ADDRESS, 32, 1697 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 1698 function_mode); 1699 /* IF_MODE */ 1700 status = cx231xx_reg_mask_write(dev, 1701 VID_BLK_I2C_ADDRESS, 32, 1702 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); 1703 /* no inv */ 1704 status = cx231xx_reg_mask_write(dev, 1705 VID_BLK_I2C_ADDRESS, 32, 1706 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1707 } 1708 } 1709 1710 return status; 1711} 1712 1713int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) 1714{ 1715 int status = 0; 1716 u32 dif_misc_ctrl_value = 0; 1717 u32 func_mode = 0; 1718 1719 cx231xx_info("%s: setStandard to %x\n", __func__, standard); 1720 1721 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value); 1722 if (standard != DIF_USE_BASEBAND) 1723 dev->norm = standard; 1724 1725 switch (dev->model) { 1726 case CX231XX_BOARD_CNXT_CARRAERA: 1727 case CX231XX_BOARD_CNXT_RDE_250: 1728 case CX231XX_BOARD_CNXT_SHELBY: 1729 case CX231XX_BOARD_CNXT_RDU_250: 1730 case CX231XX_BOARD_CNXT_VIDEO_GRABBER: 1731 …
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