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/drivers/media/dvb/frontends/mt352_priv.h

https://bitbucket.org/ndreys/linux-sunxi
C++ Header | 127 lines | 89 code | 6 blank | 32 comment | 0 complexity | 35b630fe3879748872baa1ea0756eb76 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1/*
  2 *  Driver for Zarlink DVB-T MT352 demodulator
  3 *
  4 *  Written by Holger Waechtler <holger@qanu.de>
  5 *	 and Daniel Mack <daniel@qanu.de>
  6 *
  7 *  AVerMedia AVerTV DVB-T 771 support by
  8 *       Wolfram Joost <dbox2@frokaschwei.de>
  9 *
 10 *  Support for Samsung TDTC9251DH01C(M) tuner
 11 *  Copyright (C) 2004 Antonio Mancuso <antonio.mancuso@digitaltelevision.it>
 12 *                     Amauri  Celani  <acelani@essegi.net>
 13 *
 14 *  DVICO FusionHDTV DVB-T1 and DVICO FusionHDTV DVB-T Lite support by
 15 *       Christopher Pascoe <c.pascoe@itee.uq.edu.au>
 16 *
 17 *  This program is free software; you can redistribute it and/or modify
 18 *  it under the terms of the GNU General Public License as published by
 19 *  the Free Software Foundation; either version 2 of the License, or
 20 *  (at your option) any later version.
 21 *
 22 *  This program is distributed in the hope that it will be useful,
 23 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 24 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 25 *
 26 *  GNU General Public License for more details.
 27 *
 28 *  You should have received a copy of the GNU General Public License
 29 *  along with this program; if not, write to the Free Software
 30 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
 31 */
 32
 33#ifndef _MT352_PRIV_
 34#define _MT352_PRIV_
 35
 36#define ID_MT352        0x13
 37
 38#define msb(x) (((x) >> 8) & 0xff)
 39#define lsb(x) ((x) & 0xff)
 40
 41enum mt352_reg_addr {
 42	STATUS_0           = 0x00,
 43	STATUS_1           = 0x01,
 44	STATUS_2           = 0x02,
 45	STATUS_3           = 0x03,
 46	STATUS_4           = 0x04,
 47	INTERRUPT_0        = 0x05,
 48	INTERRUPT_1        = 0x06,
 49	INTERRUPT_2        = 0x07,
 50	INTERRUPT_3        = 0x08,
 51	SNR                = 0x09,
 52	VIT_ERR_CNT_2      = 0x0A,
 53	VIT_ERR_CNT_1      = 0x0B,
 54	VIT_ERR_CNT_0      = 0x0C,
 55	RS_ERR_CNT_2       = 0x0D,
 56	RS_ERR_CNT_1       = 0x0E,
 57	RS_ERR_CNT_0       = 0x0F,
 58	RS_UBC_1           = 0x10,
 59	RS_UBC_0           = 0x11,
 60	AGC_GAIN_3         = 0x12,
 61	AGC_GAIN_2         = 0x13,
 62	AGC_GAIN_1         = 0x14,
 63	AGC_GAIN_0         = 0x15,
 64	FREQ_OFFSET_2      = 0x17,
 65	FREQ_OFFSET_1      = 0x18,
 66	FREQ_OFFSET_0      = 0x19,
 67	TIMING_OFFSET_1    = 0x1A,
 68	TIMING_OFFSET_0    = 0x1B,
 69	CHAN_FREQ_1        = 0x1C,
 70	CHAN_FREQ_0        = 0x1D,
 71	TPS_RECEIVED_1     = 0x1E,
 72	TPS_RECEIVED_0     = 0x1F,
 73	TPS_CURRENT_1      = 0x20,
 74	TPS_CURRENT_0      = 0x21,
 75	TPS_CELL_ID_1      = 0x22,
 76	TPS_CELL_ID_0      = 0x23,
 77	TPS_MISC_DATA_2    = 0x24,
 78	TPS_MISC_DATA_1    = 0x25,
 79	TPS_MISC_DATA_0    = 0x26,
 80	RESET              = 0x50,
 81	TPS_GIVEN_1        = 0x51,
 82	TPS_GIVEN_0        = 0x52,
 83	ACQ_CTL            = 0x53,
 84	TRL_NOMINAL_RATE_1 = 0x54,
 85	TRL_NOMINAL_RATE_0 = 0x55,
 86	INPUT_FREQ_1       = 0x56,
 87	INPUT_FREQ_0       = 0x57,
 88	TUNER_ADDR         = 0x58,
 89	CHAN_START_1       = 0x59,
 90	CHAN_START_0       = 0x5A,
 91	CONT_1             = 0x5B,
 92	CONT_0             = 0x5C,
 93	TUNER_GO           = 0x5D,
 94	STATUS_EN_0        = 0x5F,
 95	STATUS_EN_1        = 0x60,
 96	INTERRUPT_EN_0     = 0x61,
 97	INTERRUPT_EN_1     = 0x62,
 98	INTERRUPT_EN_2     = 0x63,
 99	INTERRUPT_EN_3     = 0x64,
100	AGC_TARGET         = 0x67,
101	AGC_CTL            = 0x68,
102	CAPT_RANGE         = 0x75,
103	SNR_SELECT_1       = 0x79,
104	SNR_SELECT_0       = 0x7A,
105	RS_ERR_PER_1       = 0x7C,
106	RS_ERR_PER_0       = 0x7D,
107	CHIP_ID            = 0x7F,
108	CHAN_STOP_1        = 0x80,
109	CHAN_STOP_0        = 0x81,
110	CHAN_STEP_1        = 0x82,
111	CHAN_STEP_0        = 0x83,
112	FEC_LOCK_TIME      = 0x85,
113	OFDM_LOCK_TIME     = 0x86,
114	ACQ_DELAY          = 0x87,
115	SCAN_CTL           = 0x88,
116	CLOCK_CTL          = 0x89,
117	CONFIG             = 0x8A,
118	MCLK_RATIO         = 0x8B,
119	GPP_CTL            = 0x8C,
120	ADC_CTL_1          = 0x8E,
121	ADC_CTL_0          = 0x8F
122};
123
124/* here we assume 1/6MHz == 166.66kHz stepsize */
125#define IF_FREQUENCYx6 217    /* 6 * 36.16666666667MHz */
126
127#endif                          /* _MT352_PRIV_ */