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/drivers/infiniband/hw/nes/nes_context.h

https://bitbucket.org/ndreys/linux-sunxi
C++ Header | 193 lines | 140 code | 16 blank | 37 comment | 0 complexity | 965310076073fa260549fa14ef6aeddf MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1/*
  2 * Copyright (c) 2006 - 2009 Intel Corporation.  All rights reserved.
  3 *
  4 * This software is available to you under a choice of one of two
  5 * licenses.  You may choose to be licensed under the terms of the GNU
  6 * General Public License (GPL) Version 2, available from the file
  7 * COPYING in the main directory of this source tree, or the
  8 * OpenIB.org BSD license below:
  9 *
 10 *     Redistribution and use in source and binary forms, with or
 11 *     without modification, are permitted provided that the following
 12 *     conditions are met:
 13 *
 14 *      - Redistributions of source code must retain the above
 15 *        copyright notice, this list of conditions and the following
 16 *        disclaimer.
 17 *
 18 *      - Redistributions in binary form must reproduce the above
 19 *        copyright notice, this list of conditions and the following
 20 *        disclaimer in the documentation and/or other materials
 21 *        provided with the distribution.
 22 *
 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 30 * SOFTWARE.
 31 */
 32
 33#ifndef NES_CONTEXT_H
 34#define NES_CONTEXT_H
 35
 36struct nes_qp_context {
 37	__le32   misc;
 38	__le32   cqs;
 39	__le32   sq_addr_low;
 40	__le32   sq_addr_high;
 41	__le32   rq_addr_low;
 42	__le32   rq_addr_high;
 43	__le32   misc2;
 44	__le16   tcpPorts[2];
 45	__le32   ip0;
 46	__le32   ip1;
 47	__le32   ip2;
 48	__le32   ip3;
 49	__le32   mss;
 50	__le32   arp_index_vlan;
 51	__le32   tcp_state_flow_label;
 52	__le32   pd_index_wscale;
 53	__le32   keepalive;
 54	u32   ts_recent;
 55	u32   ts_age;
 56	__le32   snd_nxt;
 57	__le32   snd_wnd;
 58	__le32   rcv_nxt;
 59	__le32   rcv_wnd;
 60	__le32   snd_max;
 61	__le32   snd_una;
 62	u32   srtt;
 63	__le32   rttvar;
 64	__le32   ssthresh;
 65	__le32   cwnd;
 66	__le32   snd_wl1;
 67	__le32   snd_wl2;
 68	__le32   max_snd_wnd;
 69	__le32   ts_val_delta;
 70	u32   retransmit;
 71	u32   probe_cnt;
 72	u32   hte_index;
 73	__le32   q2_addr_low;
 74	__le32   q2_addr_high;
 75	__le32   ird_index;
 76	u32   Rsvd3;
 77	__le32   ird_ord_sizes;
 78	u32   mrkr_offset;
 79	__le32   aeq_token_low;
 80	__le32   aeq_token_high;
 81};
 82
 83/* QP Context Misc Field */
 84
 85#define NES_QPCONTEXT_MISC_IWARP_VER_MASK    0x00000003
 86#define NES_QPCONTEXT_MISC_IWARP_VER_SHIFT   0
 87#define NES_QPCONTEXT_MISC_EFB_SIZE_MASK     0x000000C0
 88#define NES_QPCONTEXT_MISC_EFB_SIZE_SHIFT    6
 89#define NES_QPCONTEXT_MISC_RQ_SIZE_MASK      0x00000300
 90#define NES_QPCONTEXT_MISC_RQ_SIZE_SHIFT     8
 91#define NES_QPCONTEXT_MISC_SQ_SIZE_MASK      0x00000c00
 92#define NES_QPCONTEXT_MISC_SQ_SIZE_SHIFT     10
 93#define NES_QPCONTEXT_MISC_PCI_FCN_MASK      0x00007000
 94#define NES_QPCONTEXT_MISC_PCI_FCN_SHIFT     12
 95#define NES_QPCONTEXT_MISC_DUP_ACKS_MASK     0x00070000
 96#define NES_QPCONTEXT_MISC_DUP_ACKS_SHIFT    16
 97
 98enum nes_qp_context_misc_bits {
 99	NES_QPCONTEXT_MISC_RX_WQE_SIZE         = 0x00000004,
100	NES_QPCONTEXT_MISC_IPV4                = 0x00000008,
101	NES_QPCONTEXT_MISC_DO_NOT_FRAG         = 0x00000010,
102	NES_QPCONTEXT_MISC_INSERT_VLAN         = 0x00000020,
103	NES_QPCONTEXT_MISC_DROS                = 0x00008000,
104	NES_QPCONTEXT_MISC_WSCALE              = 0x00080000,
105	NES_QPCONTEXT_MISC_KEEPALIVE           = 0x00100000,
106	NES_QPCONTEXT_MISC_TIMESTAMP           = 0x00200000,
107	NES_QPCONTEXT_MISC_SACK                = 0x00400000,
108	NES_QPCONTEXT_MISC_RDMA_WRITE_EN       = 0x00800000,
109	NES_QPCONTEXT_MISC_RDMA_READ_EN        = 0x01000000,
110	NES_QPCONTEXT_MISC_WBIND_EN            = 0x10000000,
111	NES_QPCONTEXT_MISC_FAST_REGISTER_EN    = 0x20000000,
112	NES_QPCONTEXT_MISC_PRIV_EN             = 0x40000000,
113	NES_QPCONTEXT_MISC_NO_NAGLE            = 0x80000000
114};
115
116enum nes_qp_acc_wq_sizes {
117	HCONTEXT_TSA_WQ_SIZE_4 = 0,
118	HCONTEXT_TSA_WQ_SIZE_32 = 1,
119	HCONTEXT_TSA_WQ_SIZE_128 = 2,
120	HCONTEXT_TSA_WQ_SIZE_512 = 3
121};
122
123/* QP Context Misc2 Fields */
124#define NES_QPCONTEXT_MISC2_TTL_MASK            0x000000ff
125#define NES_QPCONTEXT_MISC2_TTL_SHIFT           0
126#define NES_QPCONTEXT_MISC2_HOP_LIMIT_MASK      0x000000ff
127#define NES_QPCONTEXT_MISC2_HOP_LIMIT_SHIFT     0
128#define NES_QPCONTEXT_MISC2_LIMIT_MASK          0x00000300
129#define NES_QPCONTEXT_MISC2_LIMIT_SHIFT         8
130#define NES_QPCONTEXT_MISC2_NIC_INDEX_MASK      0x0000fc00
131#define NES_QPCONTEXT_MISC2_NIC_INDEX_SHIFT     10
132#define NES_QPCONTEXT_MISC2_SRC_IP_MASK         0x001f0000
133#define NES_QPCONTEXT_MISC2_SRC_IP_SHIFT        16
134#define NES_QPCONTEXT_MISC2_TOS_MASK            0xff000000
135#define NES_QPCONTEXT_MISC2_TOS_SHIFT           24
136#define NES_QPCONTEXT_MISC2_TRAFFIC_CLASS_MASK  0xff000000
137#define NES_QPCONTEXT_MISC2_TRAFFIC_CLASS_SHIFT 24
138
139/* QP Context Tcp State/Flow Label Fields */
140#define NES_QPCONTEXT_TCPFLOW_FLOW_LABEL_MASK   0x000fffff
141#define NES_QPCONTEXT_TCPFLOW_FLOW_LABEL_SHIFT  0
142#define NES_QPCONTEXT_TCPFLOW_TCP_STATE_MASK    0xf0000000
143#define NES_QPCONTEXT_TCPFLOW_TCP_STATE_SHIFT   28
144
145enum nes_qp_tcp_state {
146	NES_QPCONTEXT_TCPSTATE_CLOSED = 1,
147	NES_QPCONTEXT_TCPSTATE_EST = 5,
148	NES_QPCONTEXT_TCPSTATE_TIME_WAIT = 11,
149};
150
151/* QP Context PD Index/wscale Fields */
152#define NES_QPCONTEXT_PDWSCALE_RCV_WSCALE_MASK  0x0000000f
153#define NES_QPCONTEXT_PDWSCALE_RCV_WSCALE_SHIFT 0
154#define NES_QPCONTEXT_PDWSCALE_SND_WSCALE_MASK  0x00000f00
155#define NES_QPCONTEXT_PDWSCALE_SND_WSCALE_SHIFT 8
156#define NES_QPCONTEXT_PDWSCALE_PDINDEX_MASK     0xffff0000
157#define NES_QPCONTEXT_PDWSCALE_PDINDEX_SHIFT    16
158
159/* QP Context Keepalive Fields */
160#define NES_QPCONTEXT_KEEPALIVE_DELTA_MASK      0x0000ffff
161#define NES_QPCONTEXT_KEEPALIVE_DELTA_SHIFT     0
162#define NES_QPCONTEXT_KEEPALIVE_PROBE_CNT_MASK  0x00ff0000
163#define NES_QPCONTEXT_KEEPALIVE_PROBE_CNT_SHIFT 16
164#define NES_QPCONTEXT_KEEPALIVE_INTV_MASK       0xff000000
165#define NES_QPCONTEXT_KEEPALIVE_INTV_SHIFT      24
166
167/* QP Context ORD/IRD Fields */
168#define NES_QPCONTEXT_ORDIRD_ORDSIZE_MASK       0x0000007f
169#define NES_QPCONTEXT_ORDIRD_ORDSIZE_SHIFT      0
170#define NES_QPCONTEXT_ORDIRD_IRDSIZE_MASK       0x00030000
171#define NES_QPCONTEXT_ORDIRD_IRDSIZE_SHIFT      16
172#define NES_QPCONTEXT_ORDIRD_IWARP_MODE_MASK    0x30000000
173#define NES_QPCONTEXT_ORDIRD_IWARP_MODE_SHIFT   28
174
175enum nes_ord_ird_bits {
176	NES_QPCONTEXT_ORDIRD_WRPDU                   = 0x02000000,
177	NES_QPCONTEXT_ORDIRD_LSMM_PRESENT            = 0x04000000,
178	NES_QPCONTEXT_ORDIRD_ALSMM                   = 0x08000000,
179	NES_QPCONTEXT_ORDIRD_AAH                     = 0x40000000,
180	NES_QPCONTEXT_ORDIRD_RNMC                    = 0x80000000
181};
182
183enum nes_iwarp_qp_state {
184	NES_QPCONTEXT_IWARP_STATE_NONEXIST  = 0,
185	NES_QPCONTEXT_IWARP_STATE_IDLE      = 1,
186	NES_QPCONTEXT_IWARP_STATE_RTS       = 2,
187	NES_QPCONTEXT_IWARP_STATE_CLOSING   = 3,
188	NES_QPCONTEXT_IWARP_STATE_TERMINATE = 5,
189	NES_QPCONTEXT_IWARP_STATE_ERROR     = 6
190};
191
192
193#endif		/* NES_CONTEXT_H */