/drivers/gpu/mali/mali/regs/mali_gp_regs.h
C++ Header | 214 lines | 154 code | 19 blank | 41 comment | 4 complexity | 951688ef6047efa6c7eeddaa06bc3b23 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
1/* 2 * Copyright (C) 2010, 2012 ARM Limited. All rights reserved. 3 * 4 * This program is free software and is provided to you under the terms of the GNU General Public License version 2 5 * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence. 6 * 7 * A copy of the licence is included with the program, and can also be obtained from Free Software 8 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 9 */ 10 11#ifndef _MALIGP2_CONROL_REGS_H_ 12#define _MALIGP2_CONROL_REGS_H_ 13 14/** 15 * These are the different geometry processor control registers. 16 * Their usage is to control and monitor the operation of the 17 * Vertex Shader and the Polygon List Builder in the geometry processor. 18 * Addresses are in 32-bit word relative sizes. 19 * @see [P0081] "Geometry Processor Data Structures" for details 20 */ 21 22typedef enum { 23 MALIGP2_REG_ADDR_MGMT_VSCL_START_ADDR = 0x00, 24 MALIGP2_REG_ADDR_MGMT_VSCL_END_ADDR = 0x04, 25 MALIGP2_REG_ADDR_MGMT_PLBUCL_START_ADDR = 0x08, 26 MALIGP2_REG_ADDR_MGMT_PLBUCL_END_ADDR = 0x0c, 27 MALIGP2_REG_ADDR_MGMT_PLBU_ALLOC_START_ADDR = 0x10, 28 MALIGP2_REG_ADDR_MGMT_PLBU_ALLOC_END_ADDR = 0x14, 29 MALIGP2_REG_ADDR_MGMT_CMD = 0x20, 30 MALIGP2_REG_ADDR_MGMT_INT_RAWSTAT = 0x24, 31 MALIGP2_REG_ADDR_MGMT_INT_CLEAR = 0x28, 32 MALIGP2_REG_ADDR_MGMT_INT_MASK = 0x2C, 33 MALIGP2_REG_ADDR_MGMT_INT_STAT = 0x30, 34 MALIGP2_REG_ADDR_MGMT_WRITE_BOUND_LOW = 0x34, 35 MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_ENABLE = 0x3C, 36 MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_ENABLE = 0x40, 37 MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_SRC = 0x44, 38 MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_SRC = 0x48, 39 MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_VALUE = 0x4C, 40 MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_VALUE = 0x50, 41 MALIGP2_REG_ADDR_MGMT_STATUS = 0x68, 42 MALIGP2_REG_ADDR_MGMT_VERSION = 0x6C, 43 MALIGP2_REG_ADDR_MGMT_VSCL_START_ADDR_READ = 0x80, 44 MALIGP2_REG_ADDR_MGMT_PLBCL_START_ADDR_READ = 0x84, 45 MALIGP2_CONTR_AXI_BUS_ERROR_STAT = 0x94, 46 MALIGP2_REGISTER_ADDRESS_SPACE_SIZE = 0x98, 47} maligp_reg_addr_mgmt_addr; 48 49#define MALIGP2_REG_VAL_PERF_CNT_ENABLE 1 50 51/** 52 * Commands to geometry processor. 53 * @see MALIGP2_CTRL_REG_CMD 54 */ 55typedef enum 56{ 57 MALIGP2_REG_VAL_CMD_START_VS = (1<< 0), 58 MALIGP2_REG_VAL_CMD_START_PLBU = (1<< 1), 59 MALIGP2_REG_VAL_CMD_UPDATE_PLBU_ALLOC = (1<< 4), 60 MALIGP2_REG_VAL_CMD_RESET = (1<< 5), 61 MALIGP2_REG_VAL_CMD_FORCE_HANG = (1<< 6), 62 MALIGP2_REG_VAL_CMD_STOP_BUS = (1<< 9), 63#if defined(USING_MALI400) || defined(USING_MALI450) 64 MALI400GP_REG_VAL_CMD_SOFT_RESET = (1<<10), 65#endif 66} mgp_contr_reg_val_cmd; 67 68 69/** @defgroup MALIGP2_IRQ 70 * Interrupt status of geometry processor. 71 * @see MALIGP2_CTRL_REG_INT_RAWSTAT, MALIGP2_REG_ADDR_MGMT_INT_CLEAR, 72 * MALIGP2_REG_ADDR_MGMT_INT_MASK, MALIGP2_REG_ADDR_MGMT_INT_STAT 73 * @{ 74 */ 75#define MALIGP2_REG_VAL_IRQ_VS_END_CMD_LST (1 << 0) 76#define MALIGP2_REG_VAL_IRQ_PLBU_END_CMD_LST (1 << 1) 77#define MALIGP2_REG_VAL_IRQ_PLBU_OUT_OF_MEM (1 << 2) 78#define MALIGP2_REG_VAL_IRQ_VS_SEM_IRQ (1 << 3) 79#define MALIGP2_REG_VAL_IRQ_PLBU_SEM_IRQ (1 << 4) 80#define MALIGP2_REG_VAL_IRQ_HANG (1 << 5) 81#define MALIGP2_REG_VAL_IRQ_FORCE_HANG (1 << 6) 82#define MALIGP2_REG_VAL_IRQ_PERF_CNT_0_LIMIT (1 << 7) 83#define MALIGP2_REG_VAL_IRQ_PERF_CNT_1_LIMIT (1 << 8) 84#define MALIGP2_REG_VAL_IRQ_WRITE_BOUND_ERR (1 << 9) 85#define MALIGP2_REG_VAL_IRQ_SYNC_ERROR (1 << 10) 86#define MALIGP2_REG_VAL_IRQ_AXI_BUS_ERROR (1 << 11) 87#if defined(USING_MALI400) || defined(USING_MALI450) 88#define MALI400GP_REG_VAL_IRQ_AXI_BUS_STOPPED (1 << 12) 89#define MALI400GP_REG_VAL_IRQ_VS_INVALID_CMD (1 << 13) 90#define MALI400GP_REG_VAL_IRQ_PLB_INVALID_CMD (1 << 14) 91#define MALI400GP_REG_VAL_IRQ_RESET_COMPLETED (1 << 19) 92#define MALI400GP_REG_VAL_IRQ_SEMAPHORE_UNDERFLOW (1 << 20) 93#define MALI400GP_REG_VAL_IRQ_SEMAPHORE_OVERFLOW (1 << 21) 94#define MALI400GP_REG_VAL_IRQ_PTR_ARRAY_OUT_OF_BOUNDS (1 << 22) 95#elif !defined USING_MALI200 96#error "No supported mali core defined" 97#endif 98 99/* Mask defining all IRQs in MaliGP2 */ 100#if defined(USING_MALI200) 101#define MALIGP2_REG_VAL_IRQ_MASK_ALL \ 102 (\ 103 MALIGP2_REG_VAL_IRQ_VS_END_CMD_LST | \ 104 MALIGP2_REG_VAL_IRQ_PLBU_END_CMD_LST | \ 105 MALIGP2_REG_VAL_IRQ_PLBU_OUT_OF_MEM | \ 106 MALIGP2_REG_VAL_IRQ_VS_SEM_IRQ | \ 107 MALIGP2_REG_VAL_IRQ_PLBU_SEM_IRQ | \ 108 MALIGP2_REG_VAL_IRQ_HANG | \ 109 MALIGP2_REG_VAL_IRQ_FORCE_HANG | \ 110 MALIGP2_REG_VAL_IRQ_PERF_CNT_0_LIMIT | \ 111 MALIGP2_REG_VAL_IRQ_PERF_CNT_1_LIMIT | \ 112 MALIGP2_REG_VAL_IRQ_WRITE_BOUND_ERR | \ 113 MALIGP2_REG_VAL_IRQ_SYNC_ERROR | \ 114 MALIGP2_REG_VAL_IRQ_AXI_BUS_ERROR) 115#elif defined(USING_MALI400) || defined(USING_MALI450) 116#define MALIGP2_REG_VAL_IRQ_MASK_ALL \ 117 (\ 118 MALIGP2_REG_VAL_IRQ_VS_END_CMD_LST | \ 119 MALIGP2_REG_VAL_IRQ_PLBU_END_CMD_LST | \ 120 MALIGP2_REG_VAL_IRQ_PLBU_OUT_OF_MEM | \ 121 MALIGP2_REG_VAL_IRQ_VS_SEM_IRQ | \ 122 MALIGP2_REG_VAL_IRQ_PLBU_SEM_IRQ | \ 123 MALIGP2_REG_VAL_IRQ_HANG | \ 124 MALIGP2_REG_VAL_IRQ_FORCE_HANG | \ 125 MALIGP2_REG_VAL_IRQ_PERF_CNT_0_LIMIT | \ 126 MALIGP2_REG_VAL_IRQ_PERF_CNT_1_LIMIT | \ 127 MALIGP2_REG_VAL_IRQ_WRITE_BOUND_ERR | \ 128 MALIGP2_REG_VAL_IRQ_SYNC_ERROR | \ 129 MALIGP2_REG_VAL_IRQ_AXI_BUS_ERROR | \ 130 MALI400GP_REG_VAL_IRQ_AXI_BUS_STOPPED | \ 131 MALI400GP_REG_VAL_IRQ_VS_INVALID_CMD | \ 132 MALI400GP_REG_VAL_IRQ_PLB_INVALID_CMD | \ 133 MALI400GP_REG_VAL_IRQ_RESET_COMPLETED | \ 134 MALI400GP_REG_VAL_IRQ_SEMAPHORE_UNDERFLOW | \ 135 MALI400GP_REG_VAL_IRQ_SEMAPHORE_OVERFLOW | \ 136 MALI400GP_REG_VAL_IRQ_PTR_ARRAY_OUT_OF_BOUNDS) 137#else 138#error "No supported mali core defined" 139#endif 140 141/* Mask defining the IRQs in MaliGP2 which we use*/ 142#if defined(USING_MALI200) 143#define MALIGP2_REG_VAL_IRQ_MASK_USED \ 144 (\ 145 MALIGP2_REG_VAL_IRQ_VS_END_CMD_LST | \ 146 MALIGP2_REG_VAL_IRQ_PLBU_END_CMD_LST | \ 147 MALIGP2_REG_VAL_IRQ_PLBU_OUT_OF_MEM | \ 148 MALIGP2_REG_VAL_IRQ_HANG | \ 149 MALIGP2_REG_VAL_IRQ_FORCE_HANG | \ 150 MALIGP2_REG_VAL_IRQ_WRITE_BOUND_ERR | \ 151 MALIGP2_REG_VAL_IRQ_SYNC_ERROR | \ 152 MALIGP2_REG_VAL_IRQ_AXI_BUS_ERROR) 153#elif defined(USING_MALI400) || defined(USING_MALI450) 154#define MALIGP2_REG_VAL_IRQ_MASK_USED \ 155 (\ 156 MALIGP2_REG_VAL_IRQ_VS_END_CMD_LST | \ 157 MALIGP2_REG_VAL_IRQ_PLBU_END_CMD_LST | \ 158 MALIGP2_REG_VAL_IRQ_PLBU_OUT_OF_MEM | \ 159 MALIGP2_REG_VAL_IRQ_HANG | \ 160 MALIGP2_REG_VAL_IRQ_FORCE_HANG | \ 161 MALIGP2_REG_VAL_IRQ_WRITE_BOUND_ERR | \ 162 MALIGP2_REG_VAL_IRQ_SYNC_ERROR | \ 163 MALIGP2_REG_VAL_IRQ_AXI_BUS_ERROR | \ 164 MALI400GP_REG_VAL_IRQ_VS_INVALID_CMD | \ 165 MALI400GP_REG_VAL_IRQ_PLB_INVALID_CMD | \ 166 MALI400GP_REG_VAL_IRQ_SEMAPHORE_UNDERFLOW | \ 167 MALI400GP_REG_VAL_IRQ_SEMAPHORE_OVERFLOW | \ 168 MALI400GP_REG_VAL_IRQ_PTR_ARRAY_OUT_OF_BOUNDS) 169#else 170#error "No supported mali core defined" 171#endif 172 173/* Mask defining non IRQs on MaliGP2*/ 174#define MALIGP2_REG_VAL_IRQ_MASK_NONE 0 175 176/** }@ defgroup MALIGP2_IRQ*/ 177 178/** @defgroup MALIGP2_STATUS 179 * The different Status values to the geometry processor. 180 * @see MALIGP2_CTRL_REG_STATUS 181 * @{ 182 */ 183#define MALIGP2_REG_VAL_STATUS_VS_ACTIVE 0x0002 184#define MALIGP2_REG_VAL_STATUS_BUS_STOPPED 0x0004 185#define MALIGP2_REG_VAL_STATUS_PLBU_ACTIVE 0x0008 186#define MALIGP2_REG_VAL_STATUS_BUS_ERROR 0x0040 187#define MALIGP2_REG_VAL_STATUS_WRITE_BOUND_ERR 0x0100 188/** }@ defgroup MALIGP2_STATUS*/ 189 190#define MALIGP2_REG_VAL_STATUS_MASK_ACTIVE (\ 191 MALIGP2_REG_VAL_STATUS_VS_ACTIVE|\ 192 MALIGP2_REG_VAL_STATUS_PLBU_ACTIVE) 193 194 195#define MALIGP2_REG_VAL_STATUS_MASK_ERROR (\ 196 MALIGP2_REG_VAL_STATUS_BUS_ERROR |\ 197 MALIGP2_REG_VAL_STATUS_WRITE_BOUND_ERR ) 198 199/* This should be in the top 16 bit of the version register of gp.*/ 200#define MALI200_GP_PRODUCT_ID 0xA07 201#define MALI300_GP_PRODUCT_ID 0xC07 202#define MALI400_GP_PRODUCT_ID 0xB07 203#define MALI450_GP_PRODUCT_ID 0xD07 204 205/** 206 * The different sources for instrumented on the geometry processor. 207 * @see MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_SRC 208 */ 209 210enum MALIGP2_cont_reg_perf_cnt_src { 211 MALIGP2_REG_VAL_PERF_CNT1_SRC_NUMBER_OF_VERTICES_PROCESSED = 0x0a, 212}; 213 214#endif