/drivers/gpu/mali/mali/arch-ve-virtex6-m450-8/config.h
C++ Header | 168 lines | 146 code | 8 blank | 14 comment | 0 complexity | a37f0d9e62a5fdec5012162e742bc36a MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
1/* 2 * Copyright (C) 2010, 2012 ARM Limited. All rights reserved. 3 * 4 * This program is free software and is provided to you under the terms of the GNU General Public License version 2 5 * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence. 6 * 7 * A copy of the licence is included with the program, and can also be obtained from Free Software 8 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 9 */ 10 11#ifndef __ARCH_CONFIG_H__ 12#define __ARCH_CONFIG_H__ 13 14/* Configuration for the Versatile Express platform */ 15 16#define MALI_BASE_ADDRESS 0xFC040000 17 18static _mali_osk_resource_t arch_configuration [] = 19{ 20 /* GP cluster */ 21 { 22 .type = MALI400L2, 23 .base = MALI_BASE_ADDRESS + 0x10000, 24 .description = "Mali-450 L2 cache for GP" 25 }, 26 { 27 .type = MALI400GP, 28 .description = "Mali-450 GP", 29 .base = MALI_BASE_ADDRESS, 30 .irq = -1, 31 }, 32 { 33 .type = MMU, 34 .base = MALI_BASE_ADDRESS + 0x3000, 35 .irq = 70, 36 .description = "Mali-450 MMU for GP", 37 }, 38 39 /* PP0-3 cluster */ 40 { 41 .type = MALI400L2, 42 .base = MALI_BASE_ADDRESS + 0x1000, 43 .description = "Mali-450 L2 cache for PP0-3" 44 }, 45 { 46 .type = MALI400PP, 47 .base = MALI_BASE_ADDRESS + 0x8000, 48 .irq = 70, 49 .description = "Mali-450 PP0", 50 }, 51 { 52 .type = MMU, 53 .base = MALI_BASE_ADDRESS + 0x4000, 54 .irq = 70, 55 .description = "Mali-450 MMU for PP0", 56 }, 57 { 58 .type = MALI400PP, 59 .base = MALI_BASE_ADDRESS + 0xA000, 60 .irq = 70, 61 .description = "Mali-450 PP1", 62 }, 63 { 64 .type = MMU, 65 .base = MALI_BASE_ADDRESS + 0x5000, 66 .irq = 70, 67 .description = "Mali-450 MMU for PP1", 68 }, 69 { 70 .type = MALI400PP, 71 .base = MALI_BASE_ADDRESS + 0xC000, 72 .irq = 70, 73 .description = "Mali-450 PP2", 74 }, 75 { 76 .type = MMU, 77 .base = MALI_BASE_ADDRESS + 0x6000, 78 .irq = 70, 79 .description = "Mali-450 MMU for PP2", 80 }, 81 { 82 .type = MALI400PP, 83 .base = MALI_BASE_ADDRESS + 0xE000, 84 .irq = 70, 85 .description = "Mali-450 PP3", 86 }, 87 { 88 .type = MMU, 89 .base = MALI_BASE_ADDRESS + 0x7000, 90 .irq = 70, 91 .description = "Mali-450 MMU for PP3", 92 }, 93 94 /* PP4-7 cluster */ 95 { 96 .type = MALI400L2, 97 .base = MALI_BASE_ADDRESS + 0x11000, 98 .description = "Mali-450 L2 cache for PP4-7" 99 }, 100 { 101 .type = MALI400PP, 102 .base = MALI_BASE_ADDRESS + 0x28000, 103 .irq = 70, 104 .description = "Mali-450 PP4", 105 }, 106 { 107 .type = MMU, 108 .base = MALI_BASE_ADDRESS + 0x1C000, 109 .irq = 70, 110 .description = "Mali-450 MMU for PP4", 111 }, 112 { 113 .type = MALI400PP, 114 .base = MALI_BASE_ADDRESS + 0x2A000, 115 .irq = 70, 116 .description = "Mali-450 PP5", 117 }, 118 { 119 .type = MMU, 120 .base = MALI_BASE_ADDRESS + 0x1D000, 121 .irq = 70, 122 .description = "Mali-450 MMU for PP5", 123 }, 124 { 125 .type = MALI400PP, 126 .base = MALI_BASE_ADDRESS + 0x2C000, 127 .irq = 70, 128 .description = "Mali-450 PP6", 129 }, 130 { 131 .type = MMU, 132 .base = MALI_BASE_ADDRESS + 0x1E000, 133 .irq = 70, 134 .description = "Mali-450 MMU for PP6", 135 }, 136 { 137 .type = MALI400PP, 138 .base = MALI_BASE_ADDRESS + 0x2E000, 139 .irq = 70, 140 .description = "Mali-450 PP7", 141 }, 142 { 143 .type = MMU, 144 .base = MALI_BASE_ADDRESS + 0x1F000, 145 .irq = 70, 146 .description = "Mali-450 MMU for PP7", 147 }, 148 149 /* Memory */ 150 { 151 .type = OS_MEMORY, 152 .description = "Mali OS memory", 153 .cpu_usage_adjust = 0, 154 .alloc_order = 0, /* Highest preference for this memory */ 155 .base = 0x0, 156 .size = 256 * 1024 * 1024, 157 .flags = _MALI_CPU_WRITEABLE | _MALI_CPU_READABLE | _MALI_PP_READABLE | _MALI_PP_WRITEABLE |_MALI_GP_READABLE | _MALI_GP_WRITEABLE 158 }, 159 { 160 .type = MEM_VALIDATION, 161 .description = "Framebuffer", 162 .base = 0xe0000000, 163 .size = 0x01000000, 164 .flags = _MALI_CPU_WRITEABLE | _MALI_CPU_READABLE | _MALI_PP_WRITEABLE | _MALI_PP_READABLE 165 }, 166}; 167 168#endif /* __ARCH_CONFIG_H__ */