/drivers/gpu/mali/mali/arch-ve-virtex6-m450-8/config.h

https://bitbucket.org/ndreys/linux-sunxi · C++ Header · 168 lines · 146 code · 8 blank · 14 comment · 0 complexity · a37f0d9e62a5fdec5012162e742bc36a MD5 · raw file

  1. /*
  2. * Copyright (C) 2010, 2012 ARM Limited. All rights reserved.
  3. *
  4. * This program is free software and is provided to you under the terms of the GNU General Public License version 2
  5. * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
  6. *
  7. * A copy of the licence is included with the program, and can also be obtained from Free Software
  8. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  9. */
  10. #ifndef __ARCH_CONFIG_H__
  11. #define __ARCH_CONFIG_H__
  12. /* Configuration for the Versatile Express platform */
  13. #define MALI_BASE_ADDRESS 0xFC040000
  14. static _mali_osk_resource_t arch_configuration [] =
  15. {
  16. /* GP cluster */
  17. {
  18. .type = MALI400L2,
  19. .base = MALI_BASE_ADDRESS + 0x10000,
  20. .description = "Mali-450 L2 cache for GP"
  21. },
  22. {
  23. .type = MALI400GP,
  24. .description = "Mali-450 GP",
  25. .base = MALI_BASE_ADDRESS,
  26. .irq = -1,
  27. },
  28. {
  29. .type = MMU,
  30. .base = MALI_BASE_ADDRESS + 0x3000,
  31. .irq = 70,
  32. .description = "Mali-450 MMU for GP",
  33. },
  34. /* PP0-3 cluster */
  35. {
  36. .type = MALI400L2,
  37. .base = MALI_BASE_ADDRESS + 0x1000,
  38. .description = "Mali-450 L2 cache for PP0-3"
  39. },
  40. {
  41. .type = MALI400PP,
  42. .base = MALI_BASE_ADDRESS + 0x8000,
  43. .irq = 70,
  44. .description = "Mali-450 PP0",
  45. },
  46. {
  47. .type = MMU,
  48. .base = MALI_BASE_ADDRESS + 0x4000,
  49. .irq = 70,
  50. .description = "Mali-450 MMU for PP0",
  51. },
  52. {
  53. .type = MALI400PP,
  54. .base = MALI_BASE_ADDRESS + 0xA000,
  55. .irq = 70,
  56. .description = "Mali-450 PP1",
  57. },
  58. {
  59. .type = MMU,
  60. .base = MALI_BASE_ADDRESS + 0x5000,
  61. .irq = 70,
  62. .description = "Mali-450 MMU for PP1",
  63. },
  64. {
  65. .type = MALI400PP,
  66. .base = MALI_BASE_ADDRESS + 0xC000,
  67. .irq = 70,
  68. .description = "Mali-450 PP2",
  69. },
  70. {
  71. .type = MMU,
  72. .base = MALI_BASE_ADDRESS + 0x6000,
  73. .irq = 70,
  74. .description = "Mali-450 MMU for PP2",
  75. },
  76. {
  77. .type = MALI400PP,
  78. .base = MALI_BASE_ADDRESS + 0xE000,
  79. .irq = 70,
  80. .description = "Mali-450 PP3",
  81. },
  82. {
  83. .type = MMU,
  84. .base = MALI_BASE_ADDRESS + 0x7000,
  85. .irq = 70,
  86. .description = "Mali-450 MMU for PP3",
  87. },
  88. /* PP4-7 cluster */
  89. {
  90. .type = MALI400L2,
  91. .base = MALI_BASE_ADDRESS + 0x11000,
  92. .description = "Mali-450 L2 cache for PP4-7"
  93. },
  94. {
  95. .type = MALI400PP,
  96. .base = MALI_BASE_ADDRESS + 0x28000,
  97. .irq = 70,
  98. .description = "Mali-450 PP4",
  99. },
  100. {
  101. .type = MMU,
  102. .base = MALI_BASE_ADDRESS + 0x1C000,
  103. .irq = 70,
  104. .description = "Mali-450 MMU for PP4",
  105. },
  106. {
  107. .type = MALI400PP,
  108. .base = MALI_BASE_ADDRESS + 0x2A000,
  109. .irq = 70,
  110. .description = "Mali-450 PP5",
  111. },
  112. {
  113. .type = MMU,
  114. .base = MALI_BASE_ADDRESS + 0x1D000,
  115. .irq = 70,
  116. .description = "Mali-450 MMU for PP5",
  117. },
  118. {
  119. .type = MALI400PP,
  120. .base = MALI_BASE_ADDRESS + 0x2C000,
  121. .irq = 70,
  122. .description = "Mali-450 PP6",
  123. },
  124. {
  125. .type = MMU,
  126. .base = MALI_BASE_ADDRESS + 0x1E000,
  127. .irq = 70,
  128. .description = "Mali-450 MMU for PP6",
  129. },
  130. {
  131. .type = MALI400PP,
  132. .base = MALI_BASE_ADDRESS + 0x2E000,
  133. .irq = 70,
  134. .description = "Mali-450 PP7",
  135. },
  136. {
  137. .type = MMU,
  138. .base = MALI_BASE_ADDRESS + 0x1F000,
  139. .irq = 70,
  140. .description = "Mali-450 MMU for PP7",
  141. },
  142. /* Memory */
  143. {
  144. .type = OS_MEMORY,
  145. .description = "Mali OS memory",
  146. .cpu_usage_adjust = 0,
  147. .alloc_order = 0, /* Highest preference for this memory */
  148. .base = 0x0,
  149. .size = 256 * 1024 * 1024,
  150. .flags = _MALI_CPU_WRITEABLE | _MALI_CPU_READABLE | _MALI_PP_READABLE | _MALI_PP_WRITEABLE |_MALI_GP_READABLE | _MALI_GP_WRITEABLE
  151. },
  152. {
  153. .type = MEM_VALIDATION,
  154. .description = "Framebuffer",
  155. .base = 0xe0000000,
  156. .size = 0x01000000,
  157. .flags = _MALI_CPU_WRITEABLE | _MALI_CPU_READABLE | _MALI_PP_WRITEABLE | _MALI_PP_READABLE
  158. },
  159. };
  160. #endif /* __ARCH_CONFIG_H__ */