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/drivers/gpu/drm/radeon/atombios.h

https://bitbucket.org/ndreys/linux-sunxi
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Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0

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   1/*
   2 * Copyright 2006-2007 Advanced Micro Devices, Inc.  
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 */
  22
  23
  24/****************************************************************************/	
  25/*Portion I: Definitions  shared between VBIOS and Driver                   */
  26/****************************************************************************/
  27
  28
  29#ifndef _ATOMBIOS_H
  30#define _ATOMBIOS_H
  31
  32#define ATOM_VERSION_MAJOR                   0x00020000
  33#define ATOM_VERSION_MINOR                   0x00000002
  34
  35#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR)
  36
  37/* Endianness should be specified before inclusion,
  38 * default to little endian
  39 */
  40#ifndef ATOM_BIG_ENDIAN
  41#error Endian not specified
  42#endif
  43
  44#ifdef _H2INC
  45  #ifndef ULONG 
  46    typedef unsigned long ULONG;
  47  #endif
  48
  49  #ifndef UCHAR
  50    typedef unsigned char UCHAR;
  51  #endif
  52
  53  #ifndef USHORT 
  54    typedef unsigned short USHORT;
  55  #endif
  56#endif
  57      
  58#define ATOM_DAC_A            0 
  59#define ATOM_DAC_B            1
  60#define ATOM_EXT_DAC          2
  61
  62#define ATOM_CRTC1            0
  63#define ATOM_CRTC2            1
  64#define ATOM_CRTC3            2
  65#define ATOM_CRTC4            3
  66#define ATOM_CRTC5            4
  67#define ATOM_CRTC6            5
  68#define ATOM_CRTC_INVALID     0xFF
  69
  70#define ATOM_DIGA             0
  71#define ATOM_DIGB             1
  72
  73#define ATOM_PPLL1            0
  74#define ATOM_PPLL2            1
  75#define ATOM_DCPLL            2
  76#define ATOM_PPLL0            2
  77#define ATOM_EXT_PLL1         8
  78#define ATOM_EXT_PLL2         9
  79#define ATOM_EXT_CLOCK        10
  80#define ATOM_PPLL_INVALID     0xFF
  81
  82#define ENCODER_REFCLK_SRC_P1PLL       0       
  83#define ENCODER_REFCLK_SRC_P2PLL       1
  84#define ENCODER_REFCLK_SRC_DCPLL       2
  85#define ENCODER_REFCLK_SRC_EXTCLK      3
  86#define ENCODER_REFCLK_SRC_INVALID     0xFF
  87
  88#define ATOM_SCALER1          0
  89#define ATOM_SCALER2          1
  90
  91#define ATOM_SCALER_DISABLE   0   
  92#define ATOM_SCALER_CENTER    1   
  93#define ATOM_SCALER_EXPANSION 2   
  94#define ATOM_SCALER_MULTI_EX  3   
  95
  96#define ATOM_DISABLE          0
  97#define ATOM_ENABLE           1
  98#define ATOM_LCD_BLOFF                          (ATOM_DISABLE+2)
  99#define ATOM_LCD_BLON                           (ATOM_ENABLE+2)
 100#define ATOM_LCD_BL_BRIGHTNESS_CONTROL          (ATOM_ENABLE+3)
 101#define ATOM_LCD_SELFTEST_START									(ATOM_DISABLE+5)
 102#define ATOM_LCD_SELFTEST_STOP									(ATOM_ENABLE+5)
 103#define ATOM_ENCODER_INIT			                  (ATOM_DISABLE+7)
 104#define ATOM_GET_STATUS                         (ATOM_DISABLE+8)
 105
 106#define ATOM_BLANKING         1
 107#define ATOM_BLANKING_OFF     0
 108
 109#define ATOM_CURSOR1          0
 110#define ATOM_CURSOR2          1
 111
 112#define ATOM_ICON1            0
 113#define ATOM_ICON2            1
 114
 115#define ATOM_CRT1             0
 116#define ATOM_CRT2             1
 117
 118#define ATOM_TV_NTSC          1
 119#define ATOM_TV_NTSCJ         2
 120#define ATOM_TV_PAL           3
 121#define ATOM_TV_PALM          4
 122#define ATOM_TV_PALCN         5
 123#define ATOM_TV_PALN          6
 124#define ATOM_TV_PAL60         7
 125#define ATOM_TV_SECAM         8
 126#define ATOM_TV_CV            16
 127
 128#define ATOM_DAC1_PS2         1
 129#define ATOM_DAC1_CV          2
 130#define ATOM_DAC1_NTSC        3
 131#define ATOM_DAC1_PAL         4
 132
 133#define ATOM_DAC2_PS2         ATOM_DAC1_PS2
 134#define ATOM_DAC2_CV          ATOM_DAC1_CV
 135#define ATOM_DAC2_NTSC        ATOM_DAC1_NTSC
 136#define ATOM_DAC2_PAL         ATOM_DAC1_PAL
 137 
 138#define ATOM_PM_ON            0
 139#define ATOM_PM_STANDBY       1
 140#define ATOM_PM_SUSPEND       2
 141#define ATOM_PM_OFF           3
 142
 143/* Bit0:{=0:single, =1:dual},
 144   Bit1 {=0:666RGB, =1:888RGB},
 145   Bit2:3:{Grey level}
 146   Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/
 147
 148#define ATOM_PANEL_MISC_DUAL               0x00000001
 149#define ATOM_PANEL_MISC_888RGB             0x00000002
 150#define ATOM_PANEL_MISC_GREY_LEVEL         0x0000000C
 151#define ATOM_PANEL_MISC_FPDI               0x00000010
 152#define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT   2
 153#define ATOM_PANEL_MISC_SPATIAL            0x00000020
 154#define ATOM_PANEL_MISC_TEMPORAL           0x00000040
 155#define ATOM_PANEL_MISC_API_ENABLED        0x00000080
 156
 157
 158#define MEMTYPE_DDR1              "DDR1"
 159#define MEMTYPE_DDR2              "DDR2"
 160#define MEMTYPE_DDR3              "DDR3"
 161#define MEMTYPE_DDR4              "DDR4"
 162
 163#define ASIC_BUS_TYPE_PCI         "PCI"
 164#define ASIC_BUS_TYPE_AGP         "AGP"
 165#define ASIC_BUS_TYPE_PCIE        "PCI_EXPRESS"
 166
 167/* Maximum size of that FireGL flag string */
 168
 169#define ATOM_FIREGL_FLAG_STRING     "FGL"             //Flag used to enable FireGL Support
 170#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING  3        //sizeof( ATOM_FIREGL_FLAG_STRING )
 171
 172#define ATOM_FAKE_DESKTOP_STRING    "DSK"             //Flag used to enable mobile ASIC on Desktop
 173#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING  ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 
 174
 175#define ATOM_M54T_FLAG_STRING       "M54T"            //Flag used to enable M54T Support
 176#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING    4        //sizeof( ATOM_M54T_FLAG_STRING )
 177
 178#define HW_ASSISTED_I2C_STATUS_FAILURE          2
 179#define HW_ASSISTED_I2C_STATUS_SUCCESS          1
 180
 181#pragma pack(1)                                       /* BIOS data must use byte aligment */
 182
 183/*  Define offset to location of ROM header. */
 184
 185#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER		0x00000048L
 186#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE				    0x00000002L
 187
 188#define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE    0x94
 189#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE   20    /* including the terminator 0x0! */
 190#define	OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER		0x002f
 191#define	OFFSET_TO_GET_ATOMBIOS_STRINGS_START		0x006e
 192
 193/* Common header for all ROM Data tables.
 194  Every table pointed  _ATOM_MASTER_DATA_TABLE has this common header. 
 195  And the pointer actually points to this header. */
 196
 197typedef struct _ATOM_COMMON_TABLE_HEADER
 198{
 199  USHORT usStructureSize;
 200  UCHAR  ucTableFormatRevision;   /*Change it when the Parser is not backward compatible */
 201  UCHAR  ucTableContentRevision;  /*Change it only when the table needs to change but the firmware */
 202                                  /*Image can't be updated, while Driver needs to carry the new table! */
 203}ATOM_COMMON_TABLE_HEADER;
 204
 205/****************************************************************************/	
 206// Structure stores the ROM header.
 207/****************************************************************************/	
 208typedef struct _ATOM_ROM_HEADER
 209{
 210  ATOM_COMMON_TABLE_HEADER		sHeader;
 211  UCHAR	 uaFirmWareSignature[4];    /*Signature to distinguish between Atombios and non-atombios, 
 212                                      atombios should init it as "ATOM", don't change the position */
 213  USHORT usBiosRuntimeSegmentAddress;
 214  USHORT usProtectedModeInfoOffset;
 215  USHORT usConfigFilenameOffset;
 216  USHORT usCRC_BlockOffset;
 217  USHORT usBIOS_BootupMessageOffset;
 218  USHORT usInt10Offset;
 219  USHORT usPciBusDevInitCode;
 220  USHORT usIoBaseAddress;
 221  USHORT usSubsystemVendorID;
 222  USHORT usSubsystemID;
 223  USHORT usPCI_InfoOffset; 
 224  USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */
 225  USHORT usMasterDataTableOffset;   /*Offset for SW to get all data table offsets, Don't change the position */
 226  UCHAR  ucExtendedFunctionCode;
 227  UCHAR  ucReserved;
 228}ATOM_ROM_HEADER;
 229
 230/*==============================Command Table Portion==================================== */
 231
 232#ifdef	UEFI_BUILD
 233	#define	UTEMP	USHORT
 234	#define	USHORT	void*
 235#endif
 236
 237/****************************************************************************/	
 238// Structures used in Command.mtb 
 239/****************************************************************************/	
 240typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
 241  USHORT ASIC_Init;                              //Function Table, used by various SW components,latest version 1.1
 242  USHORT GetDisplaySurfaceSize;                  //Atomic Table,  Used by Bios when enabling HW ICON
 243  USHORT ASIC_RegistersInit;                     //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
 244  USHORT VRAM_BlockVenderDetection;              //Atomic Table,  used only by Bios
 245  USHORT DIGxEncoderControl;										 //Only used by Bios
 246  USHORT MemoryControllerInit;                   //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
 247  USHORT EnableCRTCMemReq;                       //Function Table,directly used by various SW components,latest version 2.1
 248  USHORT MemoryParamAdjust; 										 //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock if needed
 249  USHORT DVOEncoderControl;                      //Function Table,directly used by various SW components,latest version 1.2
 250  USHORT GPIOPinControl;												 //Atomic Table,  only used by Bios
 251  USHORT SetEngineClock;                         //Function Table,directly used by various SW components,latest version 1.1
 252  USHORT SetMemoryClock;                         //Function Table,directly used by various SW components,latest version 1.1
 253  USHORT SetPixelClock;                          //Function Table,directly used by various SW components,latest version 1.2  
 254  USHORT DynamicClockGating;                     //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
 255  USHORT ResetMemoryDLL;                         //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
 256  USHORT ResetMemoryDevice;                      //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
 257  USHORT MemoryPLLInit;
 258  USHORT AdjustDisplayPll;												//only used by Bios
 259  USHORT AdjustMemoryController;                 //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock                
 260  USHORT EnableASIC_StaticPwrMgt;                //Atomic Table,  only used by Bios
 261  USHORT ASIC_StaticPwrMgtStatusChange;          //Obsolete ,     only used by Bios   
 262  USHORT DAC_LoadDetection;                      //Atomic Table,  directly used by various SW components,latest version 1.2  
 263  USHORT LVTMAEncoderControl;                    //Atomic Table,directly used by various SW components,latest version 1.3
 264  USHORT LCD1OutputControl;                      //Atomic Table,  directly used by various SW components,latest version 1.1 
 265  USHORT DAC1EncoderControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1  
 266  USHORT DAC2EncoderControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1 
 267  USHORT DVOOutputControl;                       //Atomic Table,  directly used by various SW components,latest version 1.1 
 268  USHORT CV1OutputControl;                       //Atomic Table,  Atomic Table,  Obsolete from Ry6xx, use DAC2 Output instead 
 269  USHORT GetConditionalGoldenSetting;            //only used by Bios
 270  USHORT TVEncoderControl;                       //Function Table,directly used by various SW components,latest version 1.1
 271  USHORT TMDSAEncoderControl;                    //Atomic Table,  directly used by various SW components,latest version 1.3
 272  USHORT LVDSEncoderControl;                     //Atomic Table,  directly used by various SW components,latest version 1.3
 273  USHORT TV1OutputControl;                       //Atomic Table,  Obsolete from Ry6xx, use DAC2 Output instead
 274  USHORT EnableScaler;                           //Atomic Table,  used only by Bios
 275  USHORT BlankCRTC;                              //Atomic Table,  directly used by various SW components,latest version 1.1 
 276  USHORT EnableCRTC;                             //Atomic Table,  directly used by various SW components,latest version 1.1 
 277  USHORT GetPixelClock;                          //Atomic Table,  directly used by various SW components,latest version 1.1 
 278  USHORT EnableVGA_Render;                       //Function Table,directly used by various SW components,latest version 1.1
 279  USHORT GetSCLKOverMCLKRatio;                   //Atomic Table,  only used by Bios
 280  USHORT SetCRTC_Timing;                         //Atomic Table,  directly used by various SW components,latest version 1.1
 281  USHORT SetCRTC_OverScan;                       //Atomic Table,  used by various SW components,latest version 1.1 
 282  USHORT SetCRTC_Replication;                    //Atomic Table,  used only by Bios
 283  USHORT SelectCRTC_Source;                      //Atomic Table,  directly used by various SW components,latest version 1.1 
 284  USHORT EnableGraphSurfaces;                    //Atomic Table,  used only by Bios
 285  USHORT UpdateCRTC_DoubleBufferRegisters;
 286  USHORT LUT_AutoFill;                           //Atomic Table,  only used by Bios
 287  USHORT EnableHW_IconCursor;                    //Atomic Table,  only used by Bios
 288  USHORT GetMemoryClock;                         //Atomic Table,  directly used by various SW components,latest version 1.1 
 289  USHORT GetEngineClock;                         //Atomic Table,  directly used by various SW components,latest version 1.1 
 290  USHORT SetCRTC_UsingDTDTiming;                 //Atomic Table,  directly used by various SW components,latest version 1.1
 291  USHORT ExternalEncoderControl;                 //Atomic Table,  directly used by various SW components,latest version 2.1
 292  USHORT LVTMAOutputControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
 293  USHORT VRAM_BlockDetectionByStrap;             //Atomic Table,  used only by Bios
 294  USHORT MemoryCleanUp;                          //Atomic Table,  only used by Bios    
 295  USHORT ProcessI2cChannelTransaction;           //Function Table,only used by Bios
 296  USHORT WriteOneByteToHWAssistedI2C;            //Function Table,indirectly used by various SW components 
 297  USHORT ReadHWAssistedI2CStatus;                //Atomic Table,  indirectly used by various SW components
 298  USHORT SpeedFanControl;                        //Function Table,indirectly used by various SW components,called from ASIC_Init
 299  USHORT PowerConnectorDetection;                //Atomic Table,  directly used by various SW components,latest version 1.1
 300  USHORT MC_Synchronization;                     //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
 301  USHORT ComputeMemoryEnginePLL;                 //Atomic Table,  indirectly used by various SW components,called from SetMemory/EngineClock
 302  USHORT MemoryRefreshConversion;                //Atomic Table,  indirectly used by various SW components,called from SetMemory or SetEngineClock
 303  USHORT VRAM_GetCurrentInfoBlock;               //Atomic Table,  used only by Bios
 304  USHORT DynamicMemorySettings;                  //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
 305  USHORT MemoryTraining;                         //Atomic Table,  used only by Bios
 306  USHORT EnableSpreadSpectrumOnPPLL;             //Atomic Table,  directly used by various SW components,latest version 1.2
 307  USHORT TMDSAOutputControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
 308  USHORT SetVoltage;                             //Function Table,directly and/or indirectly used by various SW components,latest version 1.1
 309  USHORT DAC1OutputControl;                      //Atomic Table,  directly used by various SW components,latest version 1.1
 310  USHORT DAC2OutputControl;                      //Atomic Table,  directly used by various SW components,latest version 1.1
 311  USHORT SetupHWAssistedI2CStatus;               //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C"
 312  USHORT ClockSource;                            //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
 313  USHORT MemoryDeviceInit;                       //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
 314  USHORT EnableYUV;                              //Atomic Table,  indirectly used by various SW components,called from EnableVGARender
 315  USHORT DIG1EncoderControl;                     //Atomic Table,directly used by various SW components,latest version 1.1
 316  USHORT DIG2EncoderControl;                     //Atomic Table,directly used by various SW components,latest version 1.1
 317  USHORT DIG1TransmitterControl;                 //Atomic Table,directly used by various SW components,latest version 1.1
 318  USHORT DIG2TransmitterControl;	               //Atomic Table,directly used by various SW components,latest version 1.1 
 319  USHORT ProcessAuxChannelTransaction;					 //Function Table,only used by Bios
 320  USHORT DPEncoderService;											 //Function Table,only used by Bios
 321}ATOM_MASTER_LIST_OF_COMMAND_TABLES;   
 322
 323// For backward compatible 
 324#define ReadEDIDFromHWAssistedI2C                ProcessI2cChannelTransaction
 325#define UNIPHYTransmitterControl						     DIG1TransmitterControl
 326#define LVTMATransmitterControl							     DIG2TransmitterControl
 327#define SetCRTC_DPM_State                        GetConditionalGoldenSetting
 328#define SetUniphyInstance                        ASIC_StaticPwrMgtStatusChange
 329#define HPDInterruptService                      ReadHWAssistedI2CStatus
 330#define EnableVGA_Access                         GetSCLKOverMCLKRatio
 331#define GetDispObjectInfo                        EnableYUV 
 332
 333typedef struct _ATOM_MASTER_COMMAND_TABLE
 334{
 335  ATOM_COMMON_TABLE_HEADER           sHeader;
 336  ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables;
 337}ATOM_MASTER_COMMAND_TABLE;
 338
 339/****************************************************************************/	
 340// Structures used in every command table
 341/****************************************************************************/	
 342typedef struct _ATOM_TABLE_ATTRIBUTE
 343{
 344#if ATOM_BIG_ENDIAN
 345  USHORT  UpdatedByUtility:1;         //[15]=Table updated by utility flag
 346  USHORT  PS_SizeInBytes:7;           //[14:8]=Size of parameter space in Bytes (multiple of a dword), 
 347  USHORT  WS_SizeInBytes:8;           //[7:0]=Size of workspace in Bytes (in multiple of a dword), 
 348#else
 349  USHORT  WS_SizeInBytes:8;           //[7:0]=Size of workspace in Bytes (in multiple of a dword), 
 350  USHORT  PS_SizeInBytes:7;           //[14:8]=Size of parameter space in Bytes (multiple of a dword), 
 351  USHORT  UpdatedByUtility:1;         //[15]=Table updated by utility flag
 352#endif
 353}ATOM_TABLE_ATTRIBUTE;
 354
 355typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS
 356{
 357  ATOM_TABLE_ATTRIBUTE sbfAccess;
 358  USHORT               susAccess;
 359}ATOM_TABLE_ATTRIBUTE_ACCESS;
 360
 361/****************************************************************************/	
 362// Common header for all command tables.
 363// Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. 
 364// And the pointer actually points to this header.
 365/****************************************************************************/	
 366typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER
 367{
 368  ATOM_COMMON_TABLE_HEADER CommonHeader;
 369  ATOM_TABLE_ATTRIBUTE     TableAttribute;	
 370}ATOM_COMMON_ROM_COMMAND_TABLE_HEADER;
 371
 372/****************************************************************************/	
 373// Structures used by ComputeMemoryEnginePLLTable
 374/****************************************************************************/	
 375#define COMPUTE_MEMORY_PLL_PARAM        1
 376#define COMPUTE_ENGINE_PLL_PARAM        2
 377#define ADJUST_MC_SETTING_PARAM         3
 378
 379/****************************************************************************/	
 380// Structures used by AdjustMemoryControllerTable
 381/****************************************************************************/	
 382typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ
 383{
 384#if ATOM_BIG_ENDIAN
 385  ULONG ulPointerReturnFlag:1;      // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 
 386  ULONG ulMemoryModuleNumber:7;     // BYTE_3[6:0]
 387  ULONG ulClockFreq:24;
 388#else
 389  ULONG ulClockFreq:24;
 390  ULONG ulMemoryModuleNumber:7;     // BYTE_3[6:0]
 391  ULONG ulPointerReturnFlag:1;      // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 
 392#endif
 393}ATOM_ADJUST_MEMORY_CLOCK_FREQ;
 394#define POINTER_RETURN_FLAG             0x80
 395
 396typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
 397{
 398  ULONG   ulClock;        //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div
 399  UCHAR   ucAction;       //0:reserved //1:Memory //2:Engine  
 400  UCHAR   ucReserved;     //may expand to return larger Fbdiv later
 401  UCHAR   ucFbDiv;        //return value
 402  UCHAR   ucPostDiv;      //return value
 403}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS;
 404
 405typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2
 406{
 407  ULONG   ulClock;        //When return, [23:0] return real clock 
 408  UCHAR   ucAction;       //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register
 409  USHORT  usFbDiv;		    //return Feedback value to be written to register
 410  UCHAR   ucPostDiv;      //return post div to be written to register
 411}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2;
 412#define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION   COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
 413
 414
 415#define SET_CLOCK_FREQ_MASK                     0x00FFFFFF  //Clock change tables only take bit [23:0] as the requested clock value
 416#define USE_NON_BUS_CLOCK_MASK                  0x01000000  //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
 417#define USE_MEMORY_SELF_REFRESH_MASK            0x02000000	//Only applicable to memory clock change, when set, using memory self refresh during clock transition
 418#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE   0x04000000  //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
 419#define FIRST_TIME_CHANGE_CLOCK									0x08000000	//Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
 420#define SKIP_SW_PROGRAM_PLL											0x10000000	//Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
 421#define USE_SS_ENABLED_PIXEL_CLOCK  USE_NON_BUS_CLOCK_MASK
 422
 423#define b3USE_NON_BUS_CLOCK_MASK                  0x01       //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
 424#define b3USE_MEMORY_SELF_REFRESH                 0x02	     //Only applicable to memory clock change, when set, using memory self refresh during clock transition
 425#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE   0x04       //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
 426#define b3FIRST_TIME_CHANGE_CLOCK									0x08       //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
 427#define b3SKIP_SW_PROGRAM_PLL											0x10			 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
 428
 429typedef struct _ATOM_COMPUTE_CLOCK_FREQ
 430{
 431#if ATOM_BIG_ENDIAN
 432  ULONG ulComputeClockFlag:8;                 // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
 433  ULONG ulClockFreq:24;                       // in unit of 10kHz
 434#else
 435  ULONG ulClockFreq:24;                       // in unit of 10kHz
 436  ULONG ulComputeClockFlag:8;                 // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
 437#endif
 438}ATOM_COMPUTE_CLOCK_FREQ;
 439
 440typedef struct _ATOM_S_MPLL_FB_DIVIDER
 441{
 442  USHORT usFbDivFrac;  
 443  USHORT usFbDiv;  
 444}ATOM_S_MPLL_FB_DIVIDER;
 445
 446typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3
 447{
 448  union
 449  {
 450    ATOM_COMPUTE_CLOCK_FREQ  ulClock;         //Input Parameter
 451    ATOM_S_MPLL_FB_DIVIDER   ulFbDiv;         //Output Parameter
 452  };
 453  UCHAR   ucRefDiv;                           //Output Parameter      
 454  UCHAR   ucPostDiv;                          //Output Parameter      
 455  UCHAR   ucCntlFlag;                         //Output Parameter      
 456  UCHAR   ucReserved;
 457}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3;
 458
 459// ucCntlFlag
 460#define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN          1
 461#define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE            2
 462#define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE         4
 463#define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9						8
 464
 465
 466// V4 are only used for APU which PLL outside GPU
 467typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4
 468{
 469#if ATOM_BIG_ENDIAN
 470  ULONG  ucPostDiv;          //return parameter: post divider which is used to program to register directly
 471  ULONG  ulClock:24;         //Input= target clock, output = actual clock 
 472#else
 473  ULONG  ulClock:24;         //Input= target clock, output = actual clock 
 474  ULONG  ucPostDiv;          //return parameter: post divider which is used to program to register directly
 475#endif
 476}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4;
 477
 478typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5
 479{
 480  union
 481  {
 482    ATOM_COMPUTE_CLOCK_FREQ  ulClock;         //Input Parameter
 483    ATOM_S_MPLL_FB_DIVIDER   ulFbDiv;         //Output Parameter
 484  };
 485  UCHAR   ucRefDiv;                           //Output Parameter      
 486  UCHAR   ucPostDiv;                          //Output Parameter      
 487  union
 488  {
 489    UCHAR   ucCntlFlag;                       //Output Flags
 490    UCHAR   ucInputFlag;                      //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode
 491  };
 492  UCHAR   ucReserved;                       
 493}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5;
 494
 495// ucInputFlag
 496#define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN  1   // 1-StrobeMode, 0-PerformanceMode
 497
 498typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER
 499{
 500  ATOM_COMPUTE_CLOCK_FREQ ulClock;
 501  ULONG ulReserved[2];
 502}DYNAMICE_MEMORY_SETTINGS_PARAMETER;
 503
 504typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER
 505{
 506  ATOM_COMPUTE_CLOCK_FREQ ulClock;
 507  ULONG ulMemoryClock;
 508  ULONG ulReserved;
 509}DYNAMICE_ENGINE_SETTINGS_PARAMETER;
 510
 511/****************************************************************************/	
 512// Structures used by SetEngineClockTable
 513/****************************************************************************/	
 514typedef struct _SET_ENGINE_CLOCK_PARAMETERS
 515{
 516  ULONG ulTargetEngineClock;          //In 10Khz unit
 517}SET_ENGINE_CLOCK_PARAMETERS;
 518
 519typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION
 520{
 521  ULONG ulTargetEngineClock;          //In 10Khz unit
 522  COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
 523}SET_ENGINE_CLOCK_PS_ALLOCATION;
 524
 525/****************************************************************************/	
 526// Structures used by SetMemoryClockTable
 527/****************************************************************************/	
 528typedef struct _SET_MEMORY_CLOCK_PARAMETERS
 529{
 530  ULONG ulTargetMemoryClock;          //In 10Khz unit
 531}SET_MEMORY_CLOCK_PARAMETERS;
 532
 533typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION
 534{
 535  ULONG ulTargetMemoryClock;          //In 10Khz unit
 536  COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
 537}SET_MEMORY_CLOCK_PS_ALLOCATION;
 538
 539/****************************************************************************/	
 540// Structures used by ASIC_Init.ctb
 541/****************************************************************************/	
 542typedef struct _ASIC_INIT_PARAMETERS
 543{
 544  ULONG ulDefaultEngineClock;         //In 10Khz unit
 545  ULONG ulDefaultMemoryClock;         //In 10Khz unit
 546}ASIC_INIT_PARAMETERS;
 547
 548typedef struct _ASIC_INIT_PS_ALLOCATION
 549{
 550  ASIC_INIT_PARAMETERS sASICInitClocks;
 551  SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure
 552}ASIC_INIT_PS_ALLOCATION;
 553
 554/****************************************************************************/	
 555// Structure used by DynamicClockGatingTable.ctb
 556/****************************************************************************/	
 557typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS 
 558{
 559  UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
 560  UCHAR ucPadding[3];
 561}DYNAMIC_CLOCK_GATING_PARAMETERS;
 562#define  DYNAMIC_CLOCK_GATING_PS_ALLOCATION  DYNAMIC_CLOCK_GATING_PARAMETERS
 563
 564/****************************************************************************/	
 565// Structure used by EnableASIC_StaticPwrMgtTable.ctb
 566/****************************************************************************/	
 567typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
 568{
 569  UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
 570  UCHAR ucPadding[3];
 571}ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS;
 572#define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION  ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
 573
 574/****************************************************************************/	
 575// Structures used by DAC_LoadDetectionTable.ctb
 576/****************************************************************************/	
 577typedef struct _DAC_LOAD_DETECTION_PARAMETERS
 578{
 579  USHORT usDeviceID;                  //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT}
 580  UCHAR  ucDacType;                   //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC}
 581  UCHAR  ucMisc;											//Valid only when table revision =1.3 and above
 582}DAC_LOAD_DETECTION_PARAMETERS;
 583
 584// DAC_LOAD_DETECTION_PARAMETERS.ucMisc
 585#define DAC_LOAD_MISC_YPrPb						0x01
 586
 587typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION
 588{
 589  DAC_LOAD_DETECTION_PARAMETERS            sDacload;
 590  ULONG                                    Reserved[2];// Don't set this one, allocation for EXT DAC
 591}DAC_LOAD_DETECTION_PS_ALLOCATION;
 592
 593/****************************************************************************/	
 594// Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb
 595/****************************************************************************/	
 596typedef struct _DAC_ENCODER_CONTROL_PARAMETERS 
 597{
 598  USHORT usPixelClock;                // in 10KHz; for bios convenient
 599  UCHAR  ucDacStandard;               // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0)
 600  UCHAR  ucAction;                    // 0: turn off encoder
 601                                      // 1: setup and turn on encoder
 602                                      // 7: ATOM_ENCODER_INIT Initialize DAC
 603}DAC_ENCODER_CONTROL_PARAMETERS;
 604
 605#define DAC_ENCODER_CONTROL_PS_ALLOCATION  DAC_ENCODER_CONTROL_PARAMETERS
 606
 607/****************************************************************************/	
 608// Structures used by DIG1EncoderControlTable
 609//                    DIG2EncoderControlTable
 610//                    ExternalEncoderControlTable
 611/****************************************************************************/	
 612typedef struct _DIG_ENCODER_CONTROL_PARAMETERS
 613{
 614  USHORT usPixelClock;		// in 10KHz; for bios convenient
 615  UCHAR  ucConfig;		  
 616                            // [2] Link Select:
 617                            // =0: PHY linkA if bfLane<3
 618                            // =1: PHY linkB if bfLanes<3
 619                            // =0: PHY linkA+B if bfLanes=3
 620                            // [3] Transmitter Sel
 621                            // =0: UNIPHY or PCIEPHY
 622                            // =1: LVTMA 					
 623  UCHAR ucAction;           // =0: turn off encoder					
 624                            // =1: turn on encoder			
 625  UCHAR ucEncoderMode;
 626                            // =0: DP   encoder      
 627                            // =1: LVDS encoder          
 628                            // =2: DVI  encoder  
 629                            // =3: HDMI encoder
 630                            // =4: SDVO encoder
 631  UCHAR ucLaneNum;          // how many lanes to enable
 632  UCHAR ucReserved[2];
 633}DIG_ENCODER_CONTROL_PARAMETERS;
 634#define DIG_ENCODER_CONTROL_PS_ALLOCATION			  DIG_ENCODER_CONTROL_PARAMETERS
 635#define EXTERNAL_ENCODER_CONTROL_PARAMETER			DIG_ENCODER_CONTROL_PARAMETERS
 636
 637//ucConfig
 638#define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK				0x01
 639#define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ		0x00
 640#define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ		0x01
 641#define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ		0x02
 642#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK				  0x04
 643#define ATOM_ENCODER_CONFIG_LINKA								  0x00
 644#define ATOM_ENCODER_CONFIG_LINKB								  0x04
 645#define ATOM_ENCODER_CONFIG_LINKA_B							  ATOM_TRANSMITTER_CONFIG_LINKA
 646#define ATOM_ENCODER_CONFIG_LINKB_A							  ATOM_ENCODER_CONFIG_LINKB
 647#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK	0x08
 648#define ATOM_ENCODER_CONFIG_UNIPHY							  0x00
 649#define ATOM_ENCODER_CONFIG_LVTMA								  0x08
 650#define ATOM_ENCODER_CONFIG_TRANSMITTER1				  0x00
 651#define ATOM_ENCODER_CONFIG_TRANSMITTER2				  0x08
 652#define ATOM_ENCODER_CONFIG_DIGB								  0x80			// VBIOS Internal use, outside SW should set this bit=0
 653// ucAction
 654// ATOM_ENABLE:  Enable Encoder
 655// ATOM_DISABLE: Disable Encoder
 656
 657//ucEncoderMode
 658#define ATOM_ENCODER_MODE_DP											0
 659#define ATOM_ENCODER_MODE_LVDS										1
 660#define ATOM_ENCODER_MODE_DVI											2
 661#define ATOM_ENCODER_MODE_HDMI										3
 662#define ATOM_ENCODER_MODE_SDVO										4
 663#define ATOM_ENCODER_MODE_DP_AUDIO                5
 664#define ATOM_ENCODER_MODE_TV											13
 665#define ATOM_ENCODER_MODE_CV											14
 666#define ATOM_ENCODER_MODE_CRT											15
 667#define ATOM_ENCODER_MODE_DVO											16
 668#define ATOM_ENCODER_MODE_DP_SST                  ATOM_ENCODER_MODE_DP    // For DP1.2
 669#define ATOM_ENCODER_MODE_DP_MST                  5                       // For DP1.2
 670
 671typedef struct _ATOM_DIG_ENCODER_CONFIG_V2
 672{
 673#if ATOM_BIG_ENDIAN
 674    UCHAR ucReserved1:2;
 675    UCHAR ucTransmitterSel:2;     // =0: UniphyAB, =1: UniphyCD  =2: UniphyEF
 676    UCHAR ucLinkSel:1;            // =0: linkA/C/E =1: linkB/D/F
 677    UCHAR ucReserved:1;
 678    UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
 679#else
 680    UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
 681    UCHAR ucReserved:1;
 682    UCHAR ucLinkSel:1;            // =0: linkA/C/E =1: linkB/D/F
 683    UCHAR ucTransmitterSel:2;     // =0: UniphyAB, =1: UniphyCD  =2: UniphyEF
 684    UCHAR ucReserved1:2;
 685#endif
 686}ATOM_DIG_ENCODER_CONFIG_V2;
 687
 688
 689typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2
 690{
 691  USHORT usPixelClock;      // in 10KHz; for bios convenient
 692  ATOM_DIG_ENCODER_CONFIG_V2 acConfig;
 693  UCHAR ucAction;                                       
 694  UCHAR ucEncoderMode;
 695                            // =0: DP   encoder      
 696                            // =1: LVDS encoder          
 697                            // =2: DVI  encoder  
 698                            // =3: HDMI encoder
 699                            // =4: SDVO encoder
 700  UCHAR ucLaneNum;          // how many lanes to enable
 701  UCHAR ucStatus;           // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS
 702  UCHAR ucReserved;
 703}DIG_ENCODER_CONTROL_PARAMETERS_V2;
 704
 705//ucConfig
 706#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK				0x01
 707#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ		  0x00
 708#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ		  0x01
 709#define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK				  0x04
 710#define ATOM_ENCODER_CONFIG_V2_LINKA								  0x00
 711#define ATOM_ENCODER_CONFIG_V2_LINKB								  0x04
 712#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK	  0x18
 713#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1				    0x00
 714#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2				    0x08
 715#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3				    0x10
 716
 717// ucAction:
 718// ATOM_DISABLE
 719// ATOM_ENABLE
 720#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START       0x08
 721#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1    0x09
 722#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2    0x0a
 723#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3    0x13
 724#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE    0x0b
 725#define ATOM_ENCODER_CMD_DP_VIDEO_OFF                 0x0c
 726#define ATOM_ENCODER_CMD_DP_VIDEO_ON                  0x0d
 727#define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS    0x0e
 728#define ATOM_ENCODER_CMD_SETUP                        0x0f
 729#define ATOM_ENCODER_CMD_SETUP_PANEL_MODE             0x10
 730
 731// ucStatus
 732#define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE    0x10
 733#define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE  0x00
 734
 735//ucTableFormatRevision=1
 736//ucTableContentRevision=3
 737// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
 738typedef struct _ATOM_DIG_ENCODER_CONFIG_V3
 739{
 740#if ATOM_BIG_ENDIAN
 741    UCHAR ucReserved1:1;
 742    UCHAR ucDigSel:3;             // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
 743    UCHAR ucReserved:3;
 744    UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
 745#else
 746    UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
 747    UCHAR ucReserved:3;
 748    UCHAR ucDigSel:3;             // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
 749    UCHAR ucReserved1:1;
 750#endif
 751}ATOM_DIG_ENCODER_CONFIG_V3;
 752
 753#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK				0x03
 754#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ		  0x00
 755#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ		  0x01
 756#define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL					  0x70
 757#define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER					  0x00
 758#define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER					  0x10
 759#define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER					  0x20
 760#define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER					  0x30
 761#define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER					  0x40
 762#define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER					  0x50
 763
 764typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3
 765{
 766  USHORT usPixelClock;      // in 10KHz; for bios convenient
 767  ATOM_DIG_ENCODER_CONFIG_V3 acConfig;
 768  UCHAR ucAction;                              
 769  union {
 770    UCHAR ucEncoderMode;
 771                            // =0: DP   encoder      
 772                            // =1: LVDS encoder          
 773                            // =2: DVI  encoder  
 774                            // =3: HDMI encoder
 775                            // =4: SDVO encoder
 776                            // =5: DP audio
 777    UCHAR ucPanelMode;      // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
 778	                    // =0:     external DP
 779	                    // =1:     internal DP2
 780	                    // =0x11:  internal DP1 for NutMeg/Travis DP translator
 781  };
 782  UCHAR ucLaneNum;          // how many lanes to enable
 783  UCHAR ucBitPerColor;      // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
 784  UCHAR ucReserved;
 785}DIG_ENCODER_CONTROL_PARAMETERS_V3;
 786
 787//ucTableFormatRevision=1
 788//ucTableContentRevision=4
 789// start from NI           
 790// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
 791typedef struct _ATOM_DIG_ENCODER_CONFIG_V4
 792{
 793#if ATOM_BIG_ENDIAN
 794    UCHAR ucReserved1:1;
 795    UCHAR ucDigSel:3;             // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
 796    UCHAR ucReserved:2;
 797    UCHAR ucDPLinkRate:2;         // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz    <= Changed comparing to previous version
 798#else
 799    UCHAR ucDPLinkRate:2;         // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz    <= Changed comparing to previous version
 800    UCHAR ucReserved:2;
 801    UCHAR ucDigSel:3;             // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
 802    UCHAR ucReserved1:1;
 803#endif
 804}ATOM_DIG_ENCODER_CONFIG_V4;
 805
 806#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK				0x03
 807#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ		  0x00
 808#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ		  0x01
 809#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ		  0x02
 810#define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL					  0x70
 811#define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER					  0x00
 812#define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER					  0x10
 813#define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER					  0x20
 814#define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER					  0x30
 815#define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER					  0x40
 816#define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER					  0x50
 817
 818typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4
 819{
 820  USHORT usPixelClock;      // in 10KHz; for bios convenient
 821  union{
 822  ATOM_DIG_ENCODER_CONFIG_V4 acConfig;
 823  UCHAR ucConfig;
 824  };
 825  UCHAR ucAction;                              
 826  union {
 827    UCHAR ucEncoderMode;
 828                            // =0: DP   encoder      
 829                            // =1: LVDS encoder          
 830                            // =2: DVI  encoder  
 831                            // =3: HDMI encoder
 832                            // =4: SDVO encoder
 833                            // =5: DP audio
 834    UCHAR ucPanelMode;      // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
 835	                    // =0:     external DP
 836	                    // =1:     internal DP2
 837	                    // =0x11:  internal DP1 for NutMeg/Travis DP translator
 838  };
 839  UCHAR ucLaneNum;          // how many lanes to enable
 840  UCHAR ucBitPerColor;      // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
 841  UCHAR ucHPD_ID;           // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version
 842}DIG_ENCODER_CONTROL_PARAMETERS_V4;
 843
 844// define ucBitPerColor: 
 845#define PANEL_BPC_UNDEFINE                               0x00
 846#define PANEL_6BIT_PER_COLOR                             0x01 
 847#define PANEL_8BIT_PER_COLOR                             0x02
 848#define PANEL_10BIT_PER_COLOR                            0x03
 849#define PANEL_12BIT_PER_COLOR                            0x04
 850#define PANEL_16BIT_PER_COLOR                            0x05
 851
 852//define ucPanelMode
 853#define DP_PANEL_MODE_EXTERNAL_DP_MODE                   0x00
 854#define DP_PANEL_MODE_INTERNAL_DP2_MODE                  0x01
 855#define DP_PANEL_MODE_INTERNAL_DP1_MODE                  0x11
 856
 857/****************************************************************************/	
 858// Structures used by UNIPHYTransmitterControlTable
 859//                    LVTMATransmitterControlTable
 860//                    DVOOutputControlTable
 861/****************************************************************************/	
 862typedef struct _ATOM_DP_VS_MODE
 863{
 864  UCHAR ucLaneSel;
 865  UCHAR ucLaneSet;
 866}ATOM_DP_VS_MODE;
 867
 868typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS
 869{
 870	union
 871	{
 872  USHORT usPixelClock;		// in 10KHz; for bios convenient
 873	USHORT usInitInfo;			// when init uniphy,lower 8bit is used for connector type defined in objectid.h
 874  ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
 875	};
 876  UCHAR ucConfig;
 877													// [0]=0: 4 lane Link,      
 878													//    =1: 8 lane Link ( Dual Links TMDS ) 
 879                          // [1]=0: InCoherent mode   
 880													//    =1: Coherent Mode										
 881													// [2] Link Select:
 882  												// =0: PHY linkA   if bfLane<3
 883													// =1: PHY linkB   if bfLanes<3
 884		  										// =0: PHY linkA+B if bfLanes=3		
 885                          // [5:4]PCIE lane Sel
 886                          // =0: lane 0~3 or 0~7
 887                          // =1: lane 4~7
 888                          // =2: lane 8~11 or 8~15
 889                          // =3: lane 12~15 
 890	UCHAR ucAction;				  // =0: turn off encoder					
 891	                        // =1: turn on encoder			
 892  UCHAR ucReserved[4];
 893}DIG_TRANSMITTER_CONTROL_PARAMETERS;
 894
 895#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION		DIG_TRANSMITTER_CONTROL_PARAMETERS					
 896
 897//ucInitInfo
 898#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK	0x00ff			
 899
 900//ucConfig 
 901#define ATOM_TRANSMITTER_CONFIG_8LANE_LINK			0x01
 902#define ATOM_TRANSMITTER_CONFIG_COHERENT				0x02
 903#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK		0x04
 904#define ATOM_TRANSMITTER_CONFIG_LINKA						0x00
 905#define ATOM_TRANSMITTER_CONFIG_LINKB						0x04
 906#define ATOM_TRANSMITTER_CONFIG_LINKA_B					0x00			
 907#define ATOM_TRANSMITTER_CONFIG_LINKB_A					0x04
 908
 909#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK	0x08			// only used when ATOM_TRANSMITTER_ACTION_ENABLE
 910#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER		0x00				// only used when ATOM_TRANSMITTER_ACTION_ENABLE
 911#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER		0x08				// only used when ATOM_TRANSMITTER_ACTION_ENABLE
 912
 913#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK			0x30
 914#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL			0x00
 915#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE			0x20
 916#define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN		0x30
 917#define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK		0xc0
 918#define ATOM_TRANSMITTER_CONFIG_LANE_0_3				0x00
 919#define ATOM_TRANSMITTER_CONFIG_LANE_0_7				0x00
 920#define ATOM_TRANSMITTER_CONFIG_LANE_4_7				0x40
 921#define ATOM_TRANSMITTER_CONFIG_LANE_8_11				0x80
 922#define ATOM_TRANSMITTER_CONFIG_LANE_8_15				0x80
 923#define ATOM_TRANSMITTER_CONFIG_LANE_12_15			0xc0
 924
 925//ucAction
 926#define ATOM_TRANSMITTER_ACTION_DISABLE					       0
 927#define ATOM_TRANSMITTER_ACTION_ENABLE					       1
 928#define ATOM_TRANSMITTER_ACTION_LCD_BLOFF				       2
 929#define ATOM_TRANSMITTER_ACTION_LCD_BLON				       3
 930#define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL  4
 931#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START		 5
 932#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP			 6
 933#define ATOM_TRANSMITTER_ACTION_INIT						       7
 934#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT	       8
 935#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT		       9
 936#define ATOM_TRANSMITTER_ACTION_SETUP						       10
 937#define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH           11
 938#define ATOM_TRANSMITTER_ACTION_POWER_ON               12
 939#define ATOM_TRANSMITTER_ACTION_POWER_OFF              13
 940
 941// Following are used for DigTransmitterControlTable ver1.2
 942typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2
 943{
 944#if ATOM_BIG_ENDIAN
 945  UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
 946                                    //        =1 Dig Transmitter 2 ( Uniphy CD )
 947                                    //        =2 Dig Transmitter 3 ( Uniphy EF )
 948  UCHAR ucReserved:1;               
 949  UCHAR fDPConnector:1;             //bit4=0: DP connector  =1: None DP connector
 950  UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
 951  UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
 952                                    //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
 953
 954  UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
 955  UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
 956#else
 957  UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
 958  UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
 959  UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
 960                                    //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
 961  UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
 962  UCHAR fDPConnector:1;             //bit4=0: DP connector  =1: None DP connector
 963  UCHAR ucReserved:1;               
 964  UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
 965                                    //        =1 Dig Transmitter 2 ( Uniphy CD )
 966                                    //        =2 Dig Transmitter 3 ( Uniphy EF )
 967#endif
 968}ATOM_DIG_TRANSMITTER_CONFIG_V2;
 969
 970//ucConfig 
 971//Bit0
 972#define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR			0x01
 973
 974//Bit1
 975#define ATOM_TRANSMITTER_CONFIG_V2_COHERENT				          0x02
 976
 977//Bit2
 978#define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK		        0x04
 979#define ATOM_TRANSMITTER_CONFIG_V2_LINKA  			            0x00
 980#define ATOM_TRANSMITTER_CONFIG_V2_LINKB				            0x04
 981
 982// Bit3
 983#define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK	        0x08
 984#define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER		          0x00				// only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
 985#define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER		          0x08				// only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
 986
 987// Bit4
 988#define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR			        0x10
 989
 990// Bit7:6
 991#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK     0xC0
 992#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1           	0x00	//AB
 993#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2           	0x40	//CD
 994#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3           	0x80	//EF
 995
 996typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2
 997{
 998	union
 999	{
1000  USHORT usPixelClock;		// in 10KHz; for bios convenient
1001	USHORT usInitInfo;			// when init uniphy,lower 8bit is used for connector type defined in objectid.h
1002  ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1003	};
1004  ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig;
1005	UCHAR ucAction;				  // define as ATOM_TRANSMITER_ACTION_XXX
1006  UCHAR ucReserved[4];
1007}DIG_TRANSMITTER_CONTROL_PARAMETERS_V2;
1008
1009typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3
1010{
1011#if ATOM_BIG_ENDIAN
1012  UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1013           

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