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/drivers/gpu/drm/nouveau/nvc0_copy.c

https://bitbucket.org/ndreys/linux-sunxi
C | 243 lines | 180 code | 35 blank | 28 comment | 17 complexity | 73a45d066df3281b7c92677f44aa661f MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /*
  2. * Copyright 2011 Red Hat Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Ben Skeggs
  23. */
  24. #include <linux/firmware.h>
  25. #include "drmP.h"
  26. #include "nouveau_drv.h"
  27. #include "nouveau_util.h"
  28. #include "nouveau_vm.h"
  29. #include "nouveau_ramht.h"
  30. #include "nvc0_copy.fuc.h"
  31. struct nvc0_copy_engine {
  32. struct nouveau_exec_engine base;
  33. u32 irq;
  34. u32 pmc;
  35. u32 fuc;
  36. u32 ctx;
  37. };
  38. static int
  39. nvc0_copy_context_new(struct nouveau_channel *chan, int engine)
  40. {
  41. struct nvc0_copy_engine *pcopy = nv_engine(chan->dev, engine);
  42. struct drm_device *dev = chan->dev;
  43. struct drm_nouveau_private *dev_priv = dev->dev_private;
  44. struct nouveau_gpuobj *ramin = chan->ramin;
  45. struct nouveau_gpuobj *ctx = NULL;
  46. int ret;
  47. ret = nouveau_gpuobj_new(dev, NULL, 256, 256,
  48. NVOBJ_FLAG_VM | NVOBJ_FLAG_VM_USER |
  49. NVOBJ_FLAG_ZERO_ALLOC, &ctx);
  50. if (ret)
  51. return ret;
  52. nv_wo32(ramin, pcopy->ctx + 0, lower_32_bits(ctx->vinst));
  53. nv_wo32(ramin, pcopy->ctx + 4, upper_32_bits(ctx->vinst));
  54. dev_priv->engine.instmem.flush(dev);
  55. chan->engctx[engine] = ctx;
  56. return 0;
  57. }
  58. static int
  59. nvc0_copy_object_new(struct nouveau_channel *chan, int engine,
  60. u32 handle, u16 class)
  61. {
  62. return 0;
  63. }
  64. static void
  65. nvc0_copy_context_del(struct nouveau_channel *chan, int engine)
  66. {
  67. struct nvc0_copy_engine *pcopy = nv_engine(chan->dev, engine);
  68. struct nouveau_gpuobj *ctx = chan->engctx[engine];
  69. struct drm_device *dev = chan->dev;
  70. u32 inst;
  71. inst = (chan->ramin->vinst >> 12);
  72. inst |= 0x40000000;
  73. /* disable fifo access */
  74. nv_wr32(dev, pcopy->fuc + 0x048, 0x00000000);
  75. /* mark channel as unloaded if it's currently active */
  76. if (nv_rd32(dev, pcopy->fuc + 0x050) == inst)
  77. nv_mask(dev, pcopy->fuc + 0x050, 0x40000000, 0x00000000);
  78. /* mark next channel as invalid if it's about to be loaded */
  79. if (nv_rd32(dev, pcopy->fuc + 0x054) == inst)
  80. nv_mask(dev, pcopy->fuc + 0x054, 0x40000000, 0x00000000);
  81. /* restore fifo access */
  82. nv_wr32(dev, pcopy->fuc + 0x048, 0x00000003);
  83. nv_wo32(chan->ramin, pcopy->ctx + 0, 0x00000000);
  84. nv_wo32(chan->ramin, pcopy->ctx + 4, 0x00000000);
  85. nouveau_gpuobj_ref(NULL, &ctx);
  86. chan->engctx[engine] = ctx;
  87. }
  88. static int
  89. nvc0_copy_init(struct drm_device *dev, int engine)
  90. {
  91. struct nvc0_copy_engine *pcopy = nv_engine(dev, engine);
  92. int i;
  93. nv_mask(dev, 0x000200, pcopy->pmc, 0x00000000);
  94. nv_mask(dev, 0x000200, pcopy->pmc, pcopy->pmc);
  95. nv_wr32(dev, pcopy->fuc + 0x014, 0xffffffff);
  96. nv_wr32(dev, pcopy->fuc + 0x1c0, 0x01000000);
  97. for (i = 0; i < sizeof(nvc0_pcopy_data) / 4; i++)
  98. nv_wr32(dev, pcopy->fuc + 0x1c4, nvc0_pcopy_data[i]);
  99. nv_wr32(dev, pcopy->fuc + 0x180, 0x01000000);
  100. for (i = 0; i < sizeof(nvc0_pcopy_code) / 4; i++) {
  101. if ((i & 0x3f) == 0)
  102. nv_wr32(dev, pcopy->fuc + 0x188, i >> 6);
  103. nv_wr32(dev, pcopy->fuc + 0x184, nvc0_pcopy_code[i]);
  104. }
  105. nv_wr32(dev, pcopy->fuc + 0x084, engine - NVOBJ_ENGINE_COPY0);
  106. nv_wr32(dev, pcopy->fuc + 0x10c, 0x00000000);
  107. nv_wr32(dev, pcopy->fuc + 0x104, 0x00000000); /* ENTRY */
  108. nv_wr32(dev, pcopy->fuc + 0x100, 0x00000002); /* TRIGGER */
  109. return 0;
  110. }
  111. static int
  112. nvc0_copy_fini(struct drm_device *dev, int engine)
  113. {
  114. struct nvc0_copy_engine *pcopy = nv_engine(dev, engine);
  115. nv_mask(dev, pcopy->fuc + 0x048, 0x00000003, 0x00000000);
  116. /* trigger fuc context unload */
  117. nv_wait(dev, pcopy->fuc + 0x008, 0x0000000c, 0x00000000);
  118. nv_mask(dev, pcopy->fuc + 0x054, 0x40000000, 0x00000000);
  119. nv_wr32(dev, pcopy->fuc + 0x000, 0x00000008);
  120. nv_wait(dev, pcopy->fuc + 0x008, 0x00000008, 0x00000000);
  121. nv_wr32(dev, pcopy->fuc + 0x014, 0xffffffff);
  122. return 0;
  123. }
  124. static struct nouveau_enum nvc0_copy_isr_error_name[] = {
  125. { 0x0001, "ILLEGAL_MTHD" },
  126. { 0x0002, "INVALID_ENUM" },
  127. { 0x0003, "INVALID_BITFIELD" },
  128. {}
  129. };
  130. static void
  131. nvc0_copy_isr(struct drm_device *dev, int engine)
  132. {
  133. struct nvc0_copy_engine *pcopy = nv_engine(dev, engine);
  134. u32 disp = nv_rd32(dev, pcopy->fuc + 0x01c);
  135. u32 stat = nv_rd32(dev, pcopy->fuc + 0x008) & disp & ~(disp >> 16);
  136. u64 inst = (u64)(nv_rd32(dev, pcopy->fuc + 0x050) & 0x0fffffff) << 12;
  137. u32 chid = nvc0_graph_isr_chid(dev, inst);
  138. u32 ssta = nv_rd32(dev, pcopy->fuc + 0x040) & 0x0000ffff;
  139. u32 addr = nv_rd32(dev, pcopy->fuc + 0x040) >> 16;
  140. u32 mthd = (addr & 0x07ff) << 2;
  141. u32 subc = (addr & 0x3800) >> 11;
  142. u32 data = nv_rd32(dev, pcopy->fuc + 0x044);
  143. if (stat & 0x00000040) {
  144. NV_INFO(dev, "PCOPY: DISPATCH_ERROR [");
  145. nouveau_enum_print(nvc0_copy_isr_error_name, ssta);
  146. printk("] ch %d [0x%010llx] subc %d mthd 0x%04x data 0x%08x\n",
  147. chid, inst, subc, mthd, data);
  148. nv_wr32(dev, pcopy->fuc + 0x004, 0x00000040);
  149. stat &= ~0x00000040;
  150. }
  151. if (stat) {
  152. NV_INFO(dev, "PCOPY: unhandled intr 0x%08x\n", stat);
  153. nv_wr32(dev, pcopy->fuc + 0x004, stat);
  154. }
  155. }
  156. static void
  157. nvc0_copy_isr_0(struct drm_device *dev)
  158. {
  159. nvc0_copy_isr(dev, NVOBJ_ENGINE_COPY0);
  160. }
  161. static void
  162. nvc0_copy_isr_1(struct drm_device *dev)
  163. {
  164. nvc0_copy_isr(dev, NVOBJ_ENGINE_COPY1);
  165. }
  166. static void
  167. nvc0_copy_destroy(struct drm_device *dev, int engine)
  168. {
  169. struct nvc0_copy_engine *pcopy = nv_engine(dev, engine);
  170. nouveau_irq_unregister(dev, pcopy->irq);
  171. if (engine == NVOBJ_ENGINE_COPY0)
  172. NVOBJ_ENGINE_DEL(dev, COPY0);
  173. else
  174. NVOBJ_ENGINE_DEL(dev, COPY1);
  175. kfree(pcopy);
  176. }
  177. int
  178. nvc0_copy_create(struct drm_device *dev, int engine)
  179. {
  180. struct nvc0_copy_engine *pcopy;
  181. pcopy = kzalloc(sizeof(*pcopy), GFP_KERNEL);
  182. if (!pcopy)
  183. return -ENOMEM;
  184. pcopy->base.destroy = nvc0_copy_destroy;
  185. pcopy->base.init = nvc0_copy_init;
  186. pcopy->base.fini = nvc0_copy_fini;
  187. pcopy->base.context_new = nvc0_copy_context_new;
  188. pcopy->base.context_del = nvc0_copy_context_del;
  189. pcopy->base.object_new = nvc0_copy_object_new;
  190. if (engine == 0) {
  191. pcopy->irq = 5;
  192. pcopy->pmc = 0x00000040;
  193. pcopy->fuc = 0x104000;
  194. pcopy->ctx = 0x0230;
  195. nouveau_irq_register(dev, pcopy->irq, nvc0_copy_isr_0);
  196. NVOBJ_ENGINE_ADD(dev, COPY0, &pcopy->base);
  197. NVOBJ_CLASS(dev, 0x90b5, COPY0);
  198. } else {
  199. pcopy->irq = 6;
  200. pcopy->pmc = 0x00000080;
  201. pcopy->fuc = 0x105000;
  202. pcopy->ctx = 0x0240;
  203. nouveau_irq_register(dev, pcopy->irq, nvc0_copy_isr_1);
  204. NVOBJ_ENGINE_ADD(dev, COPY1, &pcopy->base);
  205. NVOBJ_CLASS(dev, 0x90b8, COPY1);
  206. }
  207. return 0;
  208. }