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/drivers/gpu/drm/nouveau/nv84_crypt.c

https://bitbucket.org/ndreys/linux-sunxi
C | 193 lines | 133 code | 33 blank | 27 comment | 8 complexity | 693d7eeb4a7d5c4e7b5699c42f8e3fe4 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1/*
  2 * Copyright 2010 Red Hat Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: Ben Skeggs
 23 */
 24
 25#include "drmP.h"
 26#include "nouveau_drv.h"
 27#include "nouveau_util.h"
 28#include "nouveau_vm.h"
 29#include "nouveau_ramht.h"
 30
 31struct nv84_crypt_engine {
 32	struct nouveau_exec_engine base;
 33};
 34
 35static int
 36nv84_crypt_context_new(struct nouveau_channel *chan, int engine)
 37{
 38	struct drm_device *dev = chan->dev;
 39	struct drm_nouveau_private *dev_priv = dev->dev_private;
 40	struct nouveau_gpuobj *ramin = chan->ramin;
 41	struct nouveau_gpuobj *ctx;
 42	int ret;
 43
 44	NV_DEBUG(dev, "ch%d\n", chan->id);
 45
 46	ret = nouveau_gpuobj_new(dev, chan, 256, 0, NVOBJ_FLAG_ZERO_ALLOC |
 47				 NVOBJ_FLAG_ZERO_FREE, &ctx);
 48	if (ret)
 49		return ret;
 50
 51	nv_wo32(ramin, 0xa0, 0x00190000);
 52	nv_wo32(ramin, 0xa4, ctx->vinst + ctx->size - 1);
 53	nv_wo32(ramin, 0xa8, ctx->vinst);
 54	nv_wo32(ramin, 0xac, 0);
 55	nv_wo32(ramin, 0xb0, 0);
 56	nv_wo32(ramin, 0xb4, 0);
 57	dev_priv->engine.instmem.flush(dev);
 58
 59	atomic_inc(&chan->vm->engref[engine]);
 60	chan->engctx[engine] = ctx;
 61	return 0;
 62}
 63
 64static void
 65nv84_crypt_context_del(struct nouveau_channel *chan, int engine)
 66{
 67	struct nouveau_gpuobj *ctx = chan->engctx[engine];
 68	struct drm_device *dev = chan->dev;
 69	u32 inst;
 70
 71	inst  = (chan->ramin->vinst >> 12);
 72	inst |= 0x80000000;
 73
 74	/* mark context as invalid if still on the hardware, not
 75	 * doing this causes issues the next time PCRYPT is used,
 76	 * unsurprisingly :)
 77	 */
 78	nv_wr32(dev, 0x10200c, 0x00000000);
 79	if (nv_rd32(dev, 0x102188) == inst)
 80		nv_mask(dev, 0x102188, 0x80000000, 0x00000000);
 81	if (nv_rd32(dev, 0x10218c) == inst)
 82		nv_mask(dev, 0x10218c, 0x80000000, 0x00000000);
 83	nv_wr32(dev, 0x10200c, 0x00000010);
 84
 85	nouveau_gpuobj_ref(NULL, &ctx);
 86
 87	atomic_dec(&chan->vm->engref[engine]);
 88	chan->engctx[engine] = NULL;
 89}
 90
 91static int
 92nv84_crypt_object_new(struct nouveau_channel *chan, int engine,
 93		      u32 handle, u16 class)
 94{
 95	struct drm_device *dev = chan->dev;
 96	struct drm_nouveau_private *dev_priv = dev->dev_private;
 97	struct nouveau_gpuobj *obj = NULL;
 98	int ret;
 99
100	ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
101	if (ret)
102		return ret;
103	obj->engine = 5;
104	obj->class  = class;
105
106	nv_wo32(obj, 0x00, class);
107	dev_priv->engine.instmem.flush(dev);
108
109	ret = nouveau_ramht_insert(chan, handle, obj);
110	nouveau_gpuobj_ref(NULL, &obj);
111	return ret;
112}
113
114static void
115nv84_crypt_tlb_flush(struct drm_device *dev, int engine)
116{
117	nv50_vm_flush_engine(dev, 0x0a);
118}
119
120static void
121nv84_crypt_isr(struct drm_device *dev)
122{
123	u32 stat = nv_rd32(dev, 0x102130);
124	u32 mthd = nv_rd32(dev, 0x102190);
125	u32 data = nv_rd32(dev, 0x102194);
126	u32 inst = nv_rd32(dev, 0x102188) & 0x7fffffff;
127	int show = nouveau_ratelimit();
128
129	if (show) {
130		NV_INFO(dev, "PCRYPT_INTR: 0x%08x 0x%08x 0x%08x 0x%08x\n",
131			     stat, mthd, data, inst);
132	}
133
134	nv_wr32(dev, 0x102130, stat);
135	nv_wr32(dev, 0x10200c, 0x10);
136
137	nv50_fb_vm_trap(dev, show);
138}
139
140static int
141nv84_crypt_fini(struct drm_device *dev, int engine)
142{
143	nv_wr32(dev, 0x102140, 0x00000000);
144	return 0;
145}
146
147static int
148nv84_crypt_init(struct drm_device *dev, int engine)
149{
150	nv_mask(dev, 0x000200, 0x00004000, 0x00000000);
151	nv_mask(dev, 0x000200, 0x00004000, 0x00004000);
152
153	nv_wr32(dev, 0x102130, 0xffffffff);
154	nv_wr32(dev, 0x102140, 0xffffffbf);
155
156	nv_wr32(dev, 0x10200c, 0x00000010);
157	return 0;
158}
159
160static void
161nv84_crypt_destroy(struct drm_device *dev, int engine)
162{
163	struct nv84_crypt_engine *pcrypt = nv_engine(dev, engine);
164
165	NVOBJ_ENGINE_DEL(dev, CRYPT);
166
167	nouveau_irq_unregister(dev, 14);
168	kfree(pcrypt);
169}
170
171int
172nv84_crypt_create(struct drm_device *dev)
173{
174	struct nv84_crypt_engine *pcrypt;
175
176	pcrypt = kzalloc(sizeof(*pcrypt), GFP_KERNEL);
177	if (!pcrypt)
178		return -ENOMEM;
179
180	pcrypt->base.destroy = nv84_crypt_destroy;
181	pcrypt->base.init = nv84_crypt_init;
182	pcrypt->base.fini = nv84_crypt_fini;
183	pcrypt->base.context_new = nv84_crypt_context_new;
184	pcrypt->base.context_del = nv84_crypt_context_del;
185	pcrypt->base.object_new = nv84_crypt_object_new;
186	pcrypt->base.tlb_flush = nv84_crypt_tlb_flush;
187
188	nouveau_irq_register(dev, 14, nv84_crypt_isr);
189
190	NVOBJ_ENGINE_ADD(dev, CRYPT, &pcrypt->base);
191	NVOBJ_CLASS (dev, 0x74c1, CRYPT);
192	return 0;
193}