PageRenderTime 77ms CodeModel.GetById 20ms app.highlight 27ms RepoModel.GetById 0ms app.codeStats 0ms

/drivers/gpu/drm/nouveau/nv17_tv.c

https://bitbucket.org/ndreys/linux-sunxi
C | 827 lines | 627 code | 152 blank | 48 comment | 131 complexity | 6240180fa98631c0f0cde5c0597f2289 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1/*
  2 * Copyright (C) 2009 Francisco Jerez.
  3 * All Rights Reserved.
  4 *
  5 * Permission is hereby granted, free of charge, to any person obtaining
  6 * a copy of this software and associated documentation files (the
  7 * "Software"), to deal in the Software without restriction, including
  8 * without limitation the rights to use, copy, modify, merge, publish,
  9 * distribute, sublicense, and/or sell copies of the Software, and to
 10 * permit persons to whom the Software is furnished to do so, subject to
 11 * the following conditions:
 12 *
 13 * The above copyright notice and this permission notice (including the
 14 * next paragraph) shall be included in all copies or substantial
 15 * portions of the Software.
 16 *
 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
 21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 24 *
 25 */
 26
 27#include "drmP.h"
 28#include "drm_crtc_helper.h"
 29#include "nouveau_drv.h"
 30#include "nouveau_encoder.h"
 31#include "nouveau_connector.h"
 32#include "nouveau_crtc.h"
 33#include "nouveau_hw.h"
 34#include "nv17_tv.h"
 35
 36static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
 37{
 38	struct drm_device *dev = encoder->dev;
 39	struct drm_nouveau_private *dev_priv = dev->dev_private;
 40	struct nouveau_gpio_engine *gpio = &dev_priv->engine.gpio;
 41	uint32_t testval, regoffset = nv04_dac_output_offset(encoder);
 42	uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end,
 43		fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c;
 44	uint32_t sample = 0;
 45	int head;
 46
 47#define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
 48	testval = RGB_TEST_DATA(0x82, 0xeb, 0x82);
 49	if (dev_priv->vbios.tvdactestval)
 50		testval = dev_priv->vbios.tvdactestval;
 51
 52	dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
 53	head = (dacclk & 0x100) >> 8;
 54
 55	/* Save the previous state. */
 56	gpio1 = gpio->get(dev, DCB_GPIO_TVDAC1);
 57	gpio0 = gpio->get(dev, DCB_GPIO_TVDAC0);
 58	fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL);
 59	fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START);
 60	fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END);
 61	fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
 62	test_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
 63	ctv_1c = NVReadRAMDAC(dev, head, 0x680c1c);
 64	ctv_14 = NVReadRAMDAC(dev, head, 0x680c14);
 65	ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c);
 66
 67	/* Prepare the DAC for load detection.  */
 68	gpio->set(dev, DCB_GPIO_TVDAC1, true);
 69	gpio->set(dev, DCB_GPIO_TVDAC0, true);
 70
 71	NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343);
 72	NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047);
 73	NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, 1183);
 74	NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL,
 75		      NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
 76		      NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12 |
 77		      NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
 78		      NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS |
 79		      NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS);
 80
 81	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, 0);
 82
 83	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
 84		      (dacclk & ~0xff) | 0x22);
 85	msleep(1);
 86	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
 87		      (dacclk & ~0xff) | 0x21);
 88
 89	NVWriteRAMDAC(dev, head, 0x680c1c, 1 << 20);
 90	NVWriteRAMDAC(dev, head, 0x680c14, 4 << 16);
 91
 92	/* Sample pin 0x4 (usually S-video luma). */
 93	NVWriteRAMDAC(dev, head, 0x680c6c, testval >> 10 & 0x3ff);
 94	msleep(20);
 95	sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
 96		& 0x4 << 28;
 97
 98	/* Sample the remaining pins. */
 99	NVWriteRAMDAC(dev, head, 0x680c6c, testval & 0x3ff);
100	msleep(20);
101	sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
102		& 0xa << 28;
103
104	/* Restore the previous state. */
105	NVWriteRAMDAC(dev, head, 0x680c1c, ctv_1c);
106	NVWriteRAMDAC(dev, head, 0x680c14, ctv_14);
107	NVWriteRAMDAC(dev, head, 0x680c6c, ctv_6c);
108	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, dacclk);
109	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, test_ctrl);
110	NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, fp_control);
111	NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end);
112	NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start);
113	NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal);
114	gpio->set(dev, DCB_GPIO_TVDAC1, gpio1);
115	gpio->set(dev, DCB_GPIO_TVDAC0, gpio0);
116
117	return sample;
118}
119
120static bool
121get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask)
122{
123	/* Zotac FX5200 */
124	if (nv_match_device(dev, 0x0322, 0x19da, 0x1035) ||
125	    nv_match_device(dev, 0x0322, 0x19da, 0x2035)) {
126		*pin_mask = 0xc;
127		return false;
128	}
129
130	/* MSI nForce2 IGP */
131	if (nv_match_device(dev, 0x01f0, 0x1462, 0x5710)) {
132		*pin_mask = 0xc;
133		return false;
134	}
135
136	return true;
137}
138
139static enum drm_connector_status
140nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector)
141{
142	struct drm_device *dev = encoder->dev;
143	struct drm_nouveau_private *dev_priv = dev->dev_private;
144	struct drm_mode_config *conf = &dev->mode_config;
145	struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
146	struct dcb_entry *dcb = tv_enc->base.dcb;
147	bool reliable = get_tv_detect_quirks(dev, &tv_enc->pin_mask);
148
149	if (nv04_dac_in_use(encoder))
150		return connector_status_disconnected;
151
152	if (reliable) {
153		if (dev_priv->chipset == 0x42 ||
154		    dev_priv->chipset == 0x43)
155			tv_enc->pin_mask =
156				nv42_tv_sample_load(encoder) >> 28 & 0xe;
157		else
158			tv_enc->pin_mask =
159				nv17_dac_sample_load(encoder) >> 28 & 0xe;
160	}
161
162	switch (tv_enc->pin_mask) {
163	case 0x2:
164	case 0x4:
165		tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Composite;
166		break;
167	case 0xc:
168		tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SVIDEO;
169		break;
170	case 0xe:
171		if (dcb->tvconf.has_component_output)
172			tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Component;
173		else
174			tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SCART;
175		break;
176	default:
177		tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
178		break;
179	}
180
181	drm_connector_property_set_value(connector,
182					 conf->tv_subconnector_property,
183					 tv_enc->subconnector);
184
185	if (!reliable) {
186		return connector_status_unknown;
187	} else if (tv_enc->subconnector) {
188		NV_INFO(dev, "Load detected on output %c\n",
189			'@' + ffs(dcb->or));
190		return connector_status_connected;
191	} else {
192		return connector_status_disconnected;
193	}
194}
195
196static int nv17_tv_get_ld_modes(struct drm_encoder *encoder,
197				struct drm_connector *connector)
198{
199	struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
200	const struct drm_display_mode *tv_mode;
201	int n = 0;
202
203	for (tv_mode = nv17_tv_modes; tv_mode->hdisplay; tv_mode++) {
204		struct drm_display_mode *mode;
205
206		mode = drm_mode_duplicate(encoder->dev, tv_mode);
207
208		mode->clock = tv_norm->tv_enc_mode.vrefresh *
209			mode->htotal / 1000 *
210			mode->vtotal / 1000;
211
212		if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
213			mode->clock *= 2;
214
215		if (mode->hdisplay == tv_norm->tv_enc_mode.hdisplay &&
216		    mode->vdisplay == tv_norm->tv_enc_mode.vdisplay)
217			mode->type |= DRM_MODE_TYPE_PREFERRED;
218
219		drm_mode_probed_add(connector, mode);
220		n++;
221	}
222
223	return n;
224}
225
226static int nv17_tv_get_hd_modes(struct drm_encoder *encoder,
227				struct drm_connector *connector)
228{
229	struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
230	struct drm_display_mode *output_mode = &tv_norm->ctv_enc_mode.mode;
231	struct drm_display_mode *mode;
232	const struct {
233		int hdisplay;
234		int vdisplay;
235	} modes[] = {
236		{ 640, 400 },
237		{ 640, 480 },
238		{ 720, 480 },
239		{ 720, 576 },
240		{ 800, 600 },
241		{ 1024, 768 },
242		{ 1280, 720 },
243		{ 1280, 1024 },
244		{ 1920, 1080 }
245	};
246	int i, n = 0;
247
248	for (i = 0; i < ARRAY_SIZE(modes); i++) {
249		if (modes[i].hdisplay > output_mode->hdisplay ||
250		    modes[i].vdisplay > output_mode->vdisplay)
251			continue;
252
253		if (modes[i].hdisplay == output_mode->hdisplay &&
254		    modes[i].vdisplay == output_mode->vdisplay) {
255			mode = drm_mode_duplicate(encoder->dev, output_mode);
256			mode->type |= DRM_MODE_TYPE_PREFERRED;
257
258		} else {
259			mode = drm_cvt_mode(encoder->dev, modes[i].hdisplay,
260					    modes[i].vdisplay, 60, false,
261					    (output_mode->flags &
262					     DRM_MODE_FLAG_INTERLACE), false);
263		}
264
265		/* CVT modes are sometimes unsuitable... */
266		if (output_mode->hdisplay <= 720
267		    || output_mode->hdisplay >= 1920) {
268			mode->htotal = output_mode->htotal;
269			mode->hsync_start = (mode->hdisplay + (mode->htotal
270					     - mode->hdisplay) * 9 / 10) & ~7;
271			mode->hsync_end = mode->hsync_start + 8;
272		}
273
274		if (output_mode->vdisplay >= 1024) {
275			mode->vtotal = output_mode->vtotal;
276			mode->vsync_start = output_mode->vsync_start;
277			mode->vsync_end = output_mode->vsync_end;
278		}
279
280		mode->type |= DRM_MODE_TYPE_DRIVER;
281		drm_mode_probed_add(connector, mode);
282		n++;
283	}
284
285	return n;
286}
287
288static int nv17_tv_get_modes(struct drm_encoder *encoder,
289			     struct drm_connector *connector)
290{
291	struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
292
293	if (tv_norm->kind == CTV_ENC_MODE)
294		return nv17_tv_get_hd_modes(encoder, connector);
295	else
296		return nv17_tv_get_ld_modes(encoder, connector);
297}
298
299static int nv17_tv_mode_valid(struct drm_encoder *encoder,
300			      struct drm_display_mode *mode)
301{
302	struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
303
304	if (tv_norm->kind == CTV_ENC_MODE) {
305		struct drm_display_mode *output_mode =
306						&tv_norm->ctv_enc_mode.mode;
307
308		if (mode->clock > 400000)
309			return MODE_CLOCK_HIGH;
310
311		if (mode->hdisplay > output_mode->hdisplay ||
312		    mode->vdisplay > output_mode->vdisplay)
313			return MODE_BAD;
314
315		if ((mode->flags & DRM_MODE_FLAG_INTERLACE) !=
316		    (output_mode->flags & DRM_MODE_FLAG_INTERLACE))
317			return MODE_NO_INTERLACE;
318
319		if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
320			return MODE_NO_DBLESCAN;
321
322	} else {
323		const int vsync_tolerance = 600;
324
325		if (mode->clock > 70000)
326			return MODE_CLOCK_HIGH;
327
328		if (abs(drm_mode_vrefresh(mode) * 1000 -
329			tv_norm->tv_enc_mode.vrefresh) > vsync_tolerance)
330			return MODE_VSYNC;
331
332		/* The encoder takes care of the actual interlacing */
333		if (mode->flags & DRM_MODE_FLAG_INTERLACE)
334			return MODE_NO_INTERLACE;
335	}
336
337	return MODE_OK;
338}
339
340static bool nv17_tv_mode_fixup(struct drm_encoder *encoder,
341			       struct drm_display_mode *mode,
342			       struct drm_display_mode *adjusted_mode)
343{
344	struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
345
346	if (nv04_dac_in_use(encoder))
347		return false;
348
349	if (tv_norm->kind == CTV_ENC_MODE)
350		adjusted_mode->clock = tv_norm->ctv_enc_mode.mode.clock;
351	else
352		adjusted_mode->clock = 90000;
353
354	return true;
355}
356
357static void  nv17_tv_dpms(struct drm_encoder *encoder, int mode)
358{
359	struct drm_device *dev = encoder->dev;
360	struct drm_nouveau_private *dev_priv = dev->dev_private;
361	struct nouveau_gpio_engine *gpio = &dev_priv->engine.gpio;
362	struct nv17_tv_state *regs = &to_tv_enc(encoder)->state;
363	struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
364
365	if (nouveau_encoder(encoder)->last_dpms == mode)
366		return;
367	nouveau_encoder(encoder)->last_dpms = mode;
368
369	NV_INFO(dev, "Setting dpms mode %d on TV encoder (output %d)\n",
370		 mode, nouveau_encoder(encoder)->dcb->index);
371
372	regs->ptv_200 &= ~1;
373
374	if (tv_norm->kind == CTV_ENC_MODE) {
375		nv04_dfp_update_fp_control(encoder, mode);
376
377	} else {
378		nv04_dfp_update_fp_control(encoder, DRM_MODE_DPMS_OFF);
379
380		if (mode == DRM_MODE_DPMS_ON)
381			regs->ptv_200 |= 1;
382	}
383
384	nv_load_ptv(dev, regs, 200);
385
386	gpio->set(dev, DCB_GPIO_TVDAC1, mode == DRM_MODE_DPMS_ON);
387	gpio->set(dev, DCB_GPIO_TVDAC0, mode == DRM_MODE_DPMS_ON);
388
389	nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON);
390}
391
392static void nv17_tv_prepare(struct drm_encoder *encoder)
393{
394	struct drm_device *dev = encoder->dev;
395	struct drm_nouveau_private *dev_priv = dev->dev_private;
396	struct drm_encoder_helper_funcs *helper = encoder->helper_private;
397	struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
398	int head = nouveau_crtc(encoder->crtc)->index;
399	uint8_t *cr_lcd = &dev_priv->mode_reg.crtc_reg[head].CRTC[
400							NV_CIO_CRE_LCD__INDEX];
401	uint32_t dacclk_off = NV_PRAMDAC_DACCLK +
402					nv04_dac_output_offset(encoder);
403	uint32_t dacclk;
404
405	helper->dpms(encoder, DRM_MODE_DPMS_OFF);
406
407	nv04_dfp_disable(dev, head);
408
409	/* Unbind any FP encoders from this head if we need the FP
410	 * stuff enabled. */
411	if (tv_norm->kind == CTV_ENC_MODE) {
412		struct drm_encoder *enc;
413
414		list_for_each_entry(enc, &dev->mode_config.encoder_list, head) {
415			struct dcb_entry *dcb = nouveau_encoder(enc)->dcb;
416
417			if ((dcb->type == OUTPUT_TMDS ||
418			     dcb->type == OUTPUT_LVDS) &&
419			     !enc->crtc &&
420			     nv04_dfp_get_bound_head(dev, dcb) == head) {
421				nv04_dfp_bind_head(dev, dcb, head ^ 1,
422						dev_priv->vbios.fp.dual_link);
423			}
424		}
425
426	}
427
428	if (tv_norm->kind == CTV_ENC_MODE)
429		*cr_lcd |= 0x1 | (head ? 0x0 : 0x8);
430
431	/* Set the DACCLK register */
432	dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1;
433
434	if (dev_priv->card_type == NV_40)
435		dacclk |= 0x1a << 16;
436
437	if (tv_norm->kind == CTV_ENC_MODE) {
438		dacclk |=  0x20;
439
440		if (head)
441			dacclk |= 0x100;
442		else
443			dacclk &= ~0x100;
444
445	} else {
446		dacclk |= 0x10;
447
448	}
449
450	NVWriteRAMDAC(dev, 0, dacclk_off, dacclk);
451}
452
453static void nv17_tv_mode_set(struct drm_encoder *encoder,
454			     struct drm_display_mode *drm_mode,
455			     struct drm_display_mode *adjusted_mode)
456{
457	struct drm_device *dev = encoder->dev;
458	struct drm_nouveau_private *dev_priv = dev->dev_private;
459	int head = nouveau_crtc(encoder->crtc)->index;
460	struct nv04_crtc_reg *regs = &dev_priv->mode_reg.crtc_reg[head];
461	struct nv17_tv_state *tv_regs = &to_tv_enc(encoder)->state;
462	struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
463	int i;
464
465	regs->CRTC[NV_CIO_CRE_53] = 0x40; /* FP_HTIMING */
466	regs->CRTC[NV_CIO_CRE_54] = 0; /* FP_VTIMING */
467	regs->ramdac_630 = 0x2; /* turn off green mode (tv test pattern?) */
468	regs->tv_setup = 1;
469	regs->ramdac_8c0 = 0x0;
470
471	if (tv_norm->kind == TV_ENC_MODE) {
472		tv_regs->ptv_200 = 0x13111100;
473		if (head)
474			tv_regs->ptv_200 |= 0x10;
475
476		tv_regs->ptv_20c = 0x808010;
477		tv_regs->ptv_304 = 0x2d00000;
478		tv_regs->ptv_600 = 0x0;
479		tv_regs->ptv_60c = 0x0;
480		tv_regs->ptv_610 = 0x1e00000;
481
482		if (tv_norm->tv_enc_mode.vdisplay == 576) {
483			tv_regs->ptv_508 = 0x1200000;
484			tv_regs->ptv_614 = 0x33;
485
486		} else if (tv_norm->tv_enc_mode.vdisplay == 480) {
487			tv_regs->ptv_508 = 0xf00000;
488			tv_regs->ptv_614 = 0x13;
489		}
490
491		if (dev_priv->card_type >= NV_30) {
492			tv_regs->ptv_500 = 0xe8e0;
493			tv_regs->ptv_504 = 0x1710;
494			tv_regs->ptv_604 = 0x0;
495			tv_regs->ptv_608 = 0x0;
496		} else {
497			if (tv_norm->tv_enc_mode.vdisplay == 576) {
498				tv_regs->ptv_604 = 0x20;
499				tv_regs->ptv_608 = 0x10;
500				tv_regs->ptv_500 = 0x19710;
501				tv_regs->ptv_504 = 0x68f0;
502
503			} else if (tv_norm->tv_enc_mode.vdisplay == 480) {
504				tv_regs->ptv_604 = 0x10;
505				tv_regs->ptv_608 = 0x20;
506				tv_regs->ptv_500 = 0x4b90;
507				tv_regs->ptv_504 = 0x1b480;
508			}
509		}
510
511		for (i = 0; i < 0x40; i++)
512			tv_regs->tv_enc[i] = tv_norm->tv_enc_mode.tv_enc[i];
513
514	} else {
515		struct drm_display_mode *output_mode =
516						&tv_norm->ctv_enc_mode.mode;
517
518		/* The registers in PRAMDAC+0xc00 control some timings and CSC
519		 * parameters for the CTV encoder (It's only used for "HD" TV
520		 * modes, I don't think I have enough working to guess what
521		 * they exactly mean...), it's probably connected at the
522		 * output of the FP encoder, but it also needs the analog
523		 * encoder in its OR enabled and routed to the head it's
524		 * using. It's enabled with the DACCLK register, bits [5:4].
525		 */
526		for (i = 0; i < 38; i++)
527			regs->ctv_regs[i] = tv_norm->ctv_enc_mode.ctv_regs[i];
528
529		regs->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;
530		regs->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
531		regs->fp_horiz_regs[FP_SYNC_START] =
532						output_mode->hsync_start - 1;
533		regs->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
534		regs->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay +
535			max((output_mode->hdisplay-600)/40 - 1, 1);
536
537		regs->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;
538		regs->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;
539		regs->fp_vert_regs[FP_SYNC_START] =
540						output_mode->vsync_start - 1;
541		regs->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;
542		regs->fp_vert_regs[FP_CRTC] = output_mode->vdisplay - 1;
543
544		regs->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
545			NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
546			NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
547
548		if (output_mode->flags & DRM_MODE_FLAG_PVSYNC)
549			regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS;
550		if (output_mode->flags & DRM_MODE_FLAG_PHSYNC)
551			regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS;
552
553		regs->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND |
554			NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND |
555			NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR |
556			NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR |
557			NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED |
558			NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE |
559			NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE;
560
561		regs->fp_debug_2 = 0;
562
563		regs->fp_margin_color = 0x801080;
564
565	}
566}
567
568static void nv17_tv_commit(struct drm_encoder *encoder)
569{
570	struct drm_device *dev = encoder->dev;
571	struct drm_nouveau_private *dev_priv = dev->dev_private;
572	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
573	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
574	struct drm_encoder_helper_funcs *helper = encoder->helper_private;
575
576	if (get_tv_norm(encoder)->kind == TV_ENC_MODE) {
577		nv17_tv_update_rescaler(encoder);
578		nv17_tv_update_properties(encoder);
579	} else {
580		nv17_ctv_update_rescaler(encoder);
581	}
582
583	nv17_tv_state_load(dev, &to_tv_enc(encoder)->state);
584
585	/* This could use refinement for flatpanels, but it should work */
586	if (dev_priv->chipset < 0x44)
587		NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
588					nv04_dac_output_offset(encoder),
589					0xf0000000);
590	else
591		NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
592					nv04_dac_output_offset(encoder),
593					0x00100000);
594
595	helper->dpms(encoder, DRM_MODE_DPMS_ON);
596
597	NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
598		drm_get_connector_name(
599			&nouveau_encoder_connector_get(nv_encoder)->base),
600		nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
601}
602
603static void nv17_tv_save(struct drm_encoder *encoder)
604{
605	struct drm_device *dev = encoder->dev;
606	struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
607
608	nouveau_encoder(encoder)->restore.output =
609					NVReadRAMDAC(dev, 0,
610					NV_PRAMDAC_DACCLK +
611					nv04_dac_output_offset(encoder));
612
613	nv17_tv_state_save(dev, &tv_enc->saved_state);
614
615	tv_enc->state.ptv_200 = tv_enc->saved_state.ptv_200;
616}
617
618static void nv17_tv_restore(struct drm_encoder *encoder)
619{
620	struct drm_device *dev = encoder->dev;
621
622	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK +
623				nv04_dac_output_offset(encoder),
624				nouveau_encoder(encoder)->restore.output);
625
626	nv17_tv_state_load(dev, &to_tv_enc(encoder)->saved_state);
627
628	nouveau_encoder(encoder)->last_dpms = NV_DPMS_CLEARED;
629}
630
631static int nv17_tv_create_resources(struct drm_encoder *encoder,
632				    struct drm_connector *connector)
633{
634	struct drm_device *dev = encoder->dev;
635	struct drm_mode_config *conf = &dev->mode_config;
636	struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
637	struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
638	int num_tv_norms = dcb->tvconf.has_component_output ? NUM_TV_NORMS :
639							NUM_LD_TV_NORMS;
640	int i;
641
642	if (nouveau_tv_norm) {
643		for (i = 0; i < num_tv_norms; i++) {
644			if (!strcmp(nv17_tv_norm_names[i], nouveau_tv_norm)) {
645				tv_enc->tv_norm = i;
646				break;
647			}
648		}
649
650		if (i == num_tv_norms)
651			NV_WARN(dev, "Invalid TV norm setting \"%s\"\n",
652				nouveau_tv_norm);
653	}
654
655	drm_mode_create_tv_properties(dev, num_tv_norms, nv17_tv_norm_names);
656
657	drm_connector_attach_property(connector,
658					conf->tv_select_subconnector_property,
659					tv_enc->select_subconnector);
660	drm_connector_attach_property(connector,
661					conf->tv_subconnector_property,
662					tv_enc->subconnector);
663	drm_connector_attach_property(connector,
664					conf->tv_mode_property,
665					tv_enc->tv_norm);
666	drm_connector_attach_property(connector,
667					conf->tv_flicker_reduction_property,
668					tv_enc->flicker);
669	drm_connector_attach_property(connector,
670					conf->tv_saturation_property,
671					tv_enc->saturation);
672	drm_connector_attach_property(connector,
673					conf->tv_hue_property,
674					tv_enc->hue);
675	drm_connector_attach_property(connector,
676					conf->tv_overscan_property,
677					tv_enc->overscan);
678
679	return 0;
680}
681
682static int nv17_tv_set_property(struct drm_encoder *encoder,
683				struct drm_connector *connector,
684				struct drm_property *property,
685				uint64_t val)
686{
687	struct drm_mode_config *conf = &encoder->dev->mode_config;
688	struct drm_crtc *crtc = encoder->crtc;
689	struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
690	struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
691	bool modes_changed = false;
692
693	if (property == conf->tv_overscan_property) {
694		tv_enc->overscan = val;
695		if (encoder->crtc) {
696			if (tv_norm->kind == CTV_ENC_MODE)
697				nv17_ctv_update_rescaler(encoder);
698			else
699				nv17_tv_update_rescaler(encoder);
700		}
701
702	} else if (property == conf->tv_saturation_property) {
703		if (tv_norm->kind != TV_ENC_MODE)
704			return -EINVAL;
705
706		tv_enc->saturation = val;
707		nv17_tv_update_properties(encoder);
708
709	} else if (property == conf->tv_hue_property) {
710		if (tv_norm->kind != TV_ENC_MODE)
711			return -EINVAL;
712
713		tv_enc->hue = val;
714		nv17_tv_update_properties(encoder);
715
716	} else if (property == conf->tv_flicker_reduction_property) {
717		if (tv_norm->kind != TV_ENC_MODE)
718			return -EINVAL;
719
720		tv_enc->flicker = val;
721		if (encoder->crtc)
722			nv17_tv_update_rescaler(encoder);
723
724	} else if (property == conf->tv_mode_property) {
725		if (connector->dpms != DRM_MODE_DPMS_OFF)
726			return -EINVAL;
727
728		tv_enc->tv_norm = val;
729
730		modes_changed = true;
731
732	} else if (property == conf->tv_select_subconnector_property) {
733		if (tv_norm->kind != TV_ENC_MODE)
734			return -EINVAL;
735
736		tv_enc->select_subconnector = val;
737		nv17_tv_update_properties(encoder);
738
739	} else {
740		return -EINVAL;
741	}
742
743	if (modes_changed) {
744		drm_helper_probe_single_connector_modes(connector, 0, 0);
745
746		/* Disable the crtc to ensure a full modeset is
747		 * performed whenever it's turned on again. */
748		if (crtc) {
749			struct drm_mode_set modeset = {
750				.crtc = crtc,
751			};
752
753			crtc->funcs->set_config(&modeset);
754		}
755	}
756
757	return 0;
758}
759
760static void nv17_tv_destroy(struct drm_encoder *encoder)
761{
762	struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
763
764	NV_DEBUG_KMS(encoder->dev, "\n");
765
766	drm_encoder_cleanup(encoder);
767	kfree(tv_enc);
768}
769
770static struct drm_encoder_helper_funcs nv17_tv_helper_funcs = {
771	.dpms = nv17_tv_dpms,
772	.save = nv17_tv_save,
773	.restore = nv17_tv_restore,
774	.mode_fixup = nv17_tv_mode_fixup,
775	.prepare = nv17_tv_prepare,
776	.commit = nv17_tv_commit,
777	.mode_set = nv17_tv_mode_set,
778	.detect = nv17_tv_detect,
779};
780
781static struct drm_encoder_slave_funcs nv17_tv_slave_funcs = {
782	.get_modes = nv17_tv_get_modes,
783	.mode_valid = nv17_tv_mode_valid,
784	.create_resources = nv17_tv_create_resources,
785	.set_property = nv17_tv_set_property,
786};
787
788static struct drm_encoder_funcs nv17_tv_funcs = {
789	.destroy = nv17_tv_destroy,
790};
791
792int
793nv17_tv_create(struct drm_connector *connector, struct dcb_entry *entry)
794{
795	struct drm_device *dev = connector->dev;
796	struct drm_encoder *encoder;
797	struct nv17_tv_encoder *tv_enc = NULL;
798
799	tv_enc = kzalloc(sizeof(*tv_enc), GFP_KERNEL);
800	if (!tv_enc)
801		return -ENOMEM;
802
803	tv_enc->overscan = 50;
804	tv_enc->flicker = 50;
805	tv_enc->saturation = 50;
806	tv_enc->hue = 0;
807	tv_enc->tv_norm = TV_NORM_PAL;
808	tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
809	tv_enc->select_subconnector = DRM_MODE_SUBCONNECTOR_Automatic;
810	tv_enc->pin_mask = 0;
811
812	encoder = to_drm_encoder(&tv_enc->base);
813
814	tv_enc->base.dcb = entry;
815	tv_enc->base.or = ffs(entry->or) - 1;
816
817	drm_encoder_init(dev, encoder, &nv17_tv_funcs, DRM_MODE_ENCODER_TVDAC);
818	drm_encoder_helper_add(encoder, &nv17_tv_helper_funcs);
819	to_encoder_slave(encoder)->slave_funcs = &nv17_tv_slave_funcs;
820
821	encoder->possible_crtcs = entry->heads;
822	encoder->possible_clones = 0;
823
824	nv17_tv_create_resources(encoder, connector);
825	drm_mode_connector_attach_encoder(connector, encoder);
826	return 0;
827}