/drivers/block/cciss.h

https://bitbucket.org/ndreys/linux-sunxi · C++ Header · 434 lines · 315 code · 45 blank · 74 comment · 23 complexity · 19606680b419efe3ba86ad54112f872d MD5 · raw file

  1. #ifndef CCISS_H
  2. #define CCISS_H
  3. #include <linux/genhd.h>
  4. #include <linux/mutex.h>
  5. #include "cciss_cmd.h"
  6. #define NWD_SHIFT 4
  7. #define MAX_PART (1 << NWD_SHIFT)
  8. #define IO_OK 0
  9. #define IO_ERROR 1
  10. #define IO_NEEDS_RETRY 3
  11. #define VENDOR_LEN 8
  12. #define MODEL_LEN 16
  13. #define REV_LEN 4
  14. struct ctlr_info;
  15. typedef struct ctlr_info ctlr_info_t;
  16. struct access_method {
  17. void (*submit_command)(ctlr_info_t *h, CommandList_struct *c);
  18. void (*set_intr_mask)(ctlr_info_t *h, unsigned long val);
  19. unsigned long (*fifo_full)(ctlr_info_t *h);
  20. bool (*intr_pending)(ctlr_info_t *h);
  21. unsigned long (*command_completed)(ctlr_info_t *h);
  22. };
  23. typedef struct _drive_info_struct
  24. {
  25. unsigned char LunID[8];
  26. int usage_count;
  27. struct request_queue *queue;
  28. sector_t nr_blocks;
  29. int block_size;
  30. int heads;
  31. int sectors;
  32. int cylinders;
  33. int raid_level; /* set to -1 to indicate that
  34. * the drive is not in use/configured
  35. */
  36. int busy_configuring; /* This is set when a drive is being removed
  37. * to prevent it from being opened or it's
  38. * queue from being started.
  39. */
  40. struct device dev;
  41. __u8 serial_no[16]; /* from inquiry page 0x83,
  42. * not necc. null terminated.
  43. */
  44. char vendor[VENDOR_LEN + 1]; /* SCSI vendor string */
  45. char model[MODEL_LEN + 1]; /* SCSI model string */
  46. char rev[REV_LEN + 1]; /* SCSI revision string */
  47. char device_initialized; /* indicates whether dev is initialized */
  48. } drive_info_struct;
  49. struct ctlr_info
  50. {
  51. int ctlr;
  52. char devname[8];
  53. char *product_name;
  54. char firm_ver[4]; /* Firmware version */
  55. struct pci_dev *pdev;
  56. __u32 board_id;
  57. void __iomem *vaddr;
  58. unsigned long paddr;
  59. int nr_cmds; /* Number of commands allowed on this controller */
  60. CfgTable_struct __iomem *cfgtable;
  61. int interrupts_enabled;
  62. int major;
  63. int max_commands;
  64. int commands_outstanding;
  65. int max_outstanding; /* Debug */
  66. int num_luns;
  67. int highest_lun;
  68. int usage_count; /* number of opens all all minor devices */
  69. /* Need space for temp sg list
  70. * number of scatter/gathers supported
  71. * number of scatter/gathers in chained block
  72. */
  73. struct scatterlist **scatter_list;
  74. int maxsgentries;
  75. int chainsize;
  76. int max_cmd_sgentries;
  77. SGDescriptor_struct **cmd_sg_list;
  78. # define PERF_MODE_INT 0
  79. # define DOORBELL_INT 1
  80. # define SIMPLE_MODE_INT 2
  81. # define MEMQ_MODE_INT 3
  82. unsigned int intr[4];
  83. unsigned int msix_vector;
  84. unsigned int msi_vector;
  85. int cciss_max_sectors;
  86. BYTE cciss_read;
  87. BYTE cciss_write;
  88. BYTE cciss_read_capacity;
  89. /* information about each logical volume */
  90. drive_info_struct *drv[CISS_MAX_LUN];
  91. struct access_method access;
  92. /* queue and queue Info */
  93. struct list_head reqQ;
  94. struct list_head cmpQ;
  95. unsigned int Qdepth;
  96. unsigned int maxQsinceinit;
  97. unsigned int maxSG;
  98. spinlock_t lock;
  99. /* pointers to command and error info pool */
  100. CommandList_struct *cmd_pool;
  101. dma_addr_t cmd_pool_dhandle;
  102. ErrorInfo_struct *errinfo_pool;
  103. dma_addr_t errinfo_pool_dhandle;
  104. unsigned long *cmd_pool_bits;
  105. int nr_allocs;
  106. int nr_frees;
  107. int busy_configuring;
  108. int busy_initializing;
  109. int busy_scanning;
  110. struct mutex busy_shutting_down;
  111. /* This element holds the zero based queue number of the last
  112. * queue to be started. It is used for fairness.
  113. */
  114. int next_to_run;
  115. /* Disk structures we need to pass back */
  116. struct gendisk *gendisk[CISS_MAX_LUN];
  117. #ifdef CONFIG_CISS_SCSI_TAPE
  118. struct cciss_scsi_adapter_data_t *scsi_ctlr;
  119. #endif
  120. unsigned char alive;
  121. struct list_head scan_list;
  122. struct completion scan_wait;
  123. struct device dev;
  124. /*
  125. * Performant mode tables.
  126. */
  127. u32 trans_support;
  128. u32 trans_offset;
  129. struct TransTable_struct *transtable;
  130. unsigned long transMethod;
  131. /*
  132. * Performant mode completion buffer
  133. */
  134. u64 *reply_pool;
  135. dma_addr_t reply_pool_dhandle;
  136. u64 *reply_pool_head;
  137. size_t reply_pool_size;
  138. unsigned char reply_pool_wraparound;
  139. u32 *blockFetchTable;
  140. };
  141. /* Defining the diffent access_methods
  142. *
  143. * Memory mapped FIFO interface (SMART 53xx cards)
  144. */
  145. #define SA5_DOORBELL 0x20
  146. #define SA5_REQUEST_PORT_OFFSET 0x40
  147. #define SA5_REPLY_INTR_MASK_OFFSET 0x34
  148. #define SA5_REPLY_PORT_OFFSET 0x44
  149. #define SA5_INTR_STATUS 0x30
  150. #define SA5_SCRATCHPAD_OFFSET 0xB0
  151. #define SA5_CTCFG_OFFSET 0xB4
  152. #define SA5_CTMEM_OFFSET 0xB8
  153. #define SA5_INTR_OFF 0x08
  154. #define SA5B_INTR_OFF 0x04
  155. #define SA5_INTR_PENDING 0x08
  156. #define SA5B_INTR_PENDING 0x04
  157. #define FIFO_EMPTY 0xffffffff
  158. #define CCISS_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
  159. /* Perf. mode flags */
  160. #define SA5_PERF_INTR_PENDING 0x04
  161. #define SA5_PERF_INTR_OFF 0x05
  162. #define SA5_OUTDB_STATUS_PERF_BIT 0x01
  163. #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
  164. #define SA5_OUTDB_CLEAR 0xA0
  165. #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
  166. #define SA5_OUTDB_STATUS 0x9C
  167. #define CISS_ERROR_BIT 0x02
  168. #define CCISS_INTR_ON 1
  169. #define CCISS_INTR_OFF 0
  170. /* CCISS_BOARD_READY_WAIT_SECS is how long to wait for a board
  171. * to become ready, in seconds, before giving up on it.
  172. * CCISS_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
  173. * between polling the board to see if it is ready, in
  174. * milliseconds. CCISS_BOARD_READY_ITERATIONS is derived
  175. * the above.
  176. */
  177. #define CCISS_BOARD_READY_WAIT_SECS (120)
  178. #define CCISS_BOARD_NOT_READY_WAIT_SECS (100)
  179. #define CCISS_BOARD_READY_POLL_INTERVAL_MSECS (100)
  180. #define CCISS_BOARD_READY_ITERATIONS \
  181. ((CCISS_BOARD_READY_WAIT_SECS * 1000) / \
  182. CCISS_BOARD_READY_POLL_INTERVAL_MSECS)
  183. #define CCISS_BOARD_NOT_READY_ITERATIONS \
  184. ((CCISS_BOARD_NOT_READY_WAIT_SECS * 1000) / \
  185. CCISS_BOARD_READY_POLL_INTERVAL_MSECS)
  186. #define CCISS_POST_RESET_PAUSE_MSECS (3000)
  187. #define CCISS_POST_RESET_NOOP_INTERVAL_MSECS (4000)
  188. #define CCISS_POST_RESET_NOOP_RETRIES (12)
  189. #define CCISS_POST_RESET_NOOP_TIMEOUT_MSECS (10000)
  190. /*
  191. Send the command to the hardware
  192. */
  193. static void SA5_submit_command( ctlr_info_t *h, CommandList_struct *c)
  194. {
  195. #ifdef CCISS_DEBUG
  196. printk(KERN_WARNING "cciss%d: Sending %08x - down to controller\n",
  197. h->ctlr, c->busaddr);
  198. #endif /* CCISS_DEBUG */
  199. writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
  200. readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
  201. h->commands_outstanding++;
  202. if ( h->commands_outstanding > h->max_outstanding)
  203. h->max_outstanding = h->commands_outstanding;
  204. }
  205. /*
  206. * This card is the opposite of the other cards.
  207. * 0 turns interrupts on...
  208. * 0x08 turns them off...
  209. */
  210. static void SA5_intr_mask(ctlr_info_t *h, unsigned long val)
  211. {
  212. if (val)
  213. { /* Turn interrupts on */
  214. h->interrupts_enabled = 1;
  215. writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  216. (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  217. } else /* Turn them off */
  218. {
  219. h->interrupts_enabled = 0;
  220. writel( SA5_INTR_OFF,
  221. h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  222. (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  223. }
  224. }
  225. /*
  226. * This card is the opposite of the other cards.
  227. * 0 turns interrupts on...
  228. * 0x04 turns them off...
  229. */
  230. static void SA5B_intr_mask(ctlr_info_t *h, unsigned long val)
  231. {
  232. if (val)
  233. { /* Turn interrupts on */
  234. h->interrupts_enabled = 1;
  235. writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  236. (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  237. } else /* Turn them off */
  238. {
  239. h->interrupts_enabled = 0;
  240. writel( SA5B_INTR_OFF,
  241. h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  242. (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  243. }
  244. }
  245. /* Performant mode intr_mask */
  246. static void SA5_performant_intr_mask(ctlr_info_t *h, unsigned long val)
  247. {
  248. if (val) { /* turn on interrupts */
  249. h->interrupts_enabled = 1;
  250. writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  251. (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  252. } else {
  253. h->interrupts_enabled = 0;
  254. writel(SA5_PERF_INTR_OFF,
  255. h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  256. (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  257. }
  258. }
  259. /*
  260. * Returns true if fifo is full.
  261. *
  262. */
  263. static unsigned long SA5_fifo_full(ctlr_info_t *h)
  264. {
  265. if( h->commands_outstanding >= h->max_commands)
  266. return(1);
  267. else
  268. return(0);
  269. }
  270. /*
  271. * returns value read from hardware.
  272. * returns FIFO_EMPTY if there is nothing to read
  273. */
  274. static unsigned long SA5_completed(ctlr_info_t *h)
  275. {
  276. unsigned long register_value
  277. = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
  278. if(register_value != FIFO_EMPTY)
  279. {
  280. h->commands_outstanding--;
  281. #ifdef CCISS_DEBUG
  282. printk("cciss: Read %lx back from board\n", register_value);
  283. #endif /* CCISS_DEBUG */
  284. }
  285. #ifdef CCISS_DEBUG
  286. else
  287. {
  288. printk("cciss: FIFO Empty read\n");
  289. }
  290. #endif
  291. return ( register_value);
  292. }
  293. /* Performant mode command completed */
  294. static unsigned long SA5_performant_completed(ctlr_info_t *h)
  295. {
  296. unsigned long register_value = FIFO_EMPTY;
  297. /* flush the controller write of the reply queue by reading
  298. * outbound doorbell status register.
  299. */
  300. register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
  301. /* msi auto clears the interrupt pending bit. */
  302. if (!(h->msi_vector || h->msix_vector)) {
  303. writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
  304. /* Do a read in order to flush the write to the controller
  305. * (as per spec.)
  306. */
  307. register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
  308. }
  309. if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
  310. register_value = *(h->reply_pool_head);
  311. (h->reply_pool_head)++;
  312. h->commands_outstanding--;
  313. } else {
  314. register_value = FIFO_EMPTY;
  315. }
  316. /* Check for wraparound */
  317. if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {
  318. h->reply_pool_head = h->reply_pool;
  319. h->reply_pool_wraparound ^= 1;
  320. }
  321. return register_value;
  322. }
  323. /*
  324. * Returns true if an interrupt is pending..
  325. */
  326. static bool SA5_intr_pending(ctlr_info_t *h)
  327. {
  328. unsigned long register_value =
  329. readl(h->vaddr + SA5_INTR_STATUS);
  330. #ifdef CCISS_DEBUG
  331. printk("cciss: intr_pending %lx\n", register_value);
  332. #endif /* CCISS_DEBUG */
  333. if( register_value & SA5_INTR_PENDING)
  334. return 1;
  335. return 0 ;
  336. }
  337. /*
  338. * Returns true if an interrupt is pending..
  339. */
  340. static bool SA5B_intr_pending(ctlr_info_t *h)
  341. {
  342. unsigned long register_value =
  343. readl(h->vaddr + SA5_INTR_STATUS);
  344. #ifdef CCISS_DEBUG
  345. printk("cciss: intr_pending %lx\n", register_value);
  346. #endif /* CCISS_DEBUG */
  347. if( register_value & SA5B_INTR_PENDING)
  348. return 1;
  349. return 0 ;
  350. }
  351. static bool SA5_performant_intr_pending(ctlr_info_t *h)
  352. {
  353. unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
  354. if (!register_value)
  355. return false;
  356. if (h->msi_vector || h->msix_vector)
  357. return true;
  358. /* Read outbound doorbell to flush */
  359. register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
  360. return register_value & SA5_OUTDB_STATUS_PERF_BIT;
  361. }
  362. static struct access_method SA5_access = {
  363. SA5_submit_command,
  364. SA5_intr_mask,
  365. SA5_fifo_full,
  366. SA5_intr_pending,
  367. SA5_completed,
  368. };
  369. static struct access_method SA5B_access = {
  370. SA5_submit_command,
  371. SA5B_intr_mask,
  372. SA5_fifo_full,
  373. SA5B_intr_pending,
  374. SA5_completed,
  375. };
  376. static struct access_method SA5_performant_access = {
  377. SA5_submit_command,
  378. SA5_performant_intr_mask,
  379. SA5_fifo_full,
  380. SA5_performant_intr_pending,
  381. SA5_performant_completed,
  382. };
  383. struct board_type {
  384. __u32 board_id;
  385. char *product_name;
  386. struct access_method *access;
  387. int nr_cmds; /* Max cmds this kind of ctlr can handle. */
  388. };
  389. #endif /* CCISS_H */