/drivers/block/sunxi_nand/src/include/nand_physic.h
C Header | 336 lines | 59 code | 70 blank | 207 comment | 0 complexity | 17bb3433e06710429d92646abf57859b MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
1/* 2 * drivers/block/sunxi_nand/src/include/nand_physic.h 3 * 4 * (C) Copyright 2007-2012 5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23#ifndef __NAND_PHYSIC_H__ 24#define __NAND_PHYSIC_H__ 25 26#include "nand_type.h" 27 28//=========================================== 29extern struct __NandStorageInfo_t NandStorageInfo; 30extern struct __NandPageCachePool_t PageCachePool; 31//=========================================== 32 33 34 35//============================================================================== 36// define the physical archictecture export parameter 37//============================================================================== 38 39//define the Ecc Mode 40#define ECC_MODE (NandStorageInfo.EccMode) 41 42//define the DDR tyep 43#define DDR_TYPE (NandStorageInfo.DDRType) 44 45//define the sector count of a single physical page 46#define SECTOR_CNT_OF_SINGLE_PAGE (NandStorageInfo.SectorCntPerPage) 47 48//define the sector count of a super physical page, the super page may be based on multi-plane 49#define SECTOR_CNT_OF_SUPER_PAGE (NandStorageInfo.SectorCntPerPage * NandStorageInfo.PlaneCntPerDie) 50 51//define the sector bitmap for a single page 52#define FULL_BITMAP_OF_SINGLE_PAGE ((__u32)((1<<SECTOR_CNT_OF_SINGLE_PAGE) - 1)) 53 54//define the sector bitmap for a super page, the sector count of a super page may be equal to 32 55#define FULL_BITMAP_OF_SUPER_PAGE ((__u32)((1<<(SECTOR_CNT_OF_SUPER_PAGE - 1)) | ((1<<(SECTOR_CNT_OF_SUPER_PAGE - 1)) - 1))) 56 57//define the block number offset for the multi-plane operation 58#define MULTI_PLANE_BLOCK_OFFSET (NandStorageInfo.OptPhyOpPar.MultiPlaneBlockOffset) 59 60//define the position of the bad block flag in a physical block 61#define BAD_BLOCK_FLAG_PST (NandStorageInfo.OptPhyOpPar.BadBlockFlagPosition) 62 63//define if the nand flash can support cache read operation 64#define SUPPORT_CACHE_READ (NAND_CACHE_READ & NandStorageInfo.OperationOpt) 65 66//define if the nand flash can support cache program operation 67#define SUPPORT_CACHE_PROGRAM (NAND_CACHE_PROGRAM & NandStorageInfo.OperationOpt) 68 69//define if the nand flash can support multi-plane read operation 70#define SUPPORT_MULTI_READ (NAND_MULTI_READ & NandStorageInfo.OperationOpt) 71 72//define if the nand flash can support multi-plane program operation 73#define SUPPORT_MULTI_PROGRAM (NAND_MULTI_PROGRAM & NandStorageInfo.OperationOpt) 74 75//define if the nand flash can support page copy-back with command operation 76#define SUPPORT_PAGE_COPYBACK (NAND_PAGE_COPYBACK & NandStorageInfo.OperationOpt) 77 78//define if the nand flash can support __s32ernal __s32er-leave operation 79#define SUPPORT_INT_INTERLEAVE (NAND_INT_INTERLEAVE & NandStorageInfo.OperationOpt) 80 81//define if the nand flash system can support external __s32er-leave operation 82#define SUPPORT_EXT_INTERLEAVE (NAND_EXT_INTERLEAVE & NandStorageInfo.OperationOpt) 83 84//define if the nand flash system can support randomizer 85#define SUPPORT_RANDOM (NAND_RANDOM & NandStorageInfo.OperationOpt) 86 87//define if the nand flash system can support read retry 88#define SUPPORT_READ_RETRY (NAND_READ_RETRY & NandStorageInfo.OperationOpt) 89 90//define if the nand flash system can support read unique id 91#define SUPPORT_READ_UNIQUE_ID (NAND_READ_UNIQUE_ID & NandStorageInfo.OperationOpt) 92 93//define if the nand flash system can support bank align 94#define SUPPORT_ALIGN_NAND_BNK (!(NAND_PAGE_ADR_NO_SKIP & NandStorageInfo.OperationOpt)) 95 96//define the count of the nand flash DIE in a nand flash chip 97#define DIE_CNT_OF_CHIP (NandStorageInfo.DieCntPerChip) 98 99//define the count of the nand flash bank in a nand flas hchip 100#define BNK_CNT_OF_CHIP (NandStorageInfo.BankCntPerChip) 101 102//define the Rb connect Mode 103#define RB_CONNECT_MODE (NandStorageInfo.RbConnectMode) 104 105//define the count of the total nand flash bank in the nand flash storage system 106#define TOTAL_BANK_CNT (NandStorageInfo.BankCntPerChip * NandStorageInfo.ChipCnt) 107 108//define the count of the physical block in a nand flash DIE 109#define BLOCK_CNT_OF_DIE (NandStorageInfo.BlkCntPerDie) 110 111//define the count of the nand flash plane in a nand flash DIE 112#define PLANE_CNT_OF_DIE (NandStorageInfo.PlaneCntPerDie) 113 114//define the count of the physical page in a physical block 115#define PAGE_CNT_OF_PHY_BLK (NandStorageInfo.PageCntPerPhyBlk) 116 117//define the information of the nand chip connect in the nand storage system 118#define CHIP_CONNECT_INFO (NandStorageInfo.ChipConnectInfo) 119 120//define the ReadRetryType of the nand chip connect in the nand storage system 121#define READ_RETRY_TYPE (NandStorageInfo.ReadRetryType) 122 123//define the ReadRetryType of the nand chip connect in the nand storage system 124#define READ_RETRY_MODE ((READ_RETRY_TYPE>>16)&0xff) 125 126//define the ReadRetryType of the nand chip connect in the nand storage system 127#define READ_RETRY_CYCLE ((READ_RETRY_TYPE>>8)&0xff) 128 129//define the ReadRetryType of the nand chip connect in the nand storage system 130#define READ_RETRY_REG_CNT ((READ_RETRY_TYPE>>0)&0xff) 131 132//define the nand flash access frequence parameter 133#define NAND_ACCESS_FREQUENCE (NandStorageInfo.FrequencePar) 134 135#define BAD_BLK_FLAG_PST (NandStorageInfo.OptPhyOpPar.BadBlockFlagPosition) 136 137//sync bank with chip mode, need wait whole chip true ready 138#define SYNC_CHIP_MODE 0x00 139 140//sync bank with bank mode, only check the status of the bank to wait bank ready 141#define SYNC_BANK_MODE 0x01 142 143//define the page cache for physical module processing page data 144#define PHY_TMP_PAGE_CACHE (PageCachePool.PageCache0) 145 146//define the spare data cache for physical module processing spare area data 147#define PHY_TMP_SPARE_CACHE (PageCachePool.SpareCache) 148//============================================================================== 149// define the functions __s32erface for the physic operation module 150//============================================================================== 151 152/* 153************************************************************************************************************************ 154* INIT NAND FLASH DRIVER PHYSICAL MODULE 155* 156* Description: init nand flash driver physical module. 157* 158* Aguments : none 159* 160* Returns : the resutl of initial. 161* = 0 initiate successful; 162* = -1 initiate failed. 163************************************************************************************************************************ 164*/ 165__s32 PHY_Init(void); 166__s32 PHY_ChangeMode(__u8 serial_mode); 167 168/* 169************************************************************************************************************************ 170* NAND FLASH DRIVER PHYSICAL MODULE EXIT 171* 172* Description: nand flash driver physical module exit. 173* 174* Aguments : none 175* 176* Returns : the resutl of exit. 177* = 0 exit successful; 178* = -1 exit failed. 179************************************************************************************************************************ 180*/ 181__s32 PHY_Exit(void); 182 183 184/* 185************************************************************************************************************************ 186* RESET ONE NAND FLASH CHIP 187* 188*Description: Reset the given nand chip; 189* 190*Arguments : nChip the chip select number, which need be reset. 191* 192*Return : the result of chip reset; 193* = 0 reset nand chip successful; 194* = -1 reset nand chip failed. 195************************************************************************************************************************ 196*/ 197__s32 PHY_ResetChip(__u32 nChip); 198 199 200/* 201************************************************************************************************************************ 202* READ NAND FLASH ID 203* 204*Description: Read nand flash ID from the given nand chip. 205* 206*Arguments : nChip the chip number whoes ID need be read; 207* pChipID the po__s32er to the chip ID buffer. 208* 209*Return : read nand chip ID result; 210* = 0 read chip ID successful, the chip ID has been stored in given buffer; 211* = -1 read chip ID failed. 212************************************************************************************************************************ 213*/ 214__s32 PHY_ReadNandId(__s32 nChip, void *pChipID); 215__s32 PHY_ReadNandUniqueId(__s32 bank, void *pChipID); 216 217 218/* 219************************************************************************************************************************ 220* CHECK WRITE PROTECT STATUS 221* 222*Description: check the status of write protect. 223* 224*Arguments : nChip the number of chip, which nand chip need be checked. 225* 226*Return : the result of status check; 227* = 0 the nand flash is not write proteced; 228* = 1 the nand flash is write proteced; 229* = -1 check status failed. 230************************************************************************************************************************ 231*/ 232__s32 PHY_CheckWp(__u32 nChip); 233 234 235/* 236************************************************************************************************************************ 237* PHYSICAL BLOCK ERASE 238* 239*Description: Erase one nand flash physical block. 240* 241*Arguments : pBlkAdr the parameter of the physical block which need be erased. 242* 243*Return : the result of the block erase; 244* = 0 erase physical block successful; 245* = -1 erase physical block failed. 246************************************************************************************************************************ 247*/ 248__s32 PHY_BlockErase(struct __PhysicOpPara_t *pBlkAdr); 249 250 251/* 252************************************************************************************************************************ 253* READ NAND FLASH PHYSICAL PAGE DATA 254* 255*Description: Read a page from a nand flash physical page to buffer. 256* 257*Arguments : pPageAdr the po__s32er to the accessed page parameter. 258* 259*Return : the result of physical page read; 260* = 0 read physical page successful; 261* > 0 read physical page successful, but need do some process; 262* < 0 read physical page failed. 263************************************************************************************************************************ 264*/ 265__s32 PHY_PageRead(struct __PhysicOpPara_t *pPageAdr); 266 267 268__s32 PHY_PageReadSpare(struct __PhysicOpPara_t *pPageAdr); 269 270/* 271************************************************************************************************************************ 272* WRITE NAND FLASH PHYSICAL PAGE DATA 273* 274*Description: Write a page from buffer to a nand flash physical page. 275* 276*Arguments : pPageAdr the po__s32er to the accessed page parameter. 277* 278*Return : The result of the page write; 279* = 0 page write successful; 280* > 0 page write successful, but need do some process; 281* < 0 page write failed. 282************************************************************************************************************************ 283*/ 284__s32 PHY_PageWrite(struct __PhysicOpPara_t *pPageAdr); 285 286 287/* 288************************************************************************************************************************ 289* PHYSIC PAGE COPY-BACK 290* 291*Description: copy one physical page from one physical block to another physical block. 292* 293*Arguments : pSrcPage the parameter of the source page which need be copied; 294* pDstPage the parameter of the destination page which copied to. 295* 296*Return : the result of the page copy-back; 297* = 0 page copy-back successful; 298* = -1 page copy-back failed. 299************************************************************************************************************************ 300*/ 301__s32 PHY_PageCopyback(struct __PhysicOpPara_t *pSrcPage, struct __PhysicOpPara_t *pDstPage); 302 303 304/* 305************************************************************************************************************************ 306* SYNCH NAND FLASH PHYSIC OPERATION 307* 308*Description: Synch nand flash operation, check nand flash program/erase operation status. 309* 310*Arguments : nBank the number of the bank which need be synchronized; 311* bMode the type of synch, 312* = 0 synch the chip which the bank belonged to, wait the whole chip 313* to be ready, and report status. if the chip support cacheprogram, 314* need check if the chip is true ready; 315* = 1 only synch the the bank, wait the bank ready and report the status, 316* if the chip support cache program, need not check if the cache is 317* true ready. 318* 319*Return : the result of synch; 320* = 0 synch nand flash successful, nand operation ok; 321* = -1 synch nand flash failed. 322************************************************************************************************************************ 323*/ 324__s32 PHY_SynchBank(__u32 nBank, __u32 bMode); 325 326 327__s32 PHY_GetDefaultParam(__u32 bank); 328__s32 PHY_SetDefaultParam(__u32 bank); 329 330__s32 PHY_ScanDDRParam(void); 331 332#endif //ifnedf __NAND_PHYSIC_H__ 333 334 335 336