/arch/x86/kernel/process.c

https://bitbucket.org/ndreys/linux-sunxi · C · 659 lines · 433 code · 87 blank · 139 comment · 69 complexity · 4cd57fff3b97502cbb37f804990e5e69 MD5 · raw file

  1. #include <linux/errno.h>
  2. #include <linux/kernel.h>
  3. #include <linux/mm.h>
  4. #include <linux/smp.h>
  5. #include <linux/prctl.h>
  6. #include <linux/slab.h>
  7. #include <linux/sched.h>
  8. #include <linux/module.h>
  9. #include <linux/pm.h>
  10. #include <linux/clockchips.h>
  11. #include <linux/random.h>
  12. #include <linux/user-return-notifier.h>
  13. #include <linux/dmi.h>
  14. #include <linux/utsname.h>
  15. #include <trace/events/power.h>
  16. #include <linux/hw_breakpoint.h>
  17. #include <asm/cpu.h>
  18. #include <asm/system.h>
  19. #include <asm/apic.h>
  20. #include <asm/syscalls.h>
  21. #include <asm/idle.h>
  22. #include <asm/uaccess.h>
  23. #include <asm/i387.h>
  24. #include <asm/debugreg.h>
  25. struct kmem_cache *task_xstate_cachep;
  26. EXPORT_SYMBOL_GPL(task_xstate_cachep);
  27. int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
  28. {
  29. int ret;
  30. *dst = *src;
  31. if (fpu_allocated(&src->thread.fpu)) {
  32. memset(&dst->thread.fpu, 0, sizeof(dst->thread.fpu));
  33. ret = fpu_alloc(&dst->thread.fpu);
  34. if (ret)
  35. return ret;
  36. fpu_copy(&dst->thread.fpu, &src->thread.fpu);
  37. }
  38. return 0;
  39. }
  40. void free_thread_xstate(struct task_struct *tsk)
  41. {
  42. fpu_free(&tsk->thread.fpu);
  43. }
  44. void free_thread_info(struct thread_info *ti)
  45. {
  46. free_thread_xstate(ti->task);
  47. free_pages((unsigned long)ti, get_order(THREAD_SIZE));
  48. }
  49. void arch_task_cache_init(void)
  50. {
  51. task_xstate_cachep =
  52. kmem_cache_create("task_xstate", xstate_size,
  53. __alignof__(union thread_xstate),
  54. SLAB_PANIC | SLAB_NOTRACK, NULL);
  55. }
  56. /*
  57. * Free current thread data structures etc..
  58. */
  59. void exit_thread(void)
  60. {
  61. struct task_struct *me = current;
  62. struct thread_struct *t = &me->thread;
  63. unsigned long *bp = t->io_bitmap_ptr;
  64. if (bp) {
  65. struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
  66. t->io_bitmap_ptr = NULL;
  67. clear_thread_flag(TIF_IO_BITMAP);
  68. /*
  69. * Careful, clear this in the TSS too:
  70. */
  71. memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
  72. t->io_bitmap_max = 0;
  73. put_cpu();
  74. kfree(bp);
  75. }
  76. }
  77. void show_regs(struct pt_regs *regs)
  78. {
  79. show_registers(regs);
  80. show_trace(NULL, regs, (unsigned long *)kernel_stack_pointer(regs), 0);
  81. }
  82. void show_regs_common(void)
  83. {
  84. const char *vendor, *product, *board;
  85. vendor = dmi_get_system_info(DMI_SYS_VENDOR);
  86. if (!vendor)
  87. vendor = "";
  88. product = dmi_get_system_info(DMI_PRODUCT_NAME);
  89. if (!product)
  90. product = "";
  91. /* Board Name is optional */
  92. board = dmi_get_system_info(DMI_BOARD_NAME);
  93. printk(KERN_CONT "\n");
  94. printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s",
  95. current->pid, current->comm, print_tainted(),
  96. init_utsname()->release,
  97. (int)strcspn(init_utsname()->version, " "),
  98. init_utsname()->version);
  99. printk(KERN_CONT " %s %s", vendor, product);
  100. if (board)
  101. printk(KERN_CONT "/%s", board);
  102. printk(KERN_CONT "\n");
  103. }
  104. void flush_thread(void)
  105. {
  106. struct task_struct *tsk = current;
  107. flush_ptrace_hw_breakpoint(tsk);
  108. memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
  109. /*
  110. * Forget coprocessor state..
  111. */
  112. tsk->fpu_counter = 0;
  113. clear_fpu(tsk);
  114. clear_used_math();
  115. }
  116. static void hard_disable_TSC(void)
  117. {
  118. write_cr4(read_cr4() | X86_CR4_TSD);
  119. }
  120. void disable_TSC(void)
  121. {
  122. preempt_disable();
  123. if (!test_and_set_thread_flag(TIF_NOTSC))
  124. /*
  125. * Must flip the CPU state synchronously with
  126. * TIF_NOTSC in the current running context.
  127. */
  128. hard_disable_TSC();
  129. preempt_enable();
  130. }
  131. static void hard_enable_TSC(void)
  132. {
  133. write_cr4(read_cr4() & ~X86_CR4_TSD);
  134. }
  135. static void enable_TSC(void)
  136. {
  137. preempt_disable();
  138. if (test_and_clear_thread_flag(TIF_NOTSC))
  139. /*
  140. * Must flip the CPU state synchronously with
  141. * TIF_NOTSC in the current running context.
  142. */
  143. hard_enable_TSC();
  144. preempt_enable();
  145. }
  146. int get_tsc_mode(unsigned long adr)
  147. {
  148. unsigned int val;
  149. if (test_thread_flag(TIF_NOTSC))
  150. val = PR_TSC_SIGSEGV;
  151. else
  152. val = PR_TSC_ENABLE;
  153. return put_user(val, (unsigned int __user *)adr);
  154. }
  155. int set_tsc_mode(unsigned int val)
  156. {
  157. if (val == PR_TSC_SIGSEGV)
  158. disable_TSC();
  159. else if (val == PR_TSC_ENABLE)
  160. enable_TSC();
  161. else
  162. return -EINVAL;
  163. return 0;
  164. }
  165. void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
  166. struct tss_struct *tss)
  167. {
  168. struct thread_struct *prev, *next;
  169. prev = &prev_p->thread;
  170. next = &next_p->thread;
  171. if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
  172. test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
  173. unsigned long debugctl = get_debugctlmsr();
  174. debugctl &= ~DEBUGCTLMSR_BTF;
  175. if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
  176. debugctl |= DEBUGCTLMSR_BTF;
  177. update_debugctlmsr(debugctl);
  178. }
  179. if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
  180. test_tsk_thread_flag(next_p, TIF_NOTSC)) {
  181. /* prev and next are different */
  182. if (test_tsk_thread_flag(next_p, TIF_NOTSC))
  183. hard_disable_TSC();
  184. else
  185. hard_enable_TSC();
  186. }
  187. if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
  188. /*
  189. * Copy the relevant range of the IO bitmap.
  190. * Normally this is 128 bytes or less:
  191. */
  192. memcpy(tss->io_bitmap, next->io_bitmap_ptr,
  193. max(prev->io_bitmap_max, next->io_bitmap_max));
  194. } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
  195. /*
  196. * Clear any possible leftover bits:
  197. */
  198. memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
  199. }
  200. propagate_user_return_notify(prev_p, next_p);
  201. }
  202. int sys_fork(struct pt_regs *regs)
  203. {
  204. return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
  205. }
  206. /*
  207. * This is trivial, and on the face of it looks like it
  208. * could equally well be done in user mode.
  209. *
  210. * Not so, for quite unobvious reasons - register pressure.
  211. * In user mode vfork() cannot have a stack frame, and if
  212. * done by calling the "clone()" system call directly, you
  213. * do not have enough call-clobbered registers to hold all
  214. * the information you need.
  215. */
  216. int sys_vfork(struct pt_regs *regs)
  217. {
  218. return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
  219. NULL, NULL);
  220. }
  221. long
  222. sys_clone(unsigned long clone_flags, unsigned long newsp,
  223. void __user *parent_tid, void __user *child_tid, struct pt_regs *regs)
  224. {
  225. if (!newsp)
  226. newsp = regs->sp;
  227. return do_fork(clone_flags, newsp, regs, 0, parent_tid, child_tid);
  228. }
  229. /*
  230. * This gets run with %si containing the
  231. * function to call, and %di containing
  232. * the "args".
  233. */
  234. extern void kernel_thread_helper(void);
  235. /*
  236. * Create a kernel thread
  237. */
  238. int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
  239. {
  240. struct pt_regs regs;
  241. memset(&regs, 0, sizeof(regs));
  242. regs.si = (unsigned long) fn;
  243. regs.di = (unsigned long) arg;
  244. #ifdef CONFIG_X86_32
  245. regs.ds = __USER_DS;
  246. regs.es = __USER_DS;
  247. regs.fs = __KERNEL_PERCPU;
  248. regs.gs = __KERNEL_STACK_CANARY;
  249. #else
  250. regs.ss = __KERNEL_DS;
  251. #endif
  252. regs.orig_ax = -1;
  253. regs.ip = (unsigned long) kernel_thread_helper;
  254. regs.cs = __KERNEL_CS | get_kernel_rpl();
  255. regs.flags = X86_EFLAGS_IF | 0x2;
  256. /* Ok, create the new process.. */
  257. return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
  258. }
  259. EXPORT_SYMBOL(kernel_thread);
  260. /*
  261. * sys_execve() executes a new program.
  262. */
  263. long sys_execve(const char __user *name,
  264. const char __user *const __user *argv,
  265. const char __user *const __user *envp, struct pt_regs *regs)
  266. {
  267. long error;
  268. char *filename;
  269. filename = getname(name);
  270. error = PTR_ERR(filename);
  271. if (IS_ERR(filename))
  272. return error;
  273. error = do_execve(filename, argv, envp, regs);
  274. #ifdef CONFIG_X86_32
  275. if (error == 0) {
  276. /* Make sure we don't return using sysenter.. */
  277. set_thread_flag(TIF_IRET);
  278. }
  279. #endif
  280. putname(filename);
  281. return error;
  282. }
  283. /*
  284. * Idle related variables and functions
  285. */
  286. unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
  287. EXPORT_SYMBOL(boot_option_idle_override);
  288. /*
  289. * Powermanagement idle function, if any..
  290. */
  291. void (*pm_idle)(void);
  292. #ifdef CONFIG_APM_MODULE
  293. EXPORT_SYMBOL(pm_idle);
  294. #endif
  295. static inline int hlt_use_halt(void)
  296. {
  297. return 1;
  298. }
  299. /*
  300. * We use this if we don't have any better
  301. * idle routine..
  302. */
  303. void default_idle(void)
  304. {
  305. if (hlt_use_halt()) {
  306. trace_power_start(POWER_CSTATE, 1, smp_processor_id());
  307. trace_cpu_idle(1, smp_processor_id());
  308. current_thread_info()->status &= ~TS_POLLING;
  309. /*
  310. * TS_POLLING-cleared state must be visible before we
  311. * test NEED_RESCHED:
  312. */
  313. smp_mb();
  314. if (!need_resched())
  315. safe_halt(); /* enables interrupts racelessly */
  316. else
  317. local_irq_enable();
  318. current_thread_info()->status |= TS_POLLING;
  319. trace_power_end(smp_processor_id());
  320. trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
  321. } else {
  322. local_irq_enable();
  323. /* loop is done by the caller */
  324. cpu_relax();
  325. }
  326. }
  327. #ifdef CONFIG_APM_MODULE
  328. EXPORT_SYMBOL(default_idle);
  329. #endif
  330. void stop_this_cpu(void *dummy)
  331. {
  332. local_irq_disable();
  333. /*
  334. * Remove this CPU:
  335. */
  336. set_cpu_online(smp_processor_id(), false);
  337. disable_local_APIC();
  338. for (;;) {
  339. if (hlt_works(smp_processor_id()))
  340. halt();
  341. }
  342. }
  343. static void do_nothing(void *unused)
  344. {
  345. }
  346. /*
  347. * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
  348. * pm_idle and update to new pm_idle value. Required while changing pm_idle
  349. * handler on SMP systems.
  350. *
  351. * Caller must have changed pm_idle to the new value before the call. Old
  352. * pm_idle value will not be used by any CPU after the return of this function.
  353. */
  354. void cpu_idle_wait(void)
  355. {
  356. smp_mb();
  357. /* kick all the CPUs so that they exit out of pm_idle */
  358. smp_call_function(do_nothing, NULL, 1);
  359. }
  360. EXPORT_SYMBOL_GPL(cpu_idle_wait);
  361. /*
  362. * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
  363. * which can obviate IPI to trigger checking of need_resched.
  364. * We execute MONITOR against need_resched and enter optimized wait state
  365. * through MWAIT. Whenever someone changes need_resched, we would be woken
  366. * up from MWAIT (without an IPI).
  367. *
  368. * New with Core Duo processors, MWAIT can take some hints based on CPU
  369. * capability.
  370. */
  371. void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
  372. {
  373. if (!need_resched()) {
  374. if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR))
  375. clflush((void *)&current_thread_info()->flags);
  376. __monitor((void *)&current_thread_info()->flags, 0, 0);
  377. smp_mb();
  378. if (!need_resched())
  379. __mwait(ax, cx);
  380. }
  381. }
  382. /* Default MONITOR/MWAIT with no hints, used for default C1 state */
  383. static void mwait_idle(void)
  384. {
  385. if (!need_resched()) {
  386. trace_power_start(POWER_CSTATE, 1, smp_processor_id());
  387. trace_cpu_idle(1, smp_processor_id());
  388. if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR))
  389. clflush((void *)&current_thread_info()->flags);
  390. __monitor((void *)&current_thread_info()->flags, 0, 0);
  391. smp_mb();
  392. if (!need_resched())
  393. __sti_mwait(0, 0);
  394. else
  395. local_irq_enable();
  396. trace_power_end(smp_processor_id());
  397. trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
  398. } else
  399. local_irq_enable();
  400. }
  401. /*
  402. * On SMP it's slightly faster (but much more power-consuming!)
  403. * to poll the ->work.need_resched flag instead of waiting for the
  404. * cross-CPU IPI to arrive. Use this option with caution.
  405. */
  406. static void poll_idle(void)
  407. {
  408. trace_power_start(POWER_CSTATE, 0, smp_processor_id());
  409. trace_cpu_idle(0, smp_processor_id());
  410. local_irq_enable();
  411. while (!need_resched())
  412. cpu_relax();
  413. trace_power_end(smp_processor_id());
  414. trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
  415. }
  416. /*
  417. * mwait selection logic:
  418. *
  419. * It depends on the CPU. For AMD CPUs that support MWAIT this is
  420. * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
  421. * then depend on a clock divisor and current Pstate of the core. If
  422. * all cores of a processor are in halt state (C1) the processor can
  423. * enter the C1E (C1 enhanced) state. If mwait is used this will never
  424. * happen.
  425. *
  426. * idle=mwait overrides this decision and forces the usage of mwait.
  427. */
  428. #define MWAIT_INFO 0x05
  429. #define MWAIT_ECX_EXTENDED_INFO 0x01
  430. #define MWAIT_EDX_C1 0xf0
  431. int mwait_usable(const struct cpuinfo_x86 *c)
  432. {
  433. u32 eax, ebx, ecx, edx;
  434. if (boot_option_idle_override == IDLE_FORCE_MWAIT)
  435. return 1;
  436. if (c->cpuid_level < MWAIT_INFO)
  437. return 0;
  438. cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
  439. /* Check, whether EDX has extended info about MWAIT */
  440. if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
  441. return 1;
  442. /*
  443. * edx enumeratios MONITOR/MWAIT extensions. Check, whether
  444. * C1 supports MWAIT
  445. */
  446. return (edx & MWAIT_EDX_C1);
  447. }
  448. bool amd_e400_c1e_detected;
  449. EXPORT_SYMBOL(amd_e400_c1e_detected);
  450. static cpumask_var_t amd_e400_c1e_mask;
  451. void amd_e400_remove_cpu(int cpu)
  452. {
  453. if (amd_e400_c1e_mask != NULL)
  454. cpumask_clear_cpu(cpu, amd_e400_c1e_mask);
  455. }
  456. /*
  457. * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
  458. * pending message MSR. If we detect C1E, then we handle it the same
  459. * way as C3 power states (local apic timer and TSC stop)
  460. */
  461. static void amd_e400_idle(void)
  462. {
  463. if (need_resched())
  464. return;
  465. if (!amd_e400_c1e_detected) {
  466. u32 lo, hi;
  467. rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
  468. if (lo & K8_INTP_C1E_ACTIVE_MASK) {
  469. amd_e400_c1e_detected = true;
  470. if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
  471. mark_tsc_unstable("TSC halt in AMD C1E");
  472. printk(KERN_INFO "System has AMD C1E enabled\n");
  473. }
  474. }
  475. if (amd_e400_c1e_detected) {
  476. int cpu = smp_processor_id();
  477. if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) {
  478. cpumask_set_cpu(cpu, amd_e400_c1e_mask);
  479. /*
  480. * Force broadcast so ACPI can not interfere.
  481. */
  482. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
  483. &cpu);
  484. printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
  485. cpu);
  486. }
  487. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
  488. default_idle();
  489. /*
  490. * The switch back from broadcast mode needs to be
  491. * called with interrupts disabled.
  492. */
  493. local_irq_disable();
  494. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
  495. local_irq_enable();
  496. } else
  497. default_idle();
  498. }
  499. void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
  500. {
  501. #ifdef CONFIG_SMP
  502. if (pm_idle == poll_idle && smp_num_siblings > 1) {
  503. printk_once(KERN_WARNING "WARNING: polling idle and HT enabled,"
  504. " performance may degrade.\n");
  505. }
  506. #endif
  507. if (pm_idle)
  508. return;
  509. if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
  510. /*
  511. * One CPU supports mwait => All CPUs supports mwait
  512. */
  513. printk(KERN_INFO "using mwait in idle threads.\n");
  514. pm_idle = mwait_idle;
  515. } else if (cpu_has_amd_erratum(amd_erratum_400)) {
  516. /* E400: APIC timer interrupt does not wake up CPU from C1e */
  517. printk(KERN_INFO "using AMD E400 aware idle routine\n");
  518. pm_idle = amd_e400_idle;
  519. } else
  520. pm_idle = default_idle;
  521. }
  522. void __init init_amd_e400_c1e_mask(void)
  523. {
  524. /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
  525. if (pm_idle == amd_e400_idle)
  526. zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL);
  527. }
  528. static int __init idle_setup(char *str)
  529. {
  530. if (!str)
  531. return -EINVAL;
  532. if (!strcmp(str, "poll")) {
  533. printk("using polling idle threads.\n");
  534. pm_idle = poll_idle;
  535. boot_option_idle_override = IDLE_POLL;
  536. } else if (!strcmp(str, "mwait")) {
  537. boot_option_idle_override = IDLE_FORCE_MWAIT;
  538. WARN_ONCE(1, "\"idle=mwait\" will be removed in 2012\n");
  539. } else if (!strcmp(str, "halt")) {
  540. /*
  541. * When the boot option of idle=halt is added, halt is
  542. * forced to be used for CPU idle. In such case CPU C2/C3
  543. * won't be used again.
  544. * To continue to load the CPU idle driver, don't touch
  545. * the boot_option_idle_override.
  546. */
  547. pm_idle = default_idle;
  548. boot_option_idle_override = IDLE_HALT;
  549. } else if (!strcmp(str, "nomwait")) {
  550. /*
  551. * If the boot option of "idle=nomwait" is added,
  552. * it means that mwait will be disabled for CPU C2/C3
  553. * states. In such case it won't touch the variable
  554. * of boot_option_idle_override.
  555. */
  556. boot_option_idle_override = IDLE_NOMWAIT;
  557. } else
  558. return -1;
  559. return 0;
  560. }
  561. early_param("idle", idle_setup);
  562. unsigned long arch_align_stack(unsigned long sp)
  563. {
  564. if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
  565. sp -= get_random_int() % 8192;
  566. return sp & ~0xf;
  567. }
  568. unsigned long arch_randomize_brk(struct mm_struct *mm)
  569. {
  570. unsigned long range_end = mm->brk + 0x02000000;
  571. return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
  572. }