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/arch/x86/kernel/apb_timer.c

https://bitbucket.org/ndreys/linux-sunxi
C | 701 lines | 488 code | 95 blank | 118 comment | 53 complexity | 9bc88f730996aafdad95254f5c7c0909 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1/*
  2 * apb_timer.c: Driver for Langwell APB timers
  3 *
  4 * (C) Copyright 2009 Intel Corporation
  5 * Author: Jacob Pan (jacob.jun.pan@intel.com)
  6 *
  7 * This program is free software; you can redistribute it and/or
  8 * modify it under the terms of the GNU General Public License
  9 * as published by the Free Software Foundation; version 2
 10 * of the License.
 11 *
 12 * Note:
 13 * Langwell is the south complex of Intel Moorestown MID platform. There are
 14 * eight external timers in total that can be used by the operating system.
 15 * The timer information, such as frequency and addresses, is provided to the
 16 * OS via SFI tables.
 17 * Timer interrupts are routed via FW/HW emulated IOAPIC independently via
 18 * individual redirection table entries (RTE).
 19 * Unlike HPET, there is no master counter, therefore one of the timers are
 20 * used as clocksource. The overall allocation looks like:
 21 *  - timer 0 - NR_CPUs for per cpu timer
 22 *  - one timer for clocksource
 23 *  - one timer for watchdog driver.
 24 * It is also worth notice that APB timer does not support true one-shot mode,
 25 * free-running mode will be used here to emulate one-shot mode.
 26 * APB timer can also be used as broadcast timer along with per cpu local APIC
 27 * timer, but by default APB timer has higher rating than local APIC timers.
 28 */
 29
 30#include <linux/clocksource.h>
 31#include <linux/clockchips.h>
 32#include <linux/delay.h>
 33#include <linux/errno.h>
 34#include <linux/init.h>
 35#include <linux/sysdev.h>
 36#include <linux/slab.h>
 37#include <linux/pm.h>
 38#include <linux/pci.h>
 39#include <linux/sfi.h>
 40#include <linux/interrupt.h>
 41#include <linux/cpu.h>
 42#include <linux/irq.h>
 43
 44#include <asm/fixmap.h>
 45#include <asm/apb_timer.h>
 46#include <asm/mrst.h>
 47
 48#define APBT_MASK			CLOCKSOURCE_MASK(32)
 49#define APBT_SHIFT			22
 50#define APBT_CLOCKEVENT_RATING		110
 51#define APBT_CLOCKSOURCE_RATING		250
 52#define APBT_MIN_DELTA_USEC		200
 53
 54#define EVT_TO_APBT_DEV(evt) container_of(evt, struct apbt_dev, evt)
 55#define APBT_CLOCKEVENT0_NUM   (0)
 56#define APBT_CLOCKEVENT1_NUM   (1)
 57#define APBT_CLOCKSOURCE_NUM   (2)
 58
 59static unsigned long apbt_address;
 60static int apb_timer_block_enabled;
 61static void __iomem *apbt_virt_address;
 62static int phy_cs_timer_id;
 63
 64/*
 65 * Common DW APB timer info
 66 */
 67static uint64_t apbt_freq;
 68
 69static void apbt_set_mode(enum clock_event_mode mode,
 70			  struct clock_event_device *evt);
 71static int apbt_next_event(unsigned long delta,
 72			   struct clock_event_device *evt);
 73static cycle_t apbt_read_clocksource(struct clocksource *cs);
 74static void apbt_restart_clocksource(struct clocksource *cs);
 75
 76struct apbt_dev {
 77	struct clock_event_device evt;
 78	unsigned int num;
 79	int cpu;
 80	unsigned int irq;
 81	unsigned int tick;
 82	unsigned int count;
 83	unsigned int flags;
 84	char name[10];
 85};
 86
 87static DEFINE_PER_CPU(struct apbt_dev, cpu_apbt_dev);
 88
 89#ifdef CONFIG_SMP
 90static unsigned int apbt_num_timers_used;
 91static struct apbt_dev *apbt_devs;
 92#endif
 93
 94static	inline unsigned long apbt_readl_reg(unsigned long a)
 95{
 96	return readl(apbt_virt_address + a);
 97}
 98
 99static inline void apbt_writel_reg(unsigned long d, unsigned long a)
100{
101	writel(d, apbt_virt_address + a);
102}
103
104static inline unsigned long apbt_readl(int n, unsigned long a)
105{
106	return readl(apbt_virt_address + a + n * APBTMRS_REG_SIZE);
107}
108
109static inline void apbt_writel(int n, unsigned long d, unsigned long a)
110{
111	writel(d, apbt_virt_address + a + n * APBTMRS_REG_SIZE);
112}
113
114static inline void apbt_set_mapping(void)
115{
116	struct sfi_timer_table_entry *mtmr;
117
118	if (apbt_virt_address) {
119		pr_debug("APBT base already mapped\n");
120		return;
121	}
122	mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM);
123	if (mtmr == NULL) {
124		printk(KERN_ERR "Failed to get MTMR %d from SFI\n",
125		       APBT_CLOCKEVENT0_NUM);
126		return;
127	}
128	apbt_address = (unsigned long)mtmr->phys_addr;
129	if (!apbt_address) {
130		printk(KERN_WARNING "No timer base from SFI, use default\n");
131		apbt_address = APBT_DEFAULT_BASE;
132	}
133	apbt_virt_address = ioremap_nocache(apbt_address, APBT_MMAP_SIZE);
134	if (apbt_virt_address) {
135		pr_debug("Mapped APBT physical addr %p at virtual addr %p\n",\
136			 (void *)apbt_address, (void *)apbt_virt_address);
137	} else {
138		pr_debug("Failed mapping APBT phy address at %p\n",\
139			 (void *)apbt_address);
140		goto panic_noapbt;
141	}
142	apbt_freq = mtmr->freq_hz / USEC_PER_SEC;
143	sfi_free_mtmr(mtmr);
144
145	/* Now figure out the physical timer id for clocksource device */
146	mtmr = sfi_get_mtmr(APBT_CLOCKSOURCE_NUM);
147	if (mtmr == NULL)
148		goto panic_noapbt;
149
150	/* Now figure out the physical timer id */
151	phy_cs_timer_id = (unsigned int)(mtmr->phys_addr & 0xff)
152		/ APBTMRS_REG_SIZE;
153	pr_debug("Use timer %d for clocksource\n", phy_cs_timer_id);
154	return;
155
156panic_noapbt:
157	panic("Failed to setup APB system timer\n");
158
159}
160
161static inline void apbt_clear_mapping(void)
162{
163	iounmap(apbt_virt_address);
164	apbt_virt_address = NULL;
165}
166
167/*
168 * APBT timer interrupt enable / disable
169 */
170static inline int is_apbt_capable(void)
171{
172	return apbt_virt_address ? 1 : 0;
173}
174
175static struct clocksource clocksource_apbt = {
176	.name		= "apbt",
177	.rating		= APBT_CLOCKSOURCE_RATING,
178	.read		= apbt_read_clocksource,
179	.mask		= APBT_MASK,
180	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
181	.resume		= apbt_restart_clocksource,
182};
183
184/* boot APB clock event device */
185static struct clock_event_device apbt_clockevent = {
186	.name		= "apbt0",
187	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
188	.set_mode	= apbt_set_mode,
189	.set_next_event = apbt_next_event,
190	.shift		= APBT_SHIFT,
191	.irq		= 0,
192	.rating		= APBT_CLOCKEVENT_RATING,
193};
194
195/*
196 * start count down from 0xffff_ffff. this is done by toggling the enable bit
197 * then load initial load count to ~0.
198 */
199static void apbt_start_counter(int n)
200{
201	unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL);
202
203	ctrl &= ~APBTMR_CONTROL_ENABLE;
204	apbt_writel(n, ctrl, APBTMR_N_CONTROL);
205	apbt_writel(n, ~0, APBTMR_N_LOAD_COUNT);
206	/* enable, mask interrupt */
207	ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
208	ctrl |= (APBTMR_CONTROL_ENABLE | APBTMR_CONTROL_INT);
209	apbt_writel(n, ctrl, APBTMR_N_CONTROL);
210	/* read it once to get cached counter value initialized */
211	apbt_read_clocksource(&clocksource_apbt);
212}
213
214static irqreturn_t apbt_interrupt_handler(int irq, void *data)
215{
216	struct apbt_dev *dev = (struct apbt_dev *)data;
217	struct clock_event_device *aevt = &dev->evt;
218
219	if (!aevt->event_handler) {
220		printk(KERN_INFO "Spurious APBT timer interrupt on %d\n",
221		       dev->num);
222		return IRQ_NONE;
223	}
224	aevt->event_handler(aevt);
225	return IRQ_HANDLED;
226}
227
228static void apbt_restart_clocksource(struct clocksource *cs)
229{
230	apbt_start_counter(phy_cs_timer_id);
231}
232
233static void apbt_enable_int(int n)
234{
235	unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL);
236	/* clear pending intr */
237	apbt_readl(n, APBTMR_N_EOI);
238	ctrl &= ~APBTMR_CONTROL_INT;
239	apbt_writel(n, ctrl, APBTMR_N_CONTROL);
240}
241
242static void apbt_disable_int(int n)
243{
244	unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL);
245
246	ctrl |= APBTMR_CONTROL_INT;
247	apbt_writel(n, ctrl, APBTMR_N_CONTROL);
248}
249
250
251static int __init apbt_clockevent_register(void)
252{
253	struct sfi_timer_table_entry *mtmr;
254	struct apbt_dev *adev = &__get_cpu_var(cpu_apbt_dev);
255
256	mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM);
257	if (mtmr == NULL) {
258		printk(KERN_ERR "Failed to get MTMR %d from SFI\n",
259		       APBT_CLOCKEVENT0_NUM);
260		return -ENODEV;
261	}
262
263	/*
264	 * We need to calculate the scaled math multiplication factor for
265	 * nanosecond to apbt tick conversion.
266	 * mult = (nsec/cycle)*2^APBT_SHIFT
267	 */
268	apbt_clockevent.mult = div_sc((unsigned long) mtmr->freq_hz
269				      , NSEC_PER_SEC, APBT_SHIFT);
270
271	/* Calculate the min / max delta */
272	apbt_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
273							   &apbt_clockevent);
274	apbt_clockevent.min_delta_ns = clockevent_delta2ns(
275		APBT_MIN_DELTA_USEC*apbt_freq,
276		&apbt_clockevent);
277	/*
278	 * Start apbt with the boot cpu mask and make it
279	 * global if not used for per cpu timer.
280	 */
281	apbt_clockevent.cpumask = cpumask_of(smp_processor_id());
282	adev->num = smp_processor_id();
283	memcpy(&adev->evt, &apbt_clockevent, sizeof(struct clock_event_device));
284
285	if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) {
286		adev->evt.rating = APBT_CLOCKEVENT_RATING - 100;
287		global_clock_event = &adev->evt;
288		printk(KERN_DEBUG "%s clockevent registered as global\n",
289		       global_clock_event->name);
290	}
291
292	if (request_irq(apbt_clockevent.irq, apbt_interrupt_handler,
293			IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
294			apbt_clockevent.name, adev)) {
295		printk(KERN_ERR "Failed request IRQ for APBT%d\n",
296		       apbt_clockevent.irq);
297	}
298
299	clockevents_register_device(&adev->evt);
300	/* Start APBT 0 interrupts */
301	apbt_enable_int(APBT_CLOCKEVENT0_NUM);
302
303	sfi_free_mtmr(mtmr);
304	return 0;
305}
306
307#ifdef CONFIG_SMP
308
309static void apbt_setup_irq(struct apbt_dev *adev)
310{
311	/* timer0 irq has been setup early */
312	if (adev->irq == 0)
313		return;
314
315	irq_modify_status(adev->irq, 0, IRQ_MOVE_PCNTXT);
316	irq_set_affinity(adev->irq, cpumask_of(adev->cpu));
317	/* APB timer irqs are set up as mp_irqs, timer is edge type */
318	__irq_set_handler(adev->irq, handle_edge_irq, 0, "edge");
319
320	if (system_state == SYSTEM_BOOTING) {
321		if (request_irq(adev->irq, apbt_interrupt_handler,
322					IRQF_TIMER | IRQF_DISABLED |
323					IRQF_NOBALANCING,
324					adev->name, adev)) {
325			printk(KERN_ERR "Failed request IRQ for APBT%d\n",
326			       adev->num);
327		}
328	} else
329		enable_irq(adev->irq);
330}
331
332/* Should be called with per cpu */
333void apbt_setup_secondary_clock(void)
334{
335	struct apbt_dev *adev;
336	struct clock_event_device *aevt;
337	int cpu;
338
339	/* Don't register boot CPU clockevent */
340	cpu = smp_processor_id();
341	if (!cpu)
342		return;
343	/*
344	 * We need to calculate the scaled math multiplication factor for
345	 * nanosecond to apbt tick conversion.
346	 * mult = (nsec/cycle)*2^APBT_SHIFT
347	 */
348	printk(KERN_INFO "Init per CPU clockevent %d\n", cpu);
349	adev = &per_cpu(cpu_apbt_dev, cpu);
350	aevt = &adev->evt;
351
352	memcpy(aevt, &apbt_clockevent, sizeof(*aevt));
353	aevt->cpumask = cpumask_of(cpu);
354	aevt->name = adev->name;
355	aevt->mode = CLOCK_EVT_MODE_UNUSED;
356
357	printk(KERN_INFO "Registering CPU %d clockevent device %s, mask %08x\n",
358	       cpu, aevt->name, *(u32 *)aevt->cpumask);
359
360	apbt_setup_irq(adev);
361
362	clockevents_register_device(aevt);
363
364	apbt_enable_int(cpu);
365
366	return;
367}
368
369/*
370 * this notify handler process CPU hotplug events. in case of S0i3, nonboot
371 * cpus are disabled/enabled frequently, for performance reasons, we keep the
372 * per cpu timer irq registered so that we do need to do free_irq/request_irq.
373 *
374 * TODO: it might be more reliable to directly disable percpu clockevent device
375 * without the notifier chain. currently, cpu 0 may get interrupts from other
376 * cpu timers during the offline process due to the ordering of notification.
377 * the extra interrupt is harmless.
378 */
379static int apbt_cpuhp_notify(struct notifier_block *n,
380			     unsigned long action, void *hcpu)
381{
382	unsigned long cpu = (unsigned long)hcpu;
383	struct apbt_dev *adev = &per_cpu(cpu_apbt_dev, cpu);
384
385	switch (action & 0xf) {
386	case CPU_DEAD:
387		disable_irq(adev->irq);
388		apbt_disable_int(cpu);
389		if (system_state == SYSTEM_RUNNING) {
390			pr_debug("skipping APBT CPU %lu offline\n", cpu);
391		} else if (adev) {
392			pr_debug("APBT clockevent for cpu %lu offline\n", cpu);
393			free_irq(adev->irq, adev);
394		}
395		break;
396	default:
397		pr_debug("APBT notified %lu, no action\n", action);
398	}
399	return NOTIFY_OK;
400}
401
402static __init int apbt_late_init(void)
403{
404	if (mrst_timer_options == MRST_TIMER_LAPIC_APBT ||
405		!apb_timer_block_enabled)
406		return 0;
407	/* This notifier should be called after workqueue is ready */
408	hotcpu_notifier(apbt_cpuhp_notify, -20);
409	return 0;
410}
411fs_initcall(apbt_late_init);
412#else
413
414void apbt_setup_secondary_clock(void) {}
415
416#endif /* CONFIG_SMP */
417
418static void apbt_set_mode(enum clock_event_mode mode,
419			  struct clock_event_device *evt)
420{
421	unsigned long ctrl;
422	uint64_t delta;
423	int timer_num;
424	struct apbt_dev *adev = EVT_TO_APBT_DEV(evt);
425
426	BUG_ON(!apbt_virt_address);
427
428	timer_num = adev->num;
429	pr_debug("%s CPU %d timer %d mode=%d\n",
430		 __func__, first_cpu(*evt->cpumask), timer_num, mode);
431
432	switch (mode) {
433	case CLOCK_EVT_MODE_PERIODIC:
434		delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * apbt_clockevent.mult;
435		delta >>= apbt_clockevent.shift;
436		ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL);
437		ctrl |= APBTMR_CONTROL_MODE_PERIODIC;
438		apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
439		/*
440		 * DW APB p. 46, have to disable timer before load counter,
441		 * may cause sync problem.
442		 */
443		ctrl &= ~APBTMR_CONTROL_ENABLE;
444		apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
445		udelay(1);
446		pr_debug("Setting clock period %d for HZ %d\n", (int)delta, HZ);
447		apbt_writel(timer_num, delta, APBTMR_N_LOAD_COUNT);
448		ctrl |= APBTMR_CONTROL_ENABLE;
449		apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
450		break;
451		/* APB timer does not have one-shot mode, use free running mode */
452	case CLOCK_EVT_MODE_ONESHOT:
453		ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL);
454		/*
455		 * set free running mode, this mode will let timer reload max
456		 * timeout which will give time (3min on 25MHz clock) to rearm
457		 * the next event, therefore emulate the one-shot mode.
458		 */
459		ctrl &= ~APBTMR_CONTROL_ENABLE;
460		ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
461
462		apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
463		/* write again to set free running mode */
464		apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
465
466		/*
467		 * DW APB p. 46, load counter with all 1s before starting free
468		 * running mode.
469		 */
470		apbt_writel(timer_num, ~0, APBTMR_N_LOAD_COUNT);
471		ctrl &= ~APBTMR_CONTROL_INT;
472		ctrl |= APBTMR_CONTROL_ENABLE;
473		apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
474		break;
475
476	case CLOCK_EVT_MODE_UNUSED:
477	case CLOCK_EVT_MODE_SHUTDOWN:
478		apbt_disable_int(timer_num);
479		ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL);
480		ctrl &= ~APBTMR_CONTROL_ENABLE;
481		apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
482		break;
483
484	case CLOCK_EVT_MODE_RESUME:
485		apbt_enable_int(timer_num);
486		break;
487	}
488}
489
490static int apbt_next_event(unsigned long delta,
491			   struct clock_event_device *evt)
492{
493	unsigned long ctrl;
494	int timer_num;
495
496	struct apbt_dev *adev = EVT_TO_APBT_DEV(evt);
497
498	timer_num = adev->num;
499	/* Disable timer */
500	ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL);
501	ctrl &= ~APBTMR_CONTROL_ENABLE;
502	apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
503	/* write new count */
504	apbt_writel(timer_num, delta, APBTMR_N_LOAD_COUNT);
505	ctrl |= APBTMR_CONTROL_ENABLE;
506	apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
507	return 0;
508}
509
510static cycle_t apbt_read_clocksource(struct clocksource *cs)
511{
512	unsigned long current_count;
513
514	current_count = apbt_readl(phy_cs_timer_id, APBTMR_N_CURRENT_VALUE);
515	return (cycle_t)~current_count;
516}
517
518static int apbt_clocksource_register(void)
519{
520	u64 start, now;
521	cycle_t t1;
522
523	/* Start the counter, use timer 2 as source, timer 0/1 for event */
524	apbt_start_counter(phy_cs_timer_id);
525
526	/* Verify whether apbt counter works */
527	t1 = apbt_read_clocksource(&clocksource_apbt);
528	rdtscll(start);
529
530	/*
531	 * We don't know the TSC frequency yet, but waiting for
532	 * 200000 TSC cycles is safe:
533	 * 4 GHz == 50us
534	 * 1 GHz == 200us
535	 */
536	do {
537		rep_nop();
538		rdtscll(now);
539	} while ((now - start) < 200000UL);
540
541	/* APBT is the only always on clocksource, it has to work! */
542	if (t1 == apbt_read_clocksource(&clocksource_apbt))
543		panic("APBT counter not counting. APBT disabled\n");
544
545	clocksource_register_khz(&clocksource_apbt, (u32)apbt_freq*1000);
546
547	return 0;
548}
549
550/*
551 * Early setup the APBT timer, only use timer 0 for booting then switch to
552 * per CPU timer if possible.
553 * returns 1 if per cpu apbt is setup
554 * returns 0 if no per cpu apbt is chosen
555 * panic if set up failed, this is the only platform timer on Moorestown.
556 */
557void __init apbt_time_init(void)
558{
559#ifdef CONFIG_SMP
560	int i;
561	struct sfi_timer_table_entry *p_mtmr;
562	unsigned int percpu_timer;
563	struct apbt_dev *adev;
564#endif
565
566	if (apb_timer_block_enabled)
567		return;
568	apbt_set_mapping();
569	if (apbt_virt_address) {
570		pr_debug("Found APBT version 0x%lx\n",\
571			 apbt_readl_reg(APBTMRS_COMP_VERSION));
572	} else
573		goto out_noapbt;
574	/*
575	 * Read the frequency and check for a sane value, for ESL model
576	 * we extend the possible clock range to allow time scaling.
577	 */
578
579	if (apbt_freq < APBT_MIN_FREQ || apbt_freq > APBT_MAX_FREQ) {
580		pr_debug("APBT has invalid freq 0x%llx\n", apbt_freq);
581		goto out_noapbt;
582	}
583	if (apbt_clocksource_register()) {
584		pr_debug("APBT has failed to register clocksource\n");
585		goto out_noapbt;
586	}
587	if (!apbt_clockevent_register())
588		apb_timer_block_enabled = 1;
589	else {
590		pr_debug("APBT has failed to register clockevent\n");
591		goto out_noapbt;
592	}
593#ifdef CONFIG_SMP
594	/* kernel cmdline disable apb timer, so we will use lapic timers */
595	if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) {
596		printk(KERN_INFO "apbt: disabled per cpu timer\n");
597		return;
598	}
599	pr_debug("%s: %d CPUs online\n", __func__, num_online_cpus());
600	if (num_possible_cpus() <= sfi_mtimer_num) {
601		percpu_timer = 1;
602		apbt_num_timers_used = num_possible_cpus();
603	} else {
604		percpu_timer = 0;
605		apbt_num_timers_used = 1;
606		adev = &per_cpu(cpu_apbt_dev, 0);
607		adev->flags &= ~APBT_DEV_USED;
608	}
609	pr_debug("%s: %d APB timers used\n", __func__, apbt_num_timers_used);
610
611	/* here we set up per CPU timer data structure */
612	apbt_devs = kzalloc(sizeof(struct apbt_dev) * apbt_num_timers_used,
613			    GFP_KERNEL);
614	if (!apbt_devs) {
615		printk(KERN_ERR "Failed to allocate APB timer devices\n");
616		return;
617	}
618	for (i = 0; i < apbt_num_timers_used; i++) {
619		adev = &per_cpu(cpu_apbt_dev, i);
620		adev->num = i;
621		adev->cpu = i;
622		p_mtmr = sfi_get_mtmr(i);
623		if (p_mtmr) {
624			adev->tick = p_mtmr->freq_hz;
625			adev->irq = p_mtmr->irq;
626		} else
627			printk(KERN_ERR "Failed to get timer for cpu %d\n", i);
628		adev->count = 0;
629		sprintf(adev->name, "apbt%d", i);
630	}
631#endif
632
633	return;
634
635out_noapbt:
636	apbt_clear_mapping();
637	apb_timer_block_enabled = 0;
638	panic("failed to enable APB timer\n");
639}
640
641static inline void apbt_disable(int n)
642{
643	if (is_apbt_capable()) {
644		unsigned long ctrl =  apbt_readl(n, APBTMR_N_CONTROL);
645		ctrl &= ~APBTMR_CONTROL_ENABLE;
646		apbt_writel(n, ctrl, APBTMR_N_CONTROL);
647	}
648}
649
650/* called before apb_timer_enable, use early map */
651unsigned long apbt_quick_calibrate()
652{
653	int i, scale;
654	u64 old, new;
655	cycle_t t1, t2;
656	unsigned long khz = 0;
657	u32 loop, shift;
658
659	apbt_set_mapping();
660	apbt_start_counter(phy_cs_timer_id);
661
662	/* check if the timer can count down, otherwise return */
663	old = apbt_read_clocksource(&clocksource_apbt);
664	i = 10000;
665	while (--i) {
666		if (old != apbt_read_clocksource(&clocksource_apbt))
667			break;
668	}
669	if (!i)
670		goto failed;
671
672	/* count 16 ms */
673	loop = (apbt_freq * 1000) << 4;
674
675	/* restart the timer to ensure it won't get to 0 in the calibration */
676	apbt_start_counter(phy_cs_timer_id);
677
678	old = apbt_read_clocksource(&clocksource_apbt);
679	old += loop;
680
681	t1 = __native_read_tsc();
682
683	do {
684		new = apbt_read_clocksource(&clocksource_apbt);
685	} while (new < old);
686
687	t2 = __native_read_tsc();
688
689	shift = 5;
690	if (unlikely(loop >> shift == 0)) {
691		printk(KERN_INFO
692		       "APBT TSC calibration failed, not enough resolution\n");
693		return 0;
694	}
695	scale = (int)div_u64((t2 - t1), loop >> shift);
696	khz = (scale * apbt_freq * 1000) >> shift;
697	printk(KERN_INFO "TSC freq calculated by APB timer is %lu khz\n", khz);
698	return khz;
699failed:
700	return 0;
701}