PageRenderTime 27ms CodeModel.GetById 24ms app.highlight 2ms RepoModel.GetById 1ms app.codeStats 0ms

/arch/x86/include/asm/x2apic.h

https://bitbucket.org/ndreys/linux-sunxi
C++ Header | 62 lines | 41 code | 11 blank | 10 comment | 0 complexity | 8c3c85b7bd1fc9aa288d1e5c767cabb8 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
 1/*
 2 * Common bits for X2APIC cluster/physical modes.
 3 */
 4
 5#ifndef _ASM_X86_X2APIC_H
 6#define _ASM_X86_X2APIC_H
 7
 8#include <asm/apic.h>
 9#include <asm/ipi.h>
10#include <linux/cpumask.h>
11
12/*
13 * Need to use more than cpu 0, because we need more vectors
14 * when MSI-X are used.
15 */
16static const struct cpumask *x2apic_target_cpus(void)
17{
18	return cpu_online_mask;
19}
20
21static int x2apic_apic_id_registered(void)
22{
23	return 1;
24}
25
26/*
27 * For now each logical cpu is in its own vector allocation domain.
28 */
29static void x2apic_vector_allocation_domain(int cpu, struct cpumask *retmask)
30{
31	cpumask_clear(retmask);
32	cpumask_set_cpu(cpu, retmask);
33}
34
35static void
36__x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int dest)
37{
38	unsigned long cfg = __prepare_ICR(0, vector, dest);
39	native_x2apic_icr_write(cfg, apicid);
40}
41
42static unsigned int x2apic_get_apic_id(unsigned long id)
43{
44	return id;
45}
46
47static unsigned long x2apic_set_apic_id(unsigned int id)
48{
49	return id;
50}
51
52static int x2apic_phys_pkg_id(int initial_apicid, int index_msb)
53{
54	return initial_apicid >> index_msb;
55}
56
57static void x2apic_send_IPI_self(int vector)
58{
59	apic_write(APIC_SELF_IPI, vector);
60}
61
62#endif /* _ASM_X86_X2APIC_H */