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/arch/x86/include/asm/i387.h

https://bitbucket.org/ndreys/linux-sunxi
C++ Header | 627 lines | 394 code | 72 blank | 161 comment | 37 complexity | 96f776a9fa69db8fb8d4ccdfeb76f546 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1/*
  2 * Copyright (C) 1994 Linus Torvalds
  3 *
  4 * Pentium III FXSR, SSE support
  5 * General FPU state handling cleanups
  6 *	Gareth Hughes <gareth@valinux.com>, May 2000
  7 * x86-64 work by Andi Kleen 2002
  8 */
  9
 10#ifndef _ASM_X86_I387_H
 11#define _ASM_X86_I387_H
 12
 13#ifndef __ASSEMBLY__
 14
 15#include <linux/sched.h>
 16#include <linux/kernel_stat.h>
 17#include <linux/regset.h>
 18#include <linux/hardirq.h>
 19#include <linux/slab.h>
 20#include <asm/asm.h>
 21#include <asm/cpufeature.h>
 22#include <asm/processor.h>
 23#include <asm/sigcontext.h>
 24#include <asm/user.h>
 25#include <asm/uaccess.h>
 26#include <asm/xsave.h>
 27
 28extern unsigned int sig_xstate_size;
 29extern void fpu_init(void);
 30extern void mxcsr_feature_mask_init(void);
 31extern int init_fpu(struct task_struct *child);
 32extern void __math_state_restore(struct task_struct *);
 33extern void math_state_restore(void);
 34extern int dump_fpu(struct pt_regs *, struct user_i387_struct *);
 35
 36extern user_regset_active_fn fpregs_active, xfpregs_active;
 37extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get,
 38				xstateregs_get;
 39extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set,
 40				 xstateregs_set;
 41
 42/*
 43 * xstateregs_active == fpregs_active. Please refer to the comment
 44 * at the definition of fpregs_active.
 45 */
 46#define xstateregs_active	fpregs_active
 47
 48extern struct _fpx_sw_bytes fx_sw_reserved;
 49#ifdef CONFIG_IA32_EMULATION
 50extern unsigned int sig_xstate_ia32_size;
 51extern struct _fpx_sw_bytes fx_sw_reserved_ia32;
 52struct _fpstate_ia32;
 53struct _xstate_ia32;
 54extern int save_i387_xstate_ia32(void __user *buf);
 55extern int restore_i387_xstate_ia32(void __user *buf);
 56#endif
 57
 58#ifdef CONFIG_MATH_EMULATION
 59extern void finit_soft_fpu(struct i387_soft_struct *soft);
 60#else
 61static inline void finit_soft_fpu(struct i387_soft_struct *soft) {}
 62#endif
 63
 64#define X87_FSW_ES (1 << 7)	/* Exception Summary */
 65
 66static __always_inline __pure bool use_xsaveopt(void)
 67{
 68	return static_cpu_has(X86_FEATURE_XSAVEOPT);
 69}
 70
 71static __always_inline __pure bool use_xsave(void)
 72{
 73	return static_cpu_has(X86_FEATURE_XSAVE);
 74}
 75
 76static __always_inline __pure bool use_fxsr(void)
 77{
 78        return static_cpu_has(X86_FEATURE_FXSR);
 79}
 80
 81extern void __sanitize_i387_state(struct task_struct *);
 82
 83static inline void sanitize_i387_state(struct task_struct *tsk)
 84{
 85	if (!use_xsaveopt())
 86		return;
 87	__sanitize_i387_state(tsk);
 88}
 89
 90#ifdef CONFIG_X86_64
 91static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
 92{
 93	int err;
 94
 95	/* See comment in fxsave() below. */
 96#ifdef CONFIG_AS_FXSAVEQ
 97	asm volatile("1:  fxrstorq %[fx]\n\t"
 98		     "2:\n"
 99		     ".section .fixup,\"ax\"\n"
100		     "3:  movl $-1,%[err]\n"
101		     "    jmp  2b\n"
102		     ".previous\n"
103		     _ASM_EXTABLE(1b, 3b)
104		     : [err] "=r" (err)
105		     : [fx] "m" (*fx), "0" (0));
106#else
107	asm volatile("1:  rex64/fxrstor (%[fx])\n\t"
108		     "2:\n"
109		     ".section .fixup,\"ax\"\n"
110		     "3:  movl $-1,%[err]\n"
111		     "    jmp  2b\n"
112		     ".previous\n"
113		     _ASM_EXTABLE(1b, 3b)
114		     : [err] "=r" (err)
115		     : [fx] "R" (fx), "m" (*fx), "0" (0));
116#endif
117	return err;
118}
119
120static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
121{
122	int err;
123
124	/*
125	 * Clear the bytes not touched by the fxsave and reserved
126	 * for the SW usage.
127	 */
128	err = __clear_user(&fx->sw_reserved,
129			   sizeof(struct _fpx_sw_bytes));
130	if (unlikely(err))
131		return -EFAULT;
132
133	/* See comment in fxsave() below. */
134#ifdef CONFIG_AS_FXSAVEQ
135	asm volatile("1:  fxsaveq %[fx]\n\t"
136		     "2:\n"
137		     ".section .fixup,\"ax\"\n"
138		     "3:  movl $-1,%[err]\n"
139		     "    jmp  2b\n"
140		     ".previous\n"
141		     _ASM_EXTABLE(1b, 3b)
142		     : [err] "=r" (err), [fx] "=m" (*fx)
143		     : "0" (0));
144#else
145	asm volatile("1:  rex64/fxsave (%[fx])\n\t"
146		     "2:\n"
147		     ".section .fixup,\"ax\"\n"
148		     "3:  movl $-1,%[err]\n"
149		     "    jmp  2b\n"
150		     ".previous\n"
151		     _ASM_EXTABLE(1b, 3b)
152		     : [err] "=r" (err), "=m" (*fx)
153		     : [fx] "R" (fx), "0" (0));
154#endif
155	if (unlikely(err) &&
156	    __clear_user(fx, sizeof(struct i387_fxsave_struct)))
157		err = -EFAULT;
158	/* No need to clear here because the caller clears USED_MATH */
159	return err;
160}
161
162static inline void fpu_fxsave(struct fpu *fpu)
163{
164	/* Using "rex64; fxsave %0" is broken because, if the memory operand
165	   uses any extended registers for addressing, a second REX prefix
166	   will be generated (to the assembler, rex64 followed by semicolon
167	   is a separate instruction), and hence the 64-bitness is lost. */
168
169#ifdef CONFIG_AS_FXSAVEQ
170	/* Using "fxsaveq %0" would be the ideal choice, but is only supported
171	   starting with gas 2.16. */
172	__asm__ __volatile__("fxsaveq %0"
173			     : "=m" (fpu->state->fxsave));
174#else
175	/* Using, as a workaround, the properly prefixed form below isn't
176	   accepted by any binutils version so far released, complaining that
177	   the same type of prefix is used twice if an extended register is
178	   needed for addressing (fix submitted to mainline 2005-11-21).
179	asm volatile("rex64/fxsave %0"
180		     : "=m" (fpu->state->fxsave));
181	   This, however, we can work around by forcing the compiler to select
182	   an addressing mode that doesn't require extended registers. */
183	asm volatile("rex64/fxsave (%[fx])"
184		     : "=m" (fpu->state->fxsave)
185		     : [fx] "R" (&fpu->state->fxsave));
186#endif
187}
188
189#else  /* CONFIG_X86_32 */
190
191/* perform fxrstor iff the processor has extended states, otherwise frstor */
192static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
193{
194	/*
195	 * The "nop" is needed to make the instructions the same
196	 * length.
197	 */
198	alternative_input(
199		"nop ; frstor %1",
200		"fxrstor %1",
201		X86_FEATURE_FXSR,
202		"m" (*fx));
203
204	return 0;
205}
206
207static inline void fpu_fxsave(struct fpu *fpu)
208{
209	asm volatile("fxsave %[fx]"
210		     : [fx] "=m" (fpu->state->fxsave));
211}
212
213#endif	/* CONFIG_X86_64 */
214
215/*
216 * These must be called with preempt disabled. Returns
217 * 'true' if the FPU state is still intact.
218 */
219static inline int fpu_save_init(struct fpu *fpu)
220{
221	if (use_xsave()) {
222		fpu_xsave(fpu);
223
224		/*
225		 * xsave header may indicate the init state of the FP.
226		 */
227		if (!(fpu->state->xsave.xsave_hdr.xstate_bv & XSTATE_FP))
228			return 1;
229	} else if (use_fxsr()) {
230		fpu_fxsave(fpu);
231	} else {
232		asm volatile("fnsave %[fx]; fwait"
233			     : [fx] "=m" (fpu->state->fsave));
234		return 0;
235	}
236
237	/*
238	 * If exceptions are pending, we need to clear them so
239	 * that we don't randomly get exceptions later.
240	 *
241	 * FIXME! Is this perhaps only true for the old-style
242	 * irq13 case? Maybe we could leave the x87 state
243	 * intact otherwise?
244	 */
245	if (unlikely(fpu->state->fxsave.swd & X87_FSW_ES)) {
246		asm volatile("fnclex");
247		return 0;
248	}
249	return 1;
250}
251
252static inline int __save_init_fpu(struct task_struct *tsk)
253{
254	return fpu_save_init(&tsk->thread.fpu);
255}
256
257static inline int fpu_fxrstor_checking(struct fpu *fpu)
258{
259	return fxrstor_checking(&fpu->state->fxsave);
260}
261
262static inline int fpu_restore_checking(struct fpu *fpu)
263{
264	if (use_xsave())
265		return fpu_xrstor_checking(fpu);
266	else
267		return fpu_fxrstor_checking(fpu);
268}
269
270static inline int restore_fpu_checking(struct task_struct *tsk)
271{
272	return fpu_restore_checking(&tsk->thread.fpu);
273}
274
275/*
276 * Software FPU state helpers. Careful: these need to
277 * be preemption protection *and* they need to be
278 * properly paired with the CR0.TS changes!
279 */
280static inline int __thread_has_fpu(struct task_struct *tsk)
281{
282	return tsk->thread.has_fpu;
283}
284
285/* Must be paired with an 'stts' after! */
286static inline void __thread_clear_has_fpu(struct task_struct *tsk)
287{
288	tsk->thread.has_fpu = 0;
289}
290
291/* Must be paired with a 'clts' before! */
292static inline void __thread_set_has_fpu(struct task_struct *tsk)
293{
294	tsk->thread.has_fpu = 1;
295}
296
297/*
298 * Encapsulate the CR0.TS handling together with the
299 * software flag.
300 *
301 * These generally need preemption protection to work,
302 * do try to avoid using these on their own.
303 */
304static inline void __thread_fpu_end(struct task_struct *tsk)
305{
306	__thread_clear_has_fpu(tsk);
307	stts();
308}
309
310static inline void __thread_fpu_begin(struct task_struct *tsk)
311{
312	clts();
313	__thread_set_has_fpu(tsk);
314}
315
316/*
317 * FPU state switching for scheduling.
318 *
319 * This is a two-stage process:
320 *
321 *  - switch_fpu_prepare() saves the old state and
322 *    sets the new state of the CR0.TS bit. This is
323 *    done within the context of the old process.
324 *
325 *  - switch_fpu_finish() restores the new state as
326 *    necessary.
327 */
328typedef struct { int preload; } fpu_switch_t;
329
330/*
331 * FIXME! We could do a totally lazy restore, but we need to
332 * add a per-cpu "this was the task that last touched the FPU
333 * on this CPU" variable, and the task needs to have a "I last
334 * touched the FPU on this CPU" and check them.
335 *
336 * We don't do that yet, so "fpu_lazy_restore()" always returns
337 * false, but some day..
338 */
339#define fpu_lazy_restore(tsk) (0)
340#define fpu_lazy_state_intact(tsk) do { } while (0)
341
342static inline fpu_switch_t switch_fpu_prepare(struct task_struct *old, struct task_struct *new)
343{
344	fpu_switch_t fpu;
345
346	fpu.preload = tsk_used_math(new) && new->fpu_counter > 5;
347	if (__thread_has_fpu(old)) {
348		if (__save_init_fpu(old))
349			fpu_lazy_state_intact(old);
350		__thread_clear_has_fpu(old);
351		old->fpu_counter++;
352
353		/* Don't change CR0.TS if we just switch! */
354		if (fpu.preload) {
355			__thread_set_has_fpu(new);
356			prefetch(new->thread.fpu.state);
357		} else
358			stts();
359	} else {
360		old->fpu_counter = 0;
361		if (fpu.preload) {
362			if (fpu_lazy_restore(new))
363				fpu.preload = 0;
364			else
365				prefetch(new->thread.fpu.state);
366			__thread_fpu_begin(new);
367		}
368	}
369	return fpu;
370}
371
372/*
373 * By the time this gets called, we've already cleared CR0.TS and
374 * given the process the FPU if we are going to preload the FPU
375 * state - all we need to do is to conditionally restore the register
376 * state itself.
377 */
378static inline void switch_fpu_finish(struct task_struct *new, fpu_switch_t fpu)
379{
380	if (fpu.preload)
381		__math_state_restore(new);
382}
383
384/*
385 * Signal frame handlers...
386 */
387extern int save_i387_xstate(void __user *buf);
388extern int restore_i387_xstate(void __user *buf);
389
390static inline void __clear_fpu(struct task_struct *tsk)
391{
392	if (__thread_has_fpu(tsk)) {
393		/* Ignore delayed exceptions from user space */
394		asm volatile("1: fwait\n"
395			     "2:\n"
396			     _ASM_EXTABLE(1b, 2b));
397		__thread_fpu_end(tsk);
398	}
399}
400
401/*
402 * Were we in an interrupt that interrupted kernel mode?
403 *
404 * We can do a kernel_fpu_begin/end() pair *ONLY* if that
405 * pair does nothing at all: the thread must not have fpu (so
406 * that we don't try to save the FPU state), and TS must
407 * be set (so that the clts/stts pair does nothing that is
408 * visible in the interrupted kernel thread).
409 */
410static inline bool interrupted_kernel_fpu_idle(void)
411{
412	return !__thread_has_fpu(current) &&
413		(read_cr0() & X86_CR0_TS);
414}
415
416/*
417 * Were we in user mode (or vm86 mode) when we were
418 * interrupted?
419 *
420 * Doing kernel_fpu_begin/end() is ok if we are running
421 * in an interrupt context from user mode - we'll just
422 * save the FPU state as required.
423 */
424static inline bool interrupted_user_mode(void)
425{
426	struct pt_regs *regs = get_irq_regs();
427	return regs && user_mode_vm(regs);
428}
429
430/*
431 * Can we use the FPU in kernel mode with the
432 * whole "kernel_fpu_begin/end()" sequence?
433 *
434 * It's always ok in process context (ie "not interrupt")
435 * but it is sometimes ok even from an irq.
436 */
437static inline bool irq_fpu_usable(void)
438{
439	return !in_interrupt() ||
440		interrupted_user_mode() ||
441		interrupted_kernel_fpu_idle();
442}
443
444static inline void kernel_fpu_begin(void)
445{
446	struct task_struct *me = current;
447
448	WARN_ON_ONCE(!irq_fpu_usable());
449	preempt_disable();
450	if (__thread_has_fpu(me)) {
451		__save_init_fpu(me);
452		__thread_clear_has_fpu(me);
453		/* We do 'stts()' in kernel_fpu_end() */
454	} else
455		clts();
456}
457
458static inline void kernel_fpu_end(void)
459{
460	stts();
461	preempt_enable();
462}
463
464/*
465 * Some instructions like VIA's padlock instructions generate a spurious
466 * DNA fault but don't modify SSE registers. And these instructions
467 * get used from interrupt context as well. To prevent these kernel instructions
468 * in interrupt context interacting wrongly with other user/kernel fpu usage, we
469 * should use them only in the context of irq_ts_save/restore()
470 */
471static inline int irq_ts_save(void)
472{
473	/*
474	 * If in process context and not atomic, we can take a spurious DNA fault.
475	 * Otherwise, doing clts() in process context requires disabling preemption
476	 * or some heavy lifting like kernel_fpu_begin()
477	 */
478	if (!in_atomic())
479		return 0;
480
481	if (read_cr0() & X86_CR0_TS) {
482		clts();
483		return 1;
484	}
485
486	return 0;
487}
488
489static inline void irq_ts_restore(int TS_state)
490{
491	if (TS_state)
492		stts();
493}
494
495/*
496 * The question "does this thread have fpu access?"
497 * is slightly racy, since preemption could come in
498 * and revoke it immediately after the test.
499 *
500 * However, even in that very unlikely scenario,
501 * we can just assume we have FPU access - typically
502 * to save the FP state - we'll just take a #NM
503 * fault and get the FPU access back.
504 *
505 * The actual user_fpu_begin/end() functions
506 * need to be preemption-safe, though.
507 *
508 * NOTE! user_fpu_end() must be used only after you
509 * have saved the FP state, and user_fpu_begin() must
510 * be used only immediately before restoring it.
511 * These functions do not do any save/restore on
512 * their own.
513 */
514static inline int user_has_fpu(void)
515{
516	return __thread_has_fpu(current);
517}
518
519static inline void user_fpu_end(void)
520{
521	preempt_disable();
522	__thread_fpu_end(current);
523	preempt_enable();
524}
525
526static inline void user_fpu_begin(void)
527{
528	preempt_disable();
529	if (!user_has_fpu())
530		__thread_fpu_begin(current);
531	preempt_enable();
532}
533
534/*
535 * These disable preemption on their own and are safe
536 */
537static inline void save_init_fpu(struct task_struct *tsk)
538{
539	WARN_ON_ONCE(!__thread_has_fpu(tsk));
540	preempt_disable();
541	__save_init_fpu(tsk);
542	__thread_fpu_end(tsk);
543	preempt_enable();
544}
545
546static inline void unlazy_fpu(struct task_struct *tsk)
547{
548	preempt_disable();
549	if (__thread_has_fpu(tsk)) {
550		__save_init_fpu(tsk);
551		__thread_fpu_end(tsk);
552	} else
553		tsk->fpu_counter = 0;
554	preempt_enable();
555}
556
557static inline void clear_fpu(struct task_struct *tsk)
558{
559	preempt_disable();
560	__clear_fpu(tsk);
561	preempt_enable();
562}
563
564/*
565 * i387 state interaction
566 */
567static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
568{
569	if (cpu_has_fxsr) {
570		return tsk->thread.fpu.state->fxsave.cwd;
571	} else {
572		return (unsigned short)tsk->thread.fpu.state->fsave.cwd;
573	}
574}
575
576static inline unsigned short get_fpu_swd(struct task_struct *tsk)
577{
578	if (cpu_has_fxsr) {
579		return tsk->thread.fpu.state->fxsave.swd;
580	} else {
581		return (unsigned short)tsk->thread.fpu.state->fsave.swd;
582	}
583}
584
585static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
586{
587	if (cpu_has_xmm) {
588		return tsk->thread.fpu.state->fxsave.mxcsr;
589	} else {
590		return MXCSR_DEFAULT;
591	}
592}
593
594static bool fpu_allocated(struct fpu *fpu)
595{
596	return fpu->state != NULL;
597}
598
599static inline int fpu_alloc(struct fpu *fpu)
600{
601	if (fpu_allocated(fpu))
602		return 0;
603	fpu->state = kmem_cache_alloc(task_xstate_cachep, GFP_KERNEL);
604	if (!fpu->state)
605		return -ENOMEM;
606	WARN_ON((unsigned long)fpu->state & 15);
607	return 0;
608}
609
610static inline void fpu_free(struct fpu *fpu)
611{
612	if (fpu->state) {
613		kmem_cache_free(task_xstate_cachep, fpu->state);
614		fpu->state = NULL;
615	}
616}
617
618static inline void fpu_copy(struct fpu *dst, struct fpu *src)
619{
620	memcpy(dst->state, src->state, xstate_size);
621}
622
623extern void fpu_finit(struct fpu *fpu);
624
625#endif /* __ASSEMBLY__ */
626
627#endif /* _ASM_X86_I387_H */