/arch/x86/include/asm/desc.h
C++ Header | 395 lines | 296 code | 71 blank | 28 comment | 18 complexity | 844154e21a871f42a2f1d52401fd58ec MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
1#ifndef _ASM_X86_DESC_H 2#define _ASM_X86_DESC_H 3 4#include <asm/desc_defs.h> 5#include <asm/ldt.h> 6#include <asm/mmu.h> 7 8#include <linux/smp.h> 9 10static inline void fill_ldt(struct desc_struct *desc, const struct user_desc *info) 11{ 12 desc->limit0 = info->limit & 0x0ffff; 13 14 desc->base0 = (info->base_addr & 0x0000ffff); 15 desc->base1 = (info->base_addr & 0x00ff0000) >> 16; 16 17 desc->type = (info->read_exec_only ^ 1) << 1; 18 desc->type |= info->contents << 2; 19 20 desc->s = 1; 21 desc->dpl = 0x3; 22 desc->p = info->seg_not_present ^ 1; 23 desc->limit = (info->limit & 0xf0000) >> 16; 24 desc->avl = info->useable; 25 desc->d = info->seg_32bit; 26 desc->g = info->limit_in_pages; 27 28 desc->base2 = (info->base_addr & 0xff000000) >> 24; 29 /* 30 * Don't allow setting of the lm bit. It is useless anyway 31 * because 64bit system calls require __USER_CS: 32 */ 33 desc->l = 0; 34} 35 36extern struct desc_ptr idt_descr; 37extern gate_desc idt_table[]; 38 39struct gdt_page { 40 struct desc_struct gdt[GDT_ENTRIES]; 41} __attribute__((aligned(PAGE_SIZE))); 42 43DECLARE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page); 44 45static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu) 46{ 47 return per_cpu(gdt_page, cpu).gdt; 48} 49 50#ifdef CONFIG_X86_64 51 52static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func, 53 unsigned dpl, unsigned ist, unsigned seg) 54{ 55 gate->offset_low = PTR_LOW(func); 56 gate->segment = __KERNEL_CS; 57 gate->ist = ist; 58 gate->p = 1; 59 gate->dpl = dpl; 60 gate->zero0 = 0; 61 gate->zero1 = 0; 62 gate->type = type; 63 gate->offset_middle = PTR_MIDDLE(func); 64 gate->offset_high = PTR_HIGH(func); 65} 66 67#else 68static inline void pack_gate(gate_desc *gate, unsigned char type, 69 unsigned long base, unsigned dpl, unsigned flags, 70 unsigned short seg) 71{ 72 gate->a = (seg << 16) | (base & 0xffff); 73 gate->b = (base & 0xffff0000) | (((0x80 | type | (dpl << 5)) & 0xff) << 8); 74} 75 76#endif 77 78static inline int desc_empty(const void *ptr) 79{ 80 const u32 *desc = ptr; 81 82 return !(desc[0] | desc[1]); 83} 84 85#ifdef CONFIG_PARAVIRT 86#include <asm/paravirt.h> 87#else 88#define load_TR_desc() native_load_tr_desc() 89#define load_gdt(dtr) native_load_gdt(dtr) 90#define load_idt(dtr) native_load_idt(dtr) 91#define load_tr(tr) asm volatile("ltr %0"::"m" (tr)) 92#define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt)) 93 94#define store_gdt(dtr) native_store_gdt(dtr) 95#define store_idt(dtr) native_store_idt(dtr) 96#define store_tr(tr) (tr = native_store_tr()) 97 98#define load_TLS(t, cpu) native_load_tls(t, cpu) 99#define set_ldt native_set_ldt 100 101#define write_ldt_entry(dt, entry, desc) native_write_ldt_entry(dt, entry, desc) 102#define write_gdt_entry(dt, entry, desc, type) native_write_gdt_entry(dt, entry, desc, type) 103#define write_idt_entry(dt, entry, g) native_write_idt_entry(dt, entry, g) 104 105static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries) 106{ 107} 108 109static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries) 110{ 111} 112#endif /* CONFIG_PARAVIRT */ 113 114#define store_ldt(ldt) asm("sldt %0" : "=m"(ldt)) 115 116static inline void native_write_idt_entry(gate_desc *idt, int entry, const gate_desc *gate) 117{ 118 memcpy(&idt[entry], gate, sizeof(*gate)); 119} 120 121static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry, const void *desc) 122{ 123 memcpy(&ldt[entry], desc, 8); 124} 125 126static inline void 127native_write_gdt_entry(struct desc_struct *gdt, int entry, const void *desc, int type) 128{ 129 unsigned int size; 130 131 switch (type) { 132 case DESC_TSS: size = sizeof(tss_desc); break; 133 case DESC_LDT: size = sizeof(ldt_desc); break; 134 default: size = sizeof(*gdt); break; 135 } 136 137 memcpy(&gdt[entry], desc, size); 138} 139 140static inline void pack_descriptor(struct desc_struct *desc, unsigned long base, 141 unsigned long limit, unsigned char type, 142 unsigned char flags) 143{ 144 desc->a = ((base & 0xffff) << 16) | (limit & 0xffff); 145 desc->b = (base & 0xff000000) | ((base & 0xff0000) >> 16) | 146 (limit & 0x000f0000) | ((type & 0xff) << 8) | 147 ((flags & 0xf) << 20); 148 desc->p = 1; 149} 150 151 152static inline void set_tssldt_descriptor(void *d, unsigned long addr, unsigned type, unsigned size) 153{ 154#ifdef CONFIG_X86_64 155 struct ldttss_desc64 *desc = d; 156 157 memset(desc, 0, sizeof(*desc)); 158 159 desc->limit0 = size & 0xFFFF; 160 desc->base0 = PTR_LOW(addr); 161 desc->base1 = PTR_MIDDLE(addr) & 0xFF; 162 desc->type = type; 163 desc->p = 1; 164 desc->limit1 = (size >> 16) & 0xF; 165 desc->base2 = (PTR_MIDDLE(addr) >> 8) & 0xFF; 166 desc->base3 = PTR_HIGH(addr); 167#else 168 pack_descriptor((struct desc_struct *)d, addr, size, 0x80 | type, 0); 169#endif 170} 171 172static inline void __set_tss_desc(unsigned cpu, unsigned int entry, void *addr) 173{ 174 struct desc_struct *d = get_cpu_gdt_table(cpu); 175 tss_desc tss; 176 177 /* 178 * sizeof(unsigned long) coming from an extra "long" at the end 179 * of the iobitmap. See tss_struct definition in processor.h 180 * 181 * -1? seg base+limit should be pointing to the address of the 182 * last valid byte 183 */ 184 set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS, 185 IO_BITMAP_OFFSET + IO_BITMAP_BYTES + 186 sizeof(unsigned long) - 1); 187 write_gdt_entry(d, entry, &tss, DESC_TSS); 188} 189 190#define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr) 191 192static inline void native_set_ldt(const void *addr, unsigned int entries) 193{ 194 if (likely(entries == 0)) 195 asm volatile("lldt %w0"::"q" (0)); 196 else { 197 unsigned cpu = smp_processor_id(); 198 ldt_desc ldt; 199 200 set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT, 201 entries * LDT_ENTRY_SIZE - 1); 202 write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_LDT, 203 &ldt, DESC_LDT); 204 asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8)); 205 } 206} 207 208static inline void native_load_tr_desc(void) 209{ 210 asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8)); 211} 212 213static inline void native_load_gdt(const struct desc_ptr *dtr) 214{ 215 asm volatile("lgdt %0"::"m" (*dtr)); 216} 217 218static inline void native_load_idt(const struct desc_ptr *dtr) 219{ 220 asm volatile("lidt %0"::"m" (*dtr)); 221} 222 223static inline void native_store_gdt(struct desc_ptr *dtr) 224{ 225 asm volatile("sgdt %0":"=m" (*dtr)); 226} 227 228static inline void native_store_idt(struct desc_ptr *dtr) 229{ 230 asm volatile("sidt %0":"=m" (*dtr)); 231} 232 233static inline unsigned long native_store_tr(void) 234{ 235 unsigned long tr; 236 237 asm volatile("str %0":"=r" (tr)); 238 239 return tr; 240} 241 242static inline void native_load_tls(struct thread_struct *t, unsigned int cpu) 243{ 244 struct desc_struct *gdt = get_cpu_gdt_table(cpu); 245 unsigned int i; 246 247 for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++) 248 gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i]; 249} 250 251#define _LDT_empty(info) \ 252 ((info)->base_addr == 0 && \ 253 (info)->limit == 0 && \ 254 (info)->contents == 0 && \ 255 (info)->read_exec_only == 1 && \ 256 (info)->seg_32bit == 0 && \ 257 (info)->limit_in_pages == 0 && \ 258 (info)->seg_not_present == 1 && \ 259 (info)->useable == 0) 260 261#ifdef CONFIG_X86_64 262#define LDT_empty(info) (_LDT_empty(info) && ((info)->lm == 0)) 263#else 264#define LDT_empty(info) (_LDT_empty(info)) 265#endif 266 267static inline void clear_LDT(void) 268{ 269 set_ldt(NULL, 0); 270} 271 272/* 273 * load one particular LDT into the current CPU 274 */ 275static inline void load_LDT_nolock(mm_context_t *pc) 276{ 277 set_ldt(pc->ldt, pc->size); 278} 279 280static inline void load_LDT(mm_context_t *pc) 281{ 282 preempt_disable(); 283 load_LDT_nolock(pc); 284 preempt_enable(); 285} 286 287static inline unsigned long get_desc_base(const struct desc_struct *desc) 288{ 289 return (unsigned)(desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24)); 290} 291 292static inline void set_desc_base(struct desc_struct *desc, unsigned long base) 293{ 294 desc->base0 = base & 0xffff; 295 desc->base1 = (base >> 16) & 0xff; 296 desc->base2 = (base >> 24) & 0xff; 297} 298 299static inline unsigned long get_desc_limit(const struct desc_struct *desc) 300{ 301 return desc->limit0 | (desc->limit << 16); 302} 303 304static inline void set_desc_limit(struct desc_struct *desc, unsigned long limit) 305{ 306 desc->limit0 = limit & 0xffff; 307 desc->limit = (limit >> 16) & 0xf; 308} 309 310static inline void _set_gate(int gate, unsigned type, void *addr, 311 unsigned dpl, unsigned ist, unsigned seg) 312{ 313 gate_desc s; 314 315 pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg); 316 /* 317 * does not need to be atomic because it is only done once at 318 * setup time 319 */ 320 write_idt_entry(idt_table, gate, &s); 321} 322 323/* 324 * This needs to use 'idt_table' rather than 'idt', and 325 * thus use the _nonmapped_ version of the IDT, as the 326 * Pentium F0 0F bugfix can have resulted in the mapped 327 * IDT being write-protected. 328 */ 329static inline void set_intr_gate(unsigned int n, void *addr) 330{ 331 BUG_ON((unsigned)n > 0xFF); 332 _set_gate(n, GATE_INTERRUPT, addr, 0, 0, __KERNEL_CS); 333} 334 335extern int first_system_vector; 336/* used_vectors is BITMAP for irq is not managed by percpu vector_irq */ 337extern unsigned long used_vectors[]; 338 339static inline void alloc_system_vector(int vector) 340{ 341 if (!test_bit(vector, used_vectors)) { 342 set_bit(vector, used_vectors); 343 if (first_system_vector > vector) 344 first_system_vector = vector; 345 } else { 346 BUG(); 347 } 348} 349 350static inline void alloc_intr_gate(unsigned int n, void *addr) 351{ 352 alloc_system_vector(n); 353 set_intr_gate(n, addr); 354} 355 356/* 357 * This routine sets up an interrupt gate at directory privilege level 3. 358 */ 359static inline void set_system_intr_gate(unsigned int n, void *addr) 360{ 361 BUG_ON((unsigned)n > 0xFF); 362 _set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS); 363} 364 365static inline void set_system_trap_gate(unsigned int n, void *addr) 366{ 367 BUG_ON((unsigned)n > 0xFF); 368 _set_gate(n, GATE_TRAP, addr, 0x3, 0, __KERNEL_CS); 369} 370 371static inline void set_trap_gate(unsigned int n, void *addr) 372{ 373 BUG_ON((unsigned)n > 0xFF); 374 _set_gate(n, GATE_TRAP, addr, 0, 0, __KERNEL_CS); 375} 376 377static inline void set_task_gate(unsigned int n, unsigned int gdt_entry) 378{ 379 BUG_ON((unsigned)n > 0xFF); 380 _set_gate(n, GATE_TASK, (void *)0, 0, 0, (gdt_entry<<3)); 381} 382 383static inline void set_intr_gate_ist(int n, void *addr, unsigned ist) 384{ 385 BUG_ON((unsigned)n > 0xFF); 386 _set_gate(n, GATE_INTERRUPT, addr, 0, ist, __KERNEL_CS); 387} 388 389static inline void set_system_intr_gate_ist(int n, void *addr, unsigned ist) 390{ 391 BUG_ON((unsigned)n > 0xFF); 392 _set_gate(n, GATE_INTERRUPT, addr, 0x3, ist, __KERNEL_CS); 393} 394 395#endif /* _ASM_X86_DESC_H */