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/arch/x86/include/asm/uv/uv_bau.h

https://bitbucket.org/ndreys/linux-sunxi
C++ Header | 680 lines | 361 code | 59 blank | 260 comment | 1 complexity | 02de7e7b7a4057b77ecad355069c06a2 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1/*
  2 * This file is subject to the terms and conditions of the GNU General Public
  3 * License.  See the file "COPYING" in the main directory of this archive
  4 * for more details.
  5 *
  6 * SGI UV Broadcast Assist Unit definitions
  7 *
  8 * Copyright (C) 2008-2011 Silicon Graphics, Inc. All rights reserved.
  9 */
 10
 11#ifndef _ASM_X86_UV_UV_BAU_H
 12#define _ASM_X86_UV_UV_BAU_H
 13
 14#include <linux/bitmap.h>
 15#define BITSPERBYTE 8
 16
 17/*
 18 * Broadcast Assist Unit messaging structures
 19 *
 20 * Selective Broadcast activations are induced by software action
 21 * specifying a particular 8-descriptor "set" via a 6-bit index written
 22 * to an MMR.
 23 * Thus there are 64 unique 512-byte sets of SB descriptors - one set for
 24 * each 6-bit index value. These descriptor sets are mapped in sequence
 25 * starting with set 0 located at the address specified in the
 26 * BAU_SB_DESCRIPTOR_BASE register, set 1 is located at BASE + 512,
 27 * set 2 is at BASE + 2*512, set 3 at BASE + 3*512, and so on.
 28 *
 29 * We will use one set for sending BAU messages from each of the
 30 * cpu's on the uvhub.
 31 *
 32 * TLB shootdown will use the first of the 8 descriptors of each set.
 33 * Each of the descriptors is 64 bytes in size (8*64 = 512 bytes in a set).
 34 */
 35
 36#define MAX_CPUS_PER_UVHUB		64
 37#define MAX_CPUS_PER_SOCKET		32
 38#define ADP_SZ				64 /* hardware-provided max. */
 39#define UV_CPUS_PER_AS			32 /* hardware-provided max. */
 40#define ITEMS_PER_DESC			8
 41/* the 'throttle' to prevent the hardware stay-busy bug */
 42#define MAX_BAU_CONCURRENT		3
 43#define UV_ACT_STATUS_MASK		0x3
 44#define UV_ACT_STATUS_SIZE		2
 45#define UV_DISTRIBUTION_SIZE		256
 46#define UV_SW_ACK_NPENDING		8
 47#define UV1_NET_ENDPOINT_INTD		0x38
 48#define UV2_NET_ENDPOINT_INTD		0x28
 49#define UV_NET_ENDPOINT_INTD		(is_uv1_hub() ?			\
 50			UV1_NET_ENDPOINT_INTD : UV2_NET_ENDPOINT_INTD)
 51#define UV_DESC_PSHIFT			49
 52#define UV_PAYLOADQ_PNODE_SHIFT		49
 53#define UV_PTC_BASENAME			"sgi_uv/ptc_statistics"
 54#define UV_BAU_BASENAME			"sgi_uv/bau_tunables"
 55#define UV_BAU_TUNABLES_DIR		"sgi_uv"
 56#define UV_BAU_TUNABLES_FILE		"bau_tunables"
 57#define WHITESPACE			" \t\n"
 58#define uv_mmask			((1UL << uv_hub_info->m_val) - 1)
 59#define uv_physnodeaddr(x)		((__pa((unsigned long)(x)) & uv_mmask))
 60#define cpubit_isset(cpu, bau_local_cpumask) \
 61	test_bit((cpu), (bau_local_cpumask).bits)
 62
 63/* [19:16] SOFT_ACK timeout period  19: 1 is urgency 7  17:16 1 is multiplier */
 64/*
 65 * UV2: Bit 19 selects between
 66 *  (0): 10 microsecond timebase and
 67 *  (1): 80 microseconds
 68 *  we're using 655us, similar to UV1: 65 units of 10us
 69 */
 70#define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL)
 71#define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (65*10UL)
 72
 73#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD	(is_uv1_hub() ?			\
 74		UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD :			\
 75		UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD)
 76
 77#define BAU_MISC_CONTROL_MULT_MASK	3
 78
 79#define UVH_AGING_PRESCALE_SEL		0x000000b000UL
 80/* [30:28] URGENCY_7  an index into a table of times */
 81#define BAU_URGENCY_7_SHIFT		28
 82#define BAU_URGENCY_7_MASK		7
 83
 84#define UVH_TRANSACTION_TIMEOUT		0x000000b200UL
 85/* [45:40] BAU - BAU transaction timeout select - a multiplier */
 86#define BAU_TRANS_SHIFT			40
 87#define BAU_TRANS_MASK			0x3f
 88
 89/*
 90 * shorten some awkward names
 91 */
 92#define AS_PUSH_SHIFT UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT
 93#define SOFTACK_MSHIFT UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT
 94#define SOFTACK_PSHIFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
 95#define SOFTACK_TIMEOUT_PERIOD UV_INTD_SOFT_ACK_TIMEOUT_PERIOD
 96#define write_gmmr	uv_write_global_mmr64
 97#define write_lmmr	uv_write_local_mmr
 98#define read_lmmr	uv_read_local_mmr
 99#define read_gmmr	uv_read_global_mmr64
100
101/*
102 * bits in UVH_LB_BAU_SB_ACTIVATION_STATUS_0/1
103 */
104#define DS_IDLE				0
105#define DS_ACTIVE			1
106#define DS_DESTINATION_TIMEOUT		2
107#define DS_SOURCE_TIMEOUT		3
108/*
109 * bits put together from HRP_LB_BAU_SB_ACTIVATION_STATUS_0/1/2
110 * values 1 and 5 will not occur
111 */
112#define UV2H_DESC_IDLE			0
113#define UV2H_DESC_DEST_TIMEOUT		2
114#define UV2H_DESC_DEST_STRONG_NACK	3
115#define UV2H_DESC_BUSY			4
116#define UV2H_DESC_SOURCE_TIMEOUT	6
117#define UV2H_DESC_DEST_PUT_ERR		7
118
119/*
120 * delay for 'plugged' timeout retries, in microseconds
121 */
122#define PLUGGED_DELAY			10
123
124/*
125 * threshholds at which to use IPI to free resources
126 */
127/* after this # consecutive 'plugged' timeouts, use IPI to release resources */
128#define PLUGSB4RESET			100
129/* after this many consecutive timeouts, use IPI to release resources */
130#define TIMEOUTSB4RESET			1
131/* at this number uses of IPI to release resources, giveup the request */
132#define IPI_RESET_LIMIT			1
133/* after this # consecutive successes, bump up the throttle if it was lowered */
134#define COMPLETE_THRESHOLD		5
135
136#define UV_LB_SUBNODEID			0x10
137
138/* these two are the same for UV1 and UV2: */
139#define UV_SA_SHFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
140#define UV_SA_MASK UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK
141/* 4 bits of software ack period */
142#define UV2_ACK_MASK			0x7UL
143#define UV2_ACK_UNITS_SHFT		3
144#define UV2_LEG_SHFT UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT
145#define UV2_EXT_SHFT UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
146
147/*
148 * number of entries in the destination side payload queue
149 */
150#define DEST_Q_SIZE			20
151/*
152 * number of destination side software ack resources
153 */
154#define DEST_NUM_RESOURCES		8
155/*
156 * completion statuses for sending a TLB flush message
157 */
158#define FLUSH_RETRY_PLUGGED		1
159#define FLUSH_RETRY_TIMEOUT		2
160#define FLUSH_GIVEUP			3
161#define FLUSH_COMPLETE			4
162
163/*
164 * tuning the action when the numalink network is extremely delayed
165 */
166#define CONGESTED_RESPONSE_US		1000	/* 'long' response time, in
167						   microseconds */
168#define CONGESTED_REPS			10	/* long delays averaged over
169						   this many broadcasts */
170#define CONGESTED_PERIOD		30	/* time for the bau to be
171						   disabled, in seconds */
172/* see msg_type: */
173#define MSG_NOOP			0
174#define MSG_REGULAR			1
175#define MSG_RETRY			2
176
177/*
178 * Distribution: 32 bytes (256 bits) (bytes 0-0x1f of descriptor)
179 * If the 'multilevel' flag in the header portion of the descriptor
180 * has been set to 0, then endpoint multi-unicast mode is selected.
181 * The distribution specification (32 bytes) is interpreted as a 256-bit
182 * distribution vector. Adjacent bits correspond to consecutive even numbered
183 * nodeIDs. The result of adding the index of a given bit to the 15-bit
184 * 'base_dest_nasid' field of the header corresponds to the
185 * destination nodeID associated with that specified bit.
186 */
187struct bau_targ_hubmask {
188	unsigned long		bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)];
189};
190
191/*
192 * mask of cpu's on a uvhub
193 * (during initialization we need to check that unsigned long has
194 *  enough bits for max. cpu's per uvhub)
195 */
196struct bau_local_cpumask {
197	unsigned long		bits;
198};
199
200/*
201 * Payload: 16 bytes (128 bits) (bytes 0x20-0x2f of descriptor)
202 * only 12 bytes (96 bits) of the payload area are usable.
203 * An additional 3 bytes (bits 27:4) of the header address are carried
204 * to the next bytes of the destination payload queue.
205 * And an additional 2 bytes of the header Suppl_A field are also
206 * carried to the destination payload queue.
207 * But the first byte of the Suppl_A becomes bits 127:120 (the 16th byte)
208 * of the destination payload queue, which is written by the hardware
209 * with the s/w ack resource bit vector.
210 * [ effective message contents (16 bytes (128 bits) maximum), not counting
211 *   the s/w ack bit vector  ]
212 */
213
214/*
215 * The payload is software-defined for INTD transactions
216 */
217struct bau_msg_payload {
218	unsigned long	address;		/* signifies a page or all
219						   TLB's of the cpu */
220	/* 64 bits */
221	unsigned short	sending_cpu;		/* filled in by sender */
222	/* 16 bits */
223	unsigned short	acknowledge_count;	/* filled in by destination */
224	/* 16 bits */
225	unsigned int	reserved1:32;		/* not usable */
226};
227
228
229/*
230 * Message header:  16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)
231 * see table 4.2.3.0.1 in broacast_assist spec.
232 */
233struct bau_msg_header {
234	unsigned int	dest_subnodeid:6;	/* must be 0x10, for the LB */
235	/* bits 5:0 */
236	unsigned int	base_dest_nasid:15;	/* nasid of the first bit */
237	/* bits 20:6 */				/* in uvhub map */
238	unsigned int	command:8;		/* message type */
239	/* bits 28:21 */
240	/* 0x38: SN3net EndPoint Message */
241	unsigned int	rsvd_1:3;		/* must be zero */
242	/* bits 31:29 */
243	/* int will align on 32 bits */
244	unsigned int	rsvd_2:9;		/* must be zero */
245	/* bits 40:32 */
246	/* Suppl_A is 56-41 */
247	unsigned int	sequence:16;		/* message sequence number */
248	/* bits 56:41 */			/* becomes bytes 16-17 of msg */
249						/* Address field (96:57) is
250						   never used as an address
251						   (these are address bits
252						   42:3) */
253
254	unsigned int	rsvd_3:1;		/* must be zero */
255	/* bit 57 */
256	/* address bits 27:4 are payload */
257	/* these next 24  (58-81) bits become bytes 12-14 of msg */
258	/* bits 65:58 land in byte 12 */
259	unsigned int	replied_to:1;		/* sent as 0 by the source to
260						   byte 12 */
261	/* bit 58 */
262	unsigned int	msg_type:3;		/* software type of the
263						   message */
264	/* bits 61:59 */
265	unsigned int	canceled:1;		/* message canceled, resource
266						   is to be freed*/
267	/* bit 62 */
268	unsigned int	payload_1a:1;		/* not currently used */
269	/* bit 63 */
270	unsigned int	payload_1b:2;		/* not currently used */
271	/* bits 65:64 */
272
273	/* bits 73:66 land in byte 13 */
274	unsigned int	payload_1ca:6;		/* not currently used */
275	/* bits 71:66 */
276	unsigned int	payload_1c:2;		/* not currently used */
277	/* bits 73:72 */
278
279	/* bits 81:74 land in byte 14 */
280	unsigned int	payload_1d:6;		/* not currently used */
281	/* bits 79:74 */
282	unsigned int	payload_1e:2;		/* not currently used */
283	/* bits 81:80 */
284
285	unsigned int	rsvd_4:7;		/* must be zero */
286	/* bits 88:82 */
287	unsigned int	swack_flag:1;		/* software acknowledge flag */
288	/* bit 89 */
289						/* INTD trasactions at
290						   destination are to wait for
291						   software acknowledge */
292	unsigned int	rsvd_5:6;		/* must be zero */
293	/* bits 95:90 */
294	unsigned int	rsvd_6:5;		/* must be zero */
295	/* bits 100:96 */
296	unsigned int	int_both:1;		/* if 1, interrupt both sockets
297						   on the uvhub */
298	/* bit 101*/
299	unsigned int	fairness:3;		/* usually zero */
300	/* bits 104:102 */
301	unsigned int	multilevel:1;		/* multi-level multicast
302						   format */
303	/* bit 105 */
304	/* 0 for TLB: endpoint multi-unicast messages */
305	unsigned int	chaining:1;		/* next descriptor is part of
306						   this activation*/
307	/* bit 106 */
308	unsigned int	rsvd_7:21;		/* must be zero */
309	/* bits 127:107 */
310};
311
312/*
313 * The activation descriptor:
314 * The format of the message to send, plus all accompanying control
315 * Should be 64 bytes
316 */
317struct bau_desc {
318	struct bau_targ_hubmask	distribution;
319	/*
320	 * message template, consisting of header and payload:
321	 */
322	struct bau_msg_header		header;
323	struct bau_msg_payload		payload;
324};
325/*
326 *   -payload--    ---------header------
327 *   bytes 0-11    bits 41-56  bits 58-81
328 *       A           B  (2)      C (3)
329 *
330 *            A/B/C are moved to:
331 *       A            C          B
332 *   bytes 0-11  bytes 12-14  bytes 16-17  (byte 15 filled in by hw as vector)
333 *   ------------payload queue-----------
334 */
335
336/*
337 * The payload queue on the destination side is an array of these.
338 * With BAU_MISC_CONTROL set for software acknowledge mode, the messages
339 * are 32 bytes (2 micropackets) (256 bits) in length, but contain only 17
340 * bytes of usable data, including the sw ack vector in byte 15 (bits 127:120)
341 * (12 bytes come from bau_msg_payload, 3 from payload_1, 2 from
342 *  swack_vec and payload_2)
343 * "Enabling Software Acknowledgment mode (see Section 4.3.3 Software
344 *  Acknowledge Processing) also selects 32 byte (17 bytes usable) payload
345 *  operation."
346 */
347struct bau_pq_entry {
348	unsigned long	address;	/* signifies a page or all TLB's
349					   of the cpu */
350	/* 64 bits, bytes 0-7 */
351	unsigned short	sending_cpu;	/* cpu that sent the message */
352	/* 16 bits, bytes 8-9 */
353	unsigned short	acknowledge_count; /* filled in by destination */
354	/* 16 bits, bytes 10-11 */
355	/* these next 3 bytes come from bits 58-81 of the message header */
356	unsigned short	replied_to:1;	/* sent as 0 by the source */
357	unsigned short	msg_type:3;	/* software message type */
358	unsigned short	canceled:1;	/* sent as 0 by the source */
359	unsigned short	unused1:3;	/* not currently using */
360	/* byte 12 */
361	unsigned char	unused2a;	/* not currently using */
362	/* byte 13 */
363	unsigned char	unused2;	/* not currently using */
364	/* byte 14 */
365	unsigned char	swack_vec;	/* filled in by the hardware */
366	/* byte 15 (bits 127:120) */
367	unsigned short	sequence;	/* message sequence number */
368	/* bytes 16-17 */
369	unsigned char	unused4[2];	/* not currently using bytes 18-19 */
370	/* bytes 18-19 */
371	int		number_of_cpus;	/* filled in at destination */
372	/* 32 bits, bytes 20-23 (aligned) */
373	unsigned char	unused5[8];	/* not using */
374	/* bytes 24-31 */
375};
376
377struct msg_desc {
378	struct bau_pq_entry	*msg;
379	int			msg_slot;
380	int			swack_slot;
381	struct bau_pq_entry	*queue_first;
382	struct bau_pq_entry	*queue_last;
383};
384
385struct reset_args {
386	int			sender;
387};
388
389/*
390 * This structure is allocated per_cpu for UV TLB shootdown statistics.
391 */
392struct ptc_stats {
393	/* sender statistics */
394	unsigned long	s_giveup;		/* number of fall backs to
395						   IPI-style flushes */
396	unsigned long	s_requestor;		/* number of shootdown
397						   requests */
398	unsigned long	s_stimeout;		/* source side timeouts */
399	unsigned long	s_dtimeout;		/* destination side timeouts */
400	unsigned long	s_time;			/* time spent in sending side */
401	unsigned long	s_retriesok;		/* successful retries */
402	unsigned long	s_ntargcpu;		/* total number of cpu's
403						   targeted */
404	unsigned long	s_ntargself;		/* times the sending cpu was
405						   targeted */
406	unsigned long	s_ntarglocals;		/* targets of cpus on the local
407						   blade */
408	unsigned long	s_ntargremotes;		/* targets of cpus on remote
409						   blades */
410	unsigned long	s_ntarglocaluvhub;	/* targets of the local hub */
411	unsigned long	s_ntargremoteuvhub;	/* remotes hubs targeted */
412	unsigned long	s_ntarguvhub;		/* total number of uvhubs
413						   targeted */
414	unsigned long	s_ntarguvhub16;		/* number of times target
415						   hubs >= 16*/
416	unsigned long	s_ntarguvhub8;		/* number of times target
417						   hubs >= 8 */
418	unsigned long	s_ntarguvhub4;		/* number of times target
419						   hubs >= 4 */
420	unsigned long	s_ntarguvhub2;		/* number of times target
421						   hubs >= 2 */
422	unsigned long	s_ntarguvhub1;		/* number of times target
423						   hubs == 1 */
424	unsigned long	s_resets_plug;		/* ipi-style resets from plug
425						   state */
426	unsigned long	s_resets_timeout;	/* ipi-style resets from
427						   timeouts */
428	unsigned long	s_busy;			/* status stayed busy past
429						   s/w timer */
430	unsigned long	s_throttles;		/* waits in throttle */
431	unsigned long	s_retry_messages;	/* retry broadcasts */
432	unsigned long	s_bau_reenabled;	/* for bau enable/disable */
433	unsigned long	s_bau_disabled;		/* for bau enable/disable */
434	/* destination statistics */
435	unsigned long	d_alltlb;		/* times all tlb's on this
436						   cpu were flushed */
437	unsigned long	d_onetlb;		/* times just one tlb on this
438						   cpu was flushed */
439	unsigned long	d_multmsg;		/* interrupts with multiple
440						   messages */
441	unsigned long	d_nomsg;		/* interrupts with no message */
442	unsigned long	d_time;			/* time spent on destination
443						   side */
444	unsigned long	d_requestee;		/* number of messages
445						   processed */
446	unsigned long	d_retries;		/* number of retry messages
447						   processed */
448	unsigned long	d_canceled;		/* number of messages canceled
449						   by retries */
450	unsigned long	d_nocanceled;		/* retries that found nothing
451						   to cancel */
452	unsigned long	d_resets;		/* number of ipi-style requests
453						   processed */
454	unsigned long	d_rcanceled;		/* number of messages canceled
455						   by resets */
456};
457
458struct tunables {
459	int			*tunp;
460	int			deflt;
461};
462
463struct hub_and_pnode {
464	short			uvhub;
465	short			pnode;
466};
467
468struct socket_desc {
469	short			num_cpus;
470	short			cpu_number[MAX_CPUS_PER_SOCKET];
471};
472
473struct uvhub_desc {
474	unsigned short		socket_mask;
475	short			num_cpus;
476	short			uvhub;
477	short			pnode;
478	struct socket_desc	socket[2];
479};
480
481/*
482 * one per-cpu; to locate the software tables
483 */
484struct bau_control {
485	struct bau_desc		*descriptor_base;
486	struct bau_pq_entry	*queue_first;
487	struct bau_pq_entry	*queue_last;
488	struct bau_pq_entry	*bau_msg_head;
489	struct bau_control	*uvhub_master;
490	struct bau_control	*socket_master;
491	struct ptc_stats	*statp;
492	unsigned long		timeout_interval;
493	unsigned long		set_bau_on_time;
494	atomic_t		active_descriptor_count;
495	int			plugged_tries;
496	int			timeout_tries;
497	int			ipi_attempts;
498	int			conseccompletes;
499	int			baudisabled;
500	int			set_bau_off;
501	short			cpu;
502	short			osnode;
503	short			uvhub_cpu;
504	short			uvhub;
505	short			cpus_in_socket;
506	short			cpus_in_uvhub;
507	short			partition_base_pnode;
508	unsigned short		message_number;
509	unsigned short		uvhub_quiesce;
510	short			socket_acknowledge_count[DEST_Q_SIZE];
511	cycles_t		send_message;
512	spinlock_t		uvhub_lock;
513	spinlock_t		queue_lock;
514	/* tunables */
515	int			max_concurr;
516	int			max_concurr_const;
517	int			plugged_delay;
518	int			plugsb4reset;
519	int			timeoutsb4reset;
520	int			ipi_reset_limit;
521	int			complete_threshold;
522	int			cong_response_us;
523	int			cong_reps;
524	int			cong_period;
525	cycles_t		period_time;
526	long			period_requests;
527	struct hub_and_pnode	*thp;
528};
529
530static unsigned long read_mmr_uv2_status(void)
531{
532	return read_lmmr(UV2H_LB_BAU_SB_ACTIVATION_STATUS_2);
533}
534
535static void write_mmr_data_broadcast(int pnode, unsigned long mmr_image)
536{
537	write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image);
538}
539
540static void write_mmr_descriptor_base(int pnode, unsigned long mmr_image)
541{
542	write_gmmr(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, mmr_image);
543}
544
545static void write_mmr_activation(unsigned long index)
546{
547	write_lmmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
548}
549
550static void write_gmmr_activation(int pnode, unsigned long mmr_image)
551{
552	write_gmmr(pnode, UVH_LB_BAU_SB_ACTIVATION_CONTROL, mmr_image);
553}
554
555static void write_mmr_payload_first(int pnode, unsigned long mmr_image)
556{
557	write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, mmr_image);
558}
559
560static void write_mmr_payload_tail(int pnode, unsigned long mmr_image)
561{
562	write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, mmr_image);
563}
564
565static void write_mmr_payload_last(int pnode, unsigned long mmr_image)
566{
567	write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, mmr_image);
568}
569
570static void write_mmr_misc_control(int pnode, unsigned long mmr_image)
571{
572	write_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
573}
574
575static unsigned long read_mmr_misc_control(int pnode)
576{
577	return read_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL);
578}
579
580static void write_mmr_sw_ack(unsigned long mr)
581{
582	uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
583}
584
585static unsigned long read_mmr_sw_ack(void)
586{
587	return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
588}
589
590static unsigned long read_gmmr_sw_ack(int pnode)
591{
592	return read_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
593}
594
595static void write_mmr_data_config(int pnode, unsigned long mr)
596{
597	uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, mr);
598}
599
600static inline int bau_uvhub_isset(int uvhub, struct bau_targ_hubmask *dstp)
601{
602	return constant_test_bit(uvhub, &dstp->bits[0]);
603}
604static inline void bau_uvhub_set(int pnode, struct bau_targ_hubmask *dstp)
605{
606	__set_bit(pnode, &dstp->bits[0]);
607}
608static inline void bau_uvhubs_clear(struct bau_targ_hubmask *dstp,
609				    int nbits)
610{
611	bitmap_zero(&dstp->bits[0], nbits);
612}
613static inline int bau_uvhub_weight(struct bau_targ_hubmask *dstp)
614{
615	return bitmap_weight((unsigned long *)&dstp->bits[0],
616				UV_DISTRIBUTION_SIZE);
617}
618
619static inline void bau_cpubits_clear(struct bau_local_cpumask *dstp, int nbits)
620{
621	bitmap_zero(&dstp->bits, nbits);
622}
623
624extern void uv_bau_message_intr1(void);
625extern void uv_bau_timeout_intr1(void);
626
627struct atomic_short {
628	short counter;
629};
630
631/*
632 * atomic_read_short - read a short atomic variable
633 * @v: pointer of type atomic_short
634 *
635 * Atomically reads the value of @v.
636 */
637static inline int atomic_read_short(const struct atomic_short *v)
638{
639	return v->counter;
640}
641
642/*
643 * atom_asr - add and return a short int
644 * @i: short value to add
645 * @v: pointer of type atomic_short
646 *
647 * Atomically adds @i to @v and returns @i + @v
648 */
649static inline int atom_asr(short i, struct atomic_short *v)
650{
651	short __i = i;
652	asm volatile(LOCK_PREFIX "xaddw %0, %1"
653			: "+r" (i), "+m" (v->counter)
654			: : "memory");
655	return i + __i;
656}
657
658/*
659 * conditionally add 1 to *v, unless *v is >= u
660 * return 0 if we cannot add 1 to *v because it is >= u
661 * return 1 if we can add 1 to *v because it is < u
662 * the add is atomic
663 *
664 * This is close to atomic_add_unless(), but this allows the 'u' value
665 * to be lowered below the current 'v'.  atomic_add_unless can only stop
666 * on equal.
667 */
668static inline int atomic_inc_unless_ge(spinlock_t *lock, atomic_t *v, int u)
669{
670	spin_lock(lock);
671	if (atomic_read(v) >= u) {
672		spin_unlock(lock);
673		return 0;
674	}
675	atomic_inc(v);
676	spin_unlock(lock);
677	return 1;
678}
679
680#endif /* _ASM_X86_UV_UV_BAU_H */