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/arch/unicore32/mm/flush.c

https://bitbucket.org/ndreys/linux-sunxi
C | 98 lines | 54 code | 12 blank | 32 comment | 8 complexity | 617522b132e43918c76c2d26d1a5d014 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
 1/*
 2 * linux/arch/unicore32/mm/flush.c
 3 *
 4 * Code specific to PKUnity SoC and UniCore ISA
 5 *
 6 * Copyright (C) 2001-2010 GUAN Xue-tao
 7 *
 8 * This program is free software; you can redistribute it and/or modify
 9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#include <linux/module.h>
13#include <linux/mm.h>
14#include <linux/pagemap.h>
15
16#include <asm/cacheflush.h>
17#include <asm/system.h>
18#include <asm/tlbflush.h>
19
20void flush_cache_mm(struct mm_struct *mm)
21{
22}
23
24void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
25		unsigned long end)
26{
27	if (vma->vm_flags & VM_EXEC)
28		__flush_icache_all();
29}
30
31void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr,
32		unsigned long pfn)
33{
34}
35
36static void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
37			 unsigned long uaddr, void *kaddr, unsigned long len)
38{
39	/* VIPT non-aliasing D-cache */
40	if (vma->vm_flags & VM_EXEC) {
41		unsigned long addr = (unsigned long)kaddr;
42
43		__cpuc_coherent_kern_range(addr, addr + len);
44	}
45}
46
47/*
48 * Copy user data from/to a page which is mapped into a different
49 * processes address space.  Really, we want to allow our "user
50 * space" model to handle this.
51 *
52 * Note that this code needs to run on the current CPU.
53 */
54void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
55		       unsigned long uaddr, void *dst, const void *src,
56		       unsigned long len)
57{
58	memcpy(dst, src, len);
59	flush_ptrace_access(vma, page, uaddr, dst, len);
60}
61
62void __flush_dcache_page(struct address_space *mapping, struct page *page)
63{
64	/*
65	 * Writeback any data associated with the kernel mapping of this
66	 * page.  This ensures that data in the physical page is mutually
67	 * coherent with the kernels mapping.
68	 */
69	__cpuc_flush_kern_dcache_area(page_address(page), PAGE_SIZE);
70}
71
72/*
73 * Ensure cache coherency between kernel mapping and userspace mapping
74 * of this page.
75 */
76void flush_dcache_page(struct page *page)
77{
78	struct address_space *mapping;
79
80	/*
81	 * The zero page is never written to, so never has any dirty
82	 * cache lines, and therefore never needs to be flushed.
83	 */
84	if (page == ZERO_PAGE(0))
85		return;
86
87	mapping = page_mapping(page);
88
89	if (mapping && !mapping_mapped(mapping))
90		clear_bit(PG_dcache_clean, &page->flags);
91	else {
92		__flush_dcache_page(mapping, page);
93		if (mapping)
94			__flush_icache_all();
95		set_bit(PG_dcache_clean, &page->flags);
96	}
97}
98EXPORT_SYMBOL(flush_dcache_page);