/arch/tile/include/arch/spr_def_64.h
C++ Header | 173 lines | 155 code | 5 blank | 13 comment | 0 complexity | 44c4996540f319d4334a4d72e70006da MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
1/* 2 * Copyright 2011 Tilera Corporation. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation, version 2. 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 11 * NON INFRINGEMENT. See the GNU General Public License for 12 * more details. 13 */ 14 15#ifndef __DOXYGEN__ 16 17#ifndef __ARCH_SPR_DEF_H__ 18#define __ARCH_SPR_DEF_H__ 19 20#define SPR_AUX_PERF_COUNT_0 0x2105 21#define SPR_AUX_PERF_COUNT_1 0x2106 22#define SPR_AUX_PERF_COUNT_CTL 0x2107 23#define SPR_AUX_PERF_COUNT_STS 0x2108 24#define SPR_CMPEXCH_VALUE 0x2780 25#define SPR_CYCLE 0x2781 26#define SPR_DONE 0x2705 27#define SPR_DSTREAM_PF 0x2706 28#define SPR_EVENT_BEGIN 0x2782 29#define SPR_EVENT_END 0x2783 30#define SPR_EX_CONTEXT_0_0 0x2580 31#define SPR_EX_CONTEXT_0_1 0x2581 32#define SPR_EX_CONTEXT_0_1__PL_SHIFT 0 33#define SPR_EX_CONTEXT_0_1__PL_RMASK 0x3 34#define SPR_EX_CONTEXT_0_1__PL_MASK 0x3 35#define SPR_EX_CONTEXT_0_1__ICS_SHIFT 2 36#define SPR_EX_CONTEXT_0_1__ICS_RMASK 0x1 37#define SPR_EX_CONTEXT_0_1__ICS_MASK 0x4 38#define SPR_EX_CONTEXT_1_0 0x2480 39#define SPR_EX_CONTEXT_1_1 0x2481 40#define SPR_EX_CONTEXT_1_1__PL_SHIFT 0 41#define SPR_EX_CONTEXT_1_1__PL_RMASK 0x3 42#define SPR_EX_CONTEXT_1_1__PL_MASK 0x3 43#define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2 44#define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1 45#define SPR_EX_CONTEXT_1_1__ICS_MASK 0x4 46#define SPR_EX_CONTEXT_2_0 0x2380 47#define SPR_EX_CONTEXT_2_1 0x2381 48#define SPR_EX_CONTEXT_2_1__PL_SHIFT 0 49#define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3 50#define SPR_EX_CONTEXT_2_1__PL_MASK 0x3 51#define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2 52#define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1 53#define SPR_EX_CONTEXT_2_1__ICS_MASK 0x4 54#define SPR_FAIL 0x2707 55#define SPR_ILL_TRANS_REASON__I_STREAM_VA_RMASK 0x1 56#define SPR_INTCTRL_0_STATUS 0x2505 57#define SPR_INTCTRL_1_STATUS 0x2405 58#define SPR_INTCTRL_2_STATUS 0x2305 59#define SPR_INTERRUPT_CRITICAL_SECTION 0x2708 60#define SPR_INTERRUPT_MASK_0 0x2506 61#define SPR_INTERRUPT_MASK_1 0x2406 62#define SPR_INTERRUPT_MASK_2 0x2306 63#define SPR_INTERRUPT_MASK_RESET_0 0x2507 64#define SPR_INTERRUPT_MASK_RESET_1 0x2407 65#define SPR_INTERRUPT_MASK_RESET_2 0x2307 66#define SPR_INTERRUPT_MASK_SET_0 0x2508 67#define SPR_INTERRUPT_MASK_SET_1 0x2408 68#define SPR_INTERRUPT_MASK_SET_2 0x2308 69#define SPR_INTERRUPT_VECTOR_BASE_0 0x2509 70#define SPR_INTERRUPT_VECTOR_BASE_1 0x2409 71#define SPR_INTERRUPT_VECTOR_BASE_2 0x2309 72#define SPR_INTERRUPT_VECTOR_BASE_3 0x2209 73#define SPR_IPI_EVENT_0 0x1f05 74#define SPR_IPI_EVENT_1 0x1e05 75#define SPR_IPI_EVENT_2 0x1d05 76#define SPR_IPI_EVENT_RESET_0 0x1f06 77#define SPR_IPI_EVENT_RESET_1 0x1e06 78#define SPR_IPI_EVENT_RESET_2 0x1d06 79#define SPR_IPI_EVENT_SET_0 0x1f07 80#define SPR_IPI_EVENT_SET_1 0x1e07 81#define SPR_IPI_EVENT_SET_2 0x1d07 82#define SPR_IPI_MASK_0 0x1f08 83#define SPR_IPI_MASK_1 0x1e08 84#define SPR_IPI_MASK_2 0x1d08 85#define SPR_IPI_MASK_RESET_0 0x1f09 86#define SPR_IPI_MASK_RESET_1 0x1e09 87#define SPR_IPI_MASK_RESET_2 0x1d09 88#define SPR_IPI_MASK_SET_0 0x1f0a 89#define SPR_IPI_MASK_SET_1 0x1e0a 90#define SPR_IPI_MASK_SET_2 0x1d0a 91#define SPR_MPL_AUX_TILE_TIMER_SET_0 0x1700 92#define SPR_MPL_AUX_TILE_TIMER_SET_1 0x1701 93#define SPR_MPL_AUX_TILE_TIMER_SET_2 0x1702 94#define SPR_MPL_INTCTRL_0_SET_0 0x2500 95#define SPR_MPL_INTCTRL_0_SET_1 0x2501 96#define SPR_MPL_INTCTRL_0_SET_2 0x2502 97#define SPR_MPL_INTCTRL_1_SET_0 0x2400 98#define SPR_MPL_INTCTRL_1_SET_1 0x2401 99#define SPR_MPL_INTCTRL_1_SET_2 0x2402 100#define SPR_MPL_INTCTRL_2_SET_0 0x2300 101#define SPR_MPL_INTCTRL_2_SET_1 0x2301 102#define SPR_MPL_INTCTRL_2_SET_2 0x2302 103#define SPR_MPL_UDN_ACCESS_SET_0 0x0b00 104#define SPR_MPL_UDN_ACCESS_SET_1 0x0b01 105#define SPR_MPL_UDN_ACCESS_SET_2 0x0b02 106#define SPR_MPL_UDN_AVAIL_SET_0 0x1b00 107#define SPR_MPL_UDN_AVAIL_SET_1 0x1b01 108#define SPR_MPL_UDN_AVAIL_SET_2 0x1b02 109#define SPR_MPL_UDN_COMPLETE_SET_0 0x0600 110#define SPR_MPL_UDN_COMPLETE_SET_1 0x0601 111#define SPR_MPL_UDN_COMPLETE_SET_2 0x0602 112#define SPR_MPL_UDN_FIREWALL_SET_0 0x1500 113#define SPR_MPL_UDN_FIREWALL_SET_1 0x1501 114#define SPR_MPL_UDN_FIREWALL_SET_2 0x1502 115#define SPR_MPL_UDN_TIMER_SET_0 0x1900 116#define SPR_MPL_UDN_TIMER_SET_1 0x1901 117#define SPR_MPL_UDN_TIMER_SET_2 0x1902 118#define SPR_MPL_WORLD_ACCESS_SET_0 0x2700 119#define SPR_MPL_WORLD_ACCESS_SET_1 0x2701 120#define SPR_MPL_WORLD_ACCESS_SET_2 0x2702 121#define SPR_PASS 0x2709 122#define SPR_PERF_COUNT_0 0x2005 123#define SPR_PERF_COUNT_1 0x2006 124#define SPR_PERF_COUNT_CTL 0x2007 125#define SPR_PERF_COUNT_DN_CTL 0x2008 126#define SPR_PERF_COUNT_STS 0x2009 127#define SPR_PROC_STATUS 0x2784 128#define SPR_SIM_CONTROL 0x2785 129#define SPR_SINGLE_STEP_CONTROL_0 0x0405 130#define SPR_SINGLE_STEP_CONTROL_0__CANCELED_MASK 0x1 131#define SPR_SINGLE_STEP_CONTROL_0__INHIBIT_MASK 0x2 132#define SPR_SINGLE_STEP_CONTROL_1 0x0305 133#define SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK 0x1 134#define SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK 0x2 135#define SPR_SINGLE_STEP_CONTROL_2 0x0205 136#define SPR_SINGLE_STEP_CONTROL_2__CANCELED_MASK 0x1 137#define SPR_SINGLE_STEP_CONTROL_2__INHIBIT_MASK 0x2 138#define SPR_SINGLE_STEP_EN_0_0 0x250a 139#define SPR_SINGLE_STEP_EN_0_1 0x240a 140#define SPR_SINGLE_STEP_EN_0_2 0x230a 141#define SPR_SINGLE_STEP_EN_1_0 0x250b 142#define SPR_SINGLE_STEP_EN_1_1 0x240b 143#define SPR_SINGLE_STEP_EN_1_2 0x230b 144#define SPR_SINGLE_STEP_EN_2_0 0x250c 145#define SPR_SINGLE_STEP_EN_2_1 0x240c 146#define SPR_SINGLE_STEP_EN_2_2 0x230c 147#define SPR_SYSTEM_SAVE_0_0 0x2582 148#define SPR_SYSTEM_SAVE_0_1 0x2583 149#define SPR_SYSTEM_SAVE_0_2 0x2584 150#define SPR_SYSTEM_SAVE_0_3 0x2585 151#define SPR_SYSTEM_SAVE_1_0 0x2482 152#define SPR_SYSTEM_SAVE_1_1 0x2483 153#define SPR_SYSTEM_SAVE_1_2 0x2484 154#define SPR_SYSTEM_SAVE_1_3 0x2485 155#define SPR_SYSTEM_SAVE_2_0 0x2382 156#define SPR_SYSTEM_SAVE_2_1 0x2383 157#define SPR_SYSTEM_SAVE_2_2 0x2384 158#define SPR_SYSTEM_SAVE_2_3 0x2385 159#define SPR_TILE_COORD 0x270b 160#define SPR_TILE_RTF_HWM 0x270c 161#define SPR_TILE_TIMER_CONTROL 0x1605 162#define SPR_UDN_AVAIL_EN 0x1b05 163#define SPR_UDN_DATA_AVAIL 0x0b80 164#define SPR_UDN_DEADLOCK_TIMEOUT 0x1906 165#define SPR_UDN_DEMUX_COUNT_0 0x0b05 166#define SPR_UDN_DEMUX_COUNT_1 0x0b06 167#define SPR_UDN_DEMUX_COUNT_2 0x0b07 168#define SPR_UDN_DEMUX_COUNT_3 0x0b08 169#define SPR_UDN_DIRECTION_PROTECT 0x1505 170 171#endif /* !defined(__ARCH_SPR_DEF_H__) */ 172 173#endif /* !defined(__DOXYGEN__) */