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/arch/sh/kernel/cpu/sh4a/setup-sh7757.c

https://bitbucket.org/ndreys/linux-sunxi
C | 1213 lines | 1078 code | 82 blank | 53 comment | 1 complexity | 6b30b32c13ed1965804676fdd987520a MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
   1/*
   2 * SH7757 Setup
   3 *
   4 * Copyright (C) 2009, 2011  Renesas Solutions Corp.
   5 *
   6 *  based on setup-sh7785.c : Copyright (C) 2007  Paul Mundt
   7 *
   8 * This file is subject to the terms and conditions of the GNU General Public
   9 * License.  See the file "COPYING" in the main directory of this archive
  10 * for more details.
  11 */
  12#include <linux/platform_device.h>
  13#include <linux/init.h>
  14#include <linux/serial.h>
  15#include <linux/serial_sci.h>
  16#include <linux/io.h>
  17#include <linux/mm.h>
  18#include <linux/sh_timer.h>
  19#include <linux/sh_dma.h>
  20
  21#include <cpu/dma-register.h>
  22#include <cpu/sh7757.h>
  23
  24static struct plat_sci_port scif2_platform_data = {
  25	.mapbase	= 0xfe4b0000,		/* SCIF2 */
  26	.flags		= UPF_BOOT_AUTOCONF,
  27	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  28	.scbrr_algo_id	= SCBRR_ALGO_2,
  29	.type		= PORT_SCIF,
  30	.irqs		= { 40, 40, 40, 40 },
  31};
  32
  33static struct platform_device scif2_device = {
  34	.name		= "sh-sci",
  35	.id		= 0,
  36	.dev		= {
  37		.platform_data	= &scif2_platform_data,
  38	},
  39};
  40
  41static struct plat_sci_port scif3_platform_data = {
  42	.mapbase	= 0xfe4c0000,		/* SCIF3 */
  43	.flags		= UPF_BOOT_AUTOCONF,
  44	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  45	.scbrr_algo_id	= SCBRR_ALGO_2,
  46	.type		= PORT_SCIF,
  47	.irqs		= { 76, 76, 76, 76 },
  48};
  49
  50static struct platform_device scif3_device = {
  51	.name		= "sh-sci",
  52	.id		= 1,
  53	.dev		= {
  54		.platform_data	= &scif3_platform_data,
  55	},
  56};
  57
  58static struct plat_sci_port scif4_platform_data = {
  59	.mapbase	= 0xfe4d0000,		/* SCIF4 */
  60	.flags		= UPF_BOOT_AUTOCONF,
  61	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  62	.scbrr_algo_id	= SCBRR_ALGO_2,
  63	.type		= PORT_SCIF,
  64	.irqs		= { 104, 104, 104, 104 },
  65};
  66
  67static struct platform_device scif4_device = {
  68	.name		= "sh-sci",
  69	.id		= 2,
  70	.dev		= {
  71		.platform_data	= &scif4_platform_data,
  72	},
  73};
  74
  75static struct sh_timer_config tmu0_platform_data = {
  76	.channel_offset = 0x04,
  77	.timer_bit = 0,
  78	.clockevent_rating = 200,
  79};
  80
  81static struct resource tmu0_resources[] = {
  82	[0] = {
  83		.start	= 0xfe430008,
  84		.end	= 0xfe430013,
  85		.flags	= IORESOURCE_MEM,
  86	},
  87	[1] = {
  88		.start	= 28,
  89		.flags	= IORESOURCE_IRQ,
  90	},
  91};
  92
  93static struct platform_device tmu0_device = {
  94	.name		= "sh_tmu",
  95	.id		= 0,
  96	.dev = {
  97		.platform_data	= &tmu0_platform_data,
  98	},
  99	.resource	= tmu0_resources,
 100	.num_resources	= ARRAY_SIZE(tmu0_resources),
 101};
 102
 103static struct sh_timer_config tmu1_platform_data = {
 104	.channel_offset = 0x10,
 105	.timer_bit = 1,
 106	.clocksource_rating = 200,
 107};
 108
 109static struct resource tmu1_resources[] = {
 110	[0] = {
 111		.start	= 0xfe430014,
 112		.end	= 0xfe43001f,
 113		.flags	= IORESOURCE_MEM,
 114	},
 115	[1] = {
 116		.start	= 29,
 117		.flags	= IORESOURCE_IRQ,
 118	},
 119};
 120
 121static struct platform_device tmu1_device = {
 122	.name		= "sh_tmu",
 123	.id		= 1,
 124	.dev = {
 125		.platform_data	= &tmu1_platform_data,
 126	},
 127	.resource	= tmu1_resources,
 128	.num_resources	= ARRAY_SIZE(tmu1_resources),
 129};
 130
 131static struct resource spi0_resources[] = {
 132	[0] = {
 133		.start	= 0xfe002000,
 134		.end	= 0xfe0020ff,
 135		.flags	= IORESOURCE_MEM,
 136	},
 137	[1] = {
 138		.start	= 86,
 139		.flags	= IORESOURCE_IRQ,
 140	},
 141};
 142
 143/* DMA */
 144static const struct sh_dmae_slave_config sh7757_dmae0_slaves[] = {
 145	{
 146		.slave_id	= SHDMA_SLAVE_SDHI_TX,
 147		.addr		= 0x1fe50030,
 148		.chcr		= SM_INC | 0x800 | 0x40000000 |
 149				  TS_INDEX2VAL(XMIT_SZ_16BIT),
 150		.mid_rid	= 0xc5,
 151	},
 152	{
 153		.slave_id	= SHDMA_SLAVE_SDHI_RX,
 154		.addr		= 0x1fe50030,
 155		.chcr		= DM_INC | 0x800 | 0x40000000 |
 156				  TS_INDEX2VAL(XMIT_SZ_16BIT),
 157		.mid_rid	= 0xc6,
 158	},
 159	{
 160		.slave_id	= SHDMA_SLAVE_MMCIF_TX,
 161		.addr		= 0x1fcb0034,
 162		.chcr		= SM_INC | 0x800 | 0x40000000 |
 163				  TS_INDEX2VAL(XMIT_SZ_32BIT),
 164		.mid_rid	= 0xd3,
 165	},
 166	{
 167		.slave_id	= SHDMA_SLAVE_MMCIF_RX,
 168		.addr		= 0x1fcb0034,
 169		.chcr		= DM_INC | 0x800 | 0x40000000 |
 170				  TS_INDEX2VAL(XMIT_SZ_32BIT),
 171		.mid_rid	= 0xd7,
 172	},
 173};
 174
 175static const struct sh_dmae_slave_config sh7757_dmae1_slaves[] = {
 176	{
 177		.slave_id	= SHDMA_SLAVE_SCIF2_TX,
 178		.addr		= 0x1f4b000c,
 179		.chcr		= SM_INC | 0x800 | 0x40000000 |
 180				  TS_INDEX2VAL(XMIT_SZ_8BIT),
 181		.mid_rid	= 0x21,
 182	},
 183	{
 184		.slave_id	= SHDMA_SLAVE_SCIF2_RX,
 185		.addr		= 0x1f4b0014,
 186		.chcr		= DM_INC | 0x800 | 0x40000000 |
 187				  TS_INDEX2VAL(XMIT_SZ_8BIT),
 188		.mid_rid	= 0x22,
 189	},
 190	{
 191		.slave_id	= SHDMA_SLAVE_SCIF3_TX,
 192		.addr		= 0x1f4c000c,
 193		.chcr		= SM_INC | 0x800 | 0x40000000 |
 194				  TS_INDEX2VAL(XMIT_SZ_8BIT),
 195		.mid_rid	= 0x29,
 196	},
 197	{
 198		.slave_id	= SHDMA_SLAVE_SCIF3_RX,
 199		.addr		= 0x1f4c0014,
 200		.chcr		= DM_INC | 0x800 | 0x40000000 |
 201				  TS_INDEX2VAL(XMIT_SZ_8BIT),
 202		.mid_rid	= 0x2a,
 203	},
 204	{
 205		.slave_id	= SHDMA_SLAVE_SCIF4_TX,
 206		.addr		= 0x1f4d000c,
 207		.chcr		= SM_INC | 0x800 | 0x40000000 |
 208				  TS_INDEX2VAL(XMIT_SZ_8BIT),
 209		.mid_rid	= 0x41,
 210	},
 211	{
 212		.slave_id	= SHDMA_SLAVE_SCIF4_RX,
 213		.addr		= 0x1f4d0014,
 214		.chcr		= DM_INC | 0x800 | 0x40000000 |
 215				  TS_INDEX2VAL(XMIT_SZ_8BIT),
 216		.mid_rid	= 0x42,
 217	},
 218};
 219
 220static const struct sh_dmae_slave_config sh7757_dmae2_slaves[] = {
 221	{
 222		.slave_id	= SHDMA_SLAVE_RIIC0_TX,
 223		.addr		= 0x1e500012,
 224		.chcr		= SM_INC | 0x800 | 0x40000000 |
 225				  TS_INDEX2VAL(XMIT_SZ_8BIT),
 226		.mid_rid	= 0x21,
 227	},
 228	{
 229		.slave_id	= SHDMA_SLAVE_RIIC0_RX,
 230		.addr		= 0x1e500013,
 231		.chcr		= DM_INC | 0x800 | 0x40000000 |
 232				  TS_INDEX2VAL(XMIT_SZ_8BIT),
 233		.mid_rid	= 0x22,
 234	},
 235	{
 236		.slave_id	= SHDMA_SLAVE_RIIC1_TX,
 237		.addr		= 0x1e510012,
 238		.chcr		= SM_INC | 0x800 | 0x40000000 |
 239				  TS_INDEX2VAL(XMIT_SZ_8BIT),
 240		.mid_rid	= 0x29,
 241	},
 242	{
 243		.slave_id	= SHDMA_SLAVE_RIIC1_RX,
 244		.addr		= 0x1e510013,
 245		.chcr		= DM_INC | 0x800 | 0x40000000 |
 246				  TS_INDEX2VAL(XMIT_SZ_8BIT),
 247		.mid_rid	= 0x2a,
 248	},
 249	{
 250		.slave_id	= SHDMA_SLAVE_RIIC2_TX,
 251		.addr		= 0x1e520012,
 252		.chcr		= SM_INC | 0x800 | 0x40000000 |
 253				  TS_INDEX2VAL(XMIT_SZ_8BIT),
 254		.mid_rid	= 0xa1,
 255	},
 256	{
 257		.slave_id	= SHDMA_SLAVE_RIIC2_RX,
 258		.addr		= 0x1e520013,
 259		.chcr		= DM_INC | 0x800 | 0x40000000 |
 260				  TS_INDEX2VAL(XMIT_SZ_8BIT),
 261		.mid_rid	= 0xa2,
 262	},
 263	{
 264		.slave_id	= SHDMA_SLAVE_RIIC3_TX,
 265		.addr		= 0x1e530012,
 266		.chcr		= SM_INC | 0x800 | 0x40000000 |
 267				  TS_INDEX2VAL(XMIT_SZ_8BIT),
 268		.mid_rid	= 0xa9,
 269	},
 270	{
 271		.slave_id	= SHDMA_SLAVE_RIIC3_RX,
 272		.addr		= 0x1e530013,
 273		.chcr		= DM_INC | 0x800 | 0x40000000 |
 274				  TS_INDEX2VAL(XMIT_SZ_8BIT),
 275		.mid_rid	= 0xaf,
 276	},
 277	{
 278		.slave_id	= SHDMA_SLAVE_RIIC4_TX,
 279		.addr		= 0x1e540012,
 280		.chcr		= SM_INC | 0x800 | 0x40000000 |
 281				  TS_INDEX2VAL(XMIT_SZ_8BIT),
 282		.mid_rid	= 0xc5,
 283	},
 284	{
 285		.slave_id	= SHDMA_SLAVE_RIIC4_RX,
 286		.addr		= 0x1e540013,
 287		.chcr		= DM_INC | 0x800 | 0x40000000 |
 288				  TS_INDEX2VAL(XMIT_SZ_8BIT),
 289		.mid_rid	= 0xc6,
 290	},
 291};
 292
 293static const struct sh_dmae_slave_config sh7757_dmae3_slaves[] = {
 294	{
 295		.slave_id	= SHDMA_SLAVE_RIIC5_TX,
 296		.addr		= 0x1e550012,
 297		.chcr		= SM_INC | 0x800 | 0x40000000 |
 298				  TS_INDEX2VAL(XMIT_SZ_8BIT),
 299		.mid_rid	= 0x21,
 300	},
 301	{
 302		.slave_id	= SHDMA_SLAVE_RIIC5_RX,
 303		.addr		= 0x1e550013,
 304		.chcr		= DM_INC | 0x800 | 0x40000000 |
 305				  TS_INDEX2VAL(XMIT_SZ_8BIT),
 306		.mid_rid	= 0x22,
 307	},
 308	{
 309		.slave_id	= SHDMA_SLAVE_RIIC6_TX,
 310		.addr		= 0x1e560012,
 311		.chcr		= SM_INC | 0x800 | 0x40000000 |
 312				  TS_INDEX2VAL(XMIT_SZ_8BIT),
 313		.mid_rid	= 0x29,
 314	},
 315	{
 316		.slave_id	= SHDMA_SLAVE_RIIC6_RX,
 317		.addr		= 0x1e560013,
 318		.chcr		= DM_INC | 0x800 | 0x40000000 |
 319				  TS_INDEX2VAL(XMIT_SZ_8BIT),
 320		.mid_rid	= 0x2a,
 321	},
 322	{
 323		.slave_id	= SHDMA_SLAVE_RIIC7_TX,
 324		.addr		= 0x1e570012,
 325		.chcr		= SM_INC | 0x800 | 0x40000000 |
 326				  TS_INDEX2VAL(XMIT_SZ_8BIT),
 327		.mid_rid	= 0x41,
 328	},
 329	{
 330		.slave_id	= SHDMA_SLAVE_RIIC7_RX,
 331		.addr		= 0x1e570013,
 332		.chcr		= DM_INC | 0x800 | 0x40000000 |
 333				  TS_INDEX2VAL(XMIT_SZ_8BIT),
 334		.mid_rid	= 0x42,
 335	},
 336	{
 337		.slave_id	= SHDMA_SLAVE_RIIC8_TX,
 338		.addr		= 0x1e580012,
 339		.chcr		= SM_INC | 0x800 | 0x40000000 |
 340				  TS_INDEX2VAL(XMIT_SZ_8BIT),
 341		.mid_rid	= 0x45,
 342	},
 343	{
 344		.slave_id	= SHDMA_SLAVE_RIIC8_RX,
 345		.addr		= 0x1e580013,
 346		.chcr		= DM_INC | 0x800 | 0x40000000 |
 347				  TS_INDEX2VAL(XMIT_SZ_8BIT),
 348		.mid_rid	= 0x46,
 349	},
 350	{
 351		.slave_id	= SHDMA_SLAVE_RIIC9_TX,
 352		.addr		= 0x1e590012,
 353		.chcr		= SM_INC | 0x800 | 0x40000000 |
 354				  TS_INDEX2VAL(XMIT_SZ_8BIT),
 355		.mid_rid	= 0x51,
 356	},
 357	{
 358		.slave_id	= SHDMA_SLAVE_RIIC9_RX,
 359		.addr		= 0x1e590013,
 360		.chcr		= DM_INC | 0x800 | 0x40000000 |
 361				  TS_INDEX2VAL(XMIT_SZ_8BIT),
 362		.mid_rid	= 0x52,
 363	},
 364};
 365
 366static const struct sh_dmae_channel sh7757_dmae_channels[] = {
 367	{
 368		.offset = 0,
 369		.dmars = 0,
 370		.dmars_bit = 0,
 371	}, {
 372		.offset = 0x10,
 373		.dmars = 0,
 374		.dmars_bit = 8,
 375	}, {
 376		.offset = 0x20,
 377		.dmars = 4,
 378		.dmars_bit = 0,
 379	}, {
 380		.offset = 0x30,
 381		.dmars = 4,
 382		.dmars_bit = 8,
 383	}, {
 384		.offset = 0x50,
 385		.dmars = 8,
 386		.dmars_bit = 0,
 387	}, {
 388		.offset = 0x60,
 389		.dmars = 8,
 390		.dmars_bit = 8,
 391	}
 392};
 393
 394static const unsigned int ts_shift[] = TS_SHIFT;
 395
 396static struct sh_dmae_pdata dma0_platform_data = {
 397	.slave		= sh7757_dmae0_slaves,
 398	.slave_num	= ARRAY_SIZE(sh7757_dmae0_slaves),
 399	.channel	= sh7757_dmae_channels,
 400	.channel_num	= ARRAY_SIZE(sh7757_dmae_channels),
 401	.ts_low_shift	= CHCR_TS_LOW_SHIFT,
 402	.ts_low_mask	= CHCR_TS_LOW_MASK,
 403	.ts_high_shift	= CHCR_TS_HIGH_SHIFT,
 404	.ts_high_mask	= CHCR_TS_HIGH_MASK,
 405	.ts_shift	= ts_shift,
 406	.ts_shift_num	= ARRAY_SIZE(ts_shift),
 407	.dmaor_init	= DMAOR_INIT,
 408};
 409
 410static struct sh_dmae_pdata dma1_platform_data = {
 411	.slave		= sh7757_dmae1_slaves,
 412	.slave_num	= ARRAY_SIZE(sh7757_dmae1_slaves),
 413	.channel	= sh7757_dmae_channels,
 414	.channel_num	= ARRAY_SIZE(sh7757_dmae_channels),
 415	.ts_low_shift	= CHCR_TS_LOW_SHIFT,
 416	.ts_low_mask	= CHCR_TS_LOW_MASK,
 417	.ts_high_shift	= CHCR_TS_HIGH_SHIFT,
 418	.ts_high_mask	= CHCR_TS_HIGH_MASK,
 419	.ts_shift	= ts_shift,
 420	.ts_shift_num	= ARRAY_SIZE(ts_shift),
 421	.dmaor_init	= DMAOR_INIT,
 422};
 423
 424static struct sh_dmae_pdata dma2_platform_data = {
 425	.slave		= sh7757_dmae2_slaves,
 426	.slave_num	= ARRAY_SIZE(sh7757_dmae2_slaves),
 427	.channel	= sh7757_dmae_channels,
 428	.channel_num	= ARRAY_SIZE(sh7757_dmae_channels),
 429	.ts_low_shift	= CHCR_TS_LOW_SHIFT,
 430	.ts_low_mask	= CHCR_TS_LOW_MASK,
 431	.ts_high_shift	= CHCR_TS_HIGH_SHIFT,
 432	.ts_high_mask	= CHCR_TS_HIGH_MASK,
 433	.ts_shift	= ts_shift,
 434	.ts_shift_num	= ARRAY_SIZE(ts_shift),
 435	.dmaor_init	= DMAOR_INIT,
 436};
 437
 438static struct sh_dmae_pdata dma3_platform_data = {
 439	.slave		= sh7757_dmae3_slaves,
 440	.slave_num	= ARRAY_SIZE(sh7757_dmae3_slaves),
 441	.channel	= sh7757_dmae_channels,
 442	.channel_num	= ARRAY_SIZE(sh7757_dmae_channels),
 443	.ts_low_shift	= CHCR_TS_LOW_SHIFT,
 444	.ts_low_mask	= CHCR_TS_LOW_MASK,
 445	.ts_high_shift	= CHCR_TS_HIGH_SHIFT,
 446	.ts_high_mask	= CHCR_TS_HIGH_MASK,
 447	.ts_shift	= ts_shift,
 448	.ts_shift_num	= ARRAY_SIZE(ts_shift),
 449	.dmaor_init	= DMAOR_INIT,
 450};
 451
 452/* channel 0 to 5 */
 453static struct resource sh7757_dmae0_resources[] = {
 454	[0] = {
 455		/* Channel registers and DMAOR */
 456		.start	= 0xff608020,
 457		.end	= 0xff60808f,
 458		.flags	= IORESOURCE_MEM,
 459	},
 460	[1] = {
 461		/* DMARSx */
 462		.start	= 0xff609000,
 463		.end	= 0xff60900b,
 464		.flags	= IORESOURCE_MEM,
 465	},
 466	{
 467		.start	= 34,
 468		.end	= 34,
 469		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 470	},
 471};
 472
 473/* channel 6 to 11 */
 474static struct resource sh7757_dmae1_resources[] = {
 475	[0] = {
 476		/* Channel registers and DMAOR */
 477		.start	= 0xff618020,
 478		.end	= 0xff61808f,
 479		.flags	= IORESOURCE_MEM,
 480	},
 481	[1] = {
 482		/* DMARSx */
 483		.start	= 0xff619000,
 484		.end	= 0xff61900b,
 485		.flags	= IORESOURCE_MEM,
 486	},
 487	{
 488		/* DMA error */
 489		.start	= 34,
 490		.end	= 34,
 491		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 492	},
 493	{
 494		/* IRQ for channels 4 */
 495		.start	= 46,
 496		.end	= 46,
 497		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 498	},
 499	{
 500		/* IRQ for channels 5 */
 501		.start	= 46,
 502		.end	= 46,
 503		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 504	},
 505	{
 506		/* IRQ for channels 6 */
 507		.start	= 88,
 508		.end	= 88,
 509		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 510	},
 511	{
 512		/* IRQ for channels 7 */
 513		.start	= 88,
 514		.end	= 88,
 515		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 516	},
 517	{
 518		/* IRQ for channels 8 */
 519		.start	= 88,
 520		.end	= 88,
 521		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 522	},
 523	{
 524		/* IRQ for channels 9 */
 525		.start	= 88,
 526		.end	= 88,
 527		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 528	},
 529	{
 530		/* IRQ for channels 10 */
 531		.start	= 88,
 532		.end	= 88,
 533		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 534	},
 535	{
 536		/* IRQ for channels 11 */
 537		.start	= 88,
 538		.end	= 88,
 539		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 540	},
 541};
 542
 543/* channel 12 to 17 */
 544static struct resource sh7757_dmae2_resources[] = {
 545	[0] = {
 546		/* Channel registers and DMAOR */
 547		.start	= 0xff708020,
 548		.end	= 0xff70808f,
 549		.flags	= IORESOURCE_MEM,
 550	},
 551	[1] = {
 552		/* DMARSx */
 553		.start	= 0xff709000,
 554		.end	= 0xff70900b,
 555		.flags	= IORESOURCE_MEM,
 556	},
 557	{
 558		/* DMA error */
 559		.start	= 323,
 560		.end	= 323,
 561		.flags	= IORESOURCE_IRQ,
 562	},
 563	{
 564		/* IRQ for channels 12 to 16 */
 565		.start	= 272,
 566		.end	= 276,
 567		.flags	= IORESOURCE_IRQ,
 568	},
 569	{
 570		/* IRQ for channel 17 */
 571		.start	= 279,
 572		.end	= 279,
 573		.flags	= IORESOURCE_IRQ,
 574	},
 575};
 576
 577/* channel 18 to 23 */
 578static struct resource sh7757_dmae3_resources[] = {
 579	[0] = {
 580		/* Channel registers and DMAOR */
 581		.start	= 0xff718020,
 582		.end	= 0xff71808f,
 583		.flags	= IORESOURCE_MEM,
 584	},
 585	[1] = {
 586		/* DMARSx */
 587		.start	= 0xff719000,
 588		.end	= 0xff71900b,
 589		.flags	= IORESOURCE_MEM,
 590	},
 591	{
 592		/* DMA error */
 593		.start	= 324,
 594		.end	= 324,
 595		.flags	= IORESOURCE_IRQ,
 596	},
 597	{
 598		/* IRQ for channels 18 to 22 */
 599		.start	= 280,
 600		.end	= 284,
 601		.flags	= IORESOURCE_IRQ,
 602	},
 603	{
 604		/* IRQ for channel 23 */
 605		.start	= 288,
 606		.end	= 288,
 607		.flags	= IORESOURCE_IRQ,
 608	},
 609};
 610
 611static struct platform_device dma0_device = {
 612	.name           = "sh-dma-engine",
 613	.id             = 0,
 614	.resource	= sh7757_dmae0_resources,
 615	.num_resources	= ARRAY_SIZE(sh7757_dmae0_resources),
 616	.dev            = {
 617		.platform_data	= &dma0_platform_data,
 618	},
 619};
 620
 621static struct platform_device dma1_device = {
 622	.name		= "sh-dma-engine",
 623	.id		= 1,
 624	.resource	= sh7757_dmae1_resources,
 625	.num_resources	= ARRAY_SIZE(sh7757_dmae1_resources),
 626	.dev		= {
 627		.platform_data	= &dma1_platform_data,
 628	},
 629};
 630
 631static struct platform_device dma2_device = {
 632	.name		= "sh-dma-engine",
 633	.id		= 2,
 634	.resource	= sh7757_dmae2_resources,
 635	.num_resources	= ARRAY_SIZE(sh7757_dmae2_resources),
 636	.dev		= {
 637		.platform_data	= &dma2_platform_data,
 638	},
 639};
 640
 641static struct platform_device dma3_device = {
 642	.name		= "sh-dma-engine",
 643	.id		= 3,
 644	.resource	= sh7757_dmae3_resources,
 645	.num_resources	= ARRAY_SIZE(sh7757_dmae3_resources),
 646	.dev		= {
 647		.platform_data	= &dma3_platform_data,
 648	},
 649};
 650
 651static struct platform_device spi0_device = {
 652	.name	= "sh_spi",
 653	.id	= 0,
 654	.dev	= {
 655		.dma_mask		= NULL,
 656		.coherent_dma_mask	= 0xffffffff,
 657	},
 658	.num_resources	= ARRAY_SIZE(spi0_resources),
 659	.resource	= spi0_resources,
 660};
 661
 662static struct resource usb_ehci_resources[] = {
 663	[0] = {
 664		.start	= 0xfe4f1000,
 665		.end	= 0xfe4f10ff,
 666		.flags	= IORESOURCE_MEM,
 667	},
 668	[1] = {
 669		.start	= 57,
 670		.end	= 57,
 671		.flags	= IORESOURCE_IRQ,
 672	},
 673};
 674
 675static struct platform_device usb_ehci_device = {
 676	.name		= "sh_ehci",
 677	.id		= -1,
 678	.dev = {
 679		.dma_mask = &usb_ehci_device.dev.coherent_dma_mask,
 680		.coherent_dma_mask = DMA_BIT_MASK(32),
 681	},
 682	.num_resources	= ARRAY_SIZE(usb_ehci_resources),
 683	.resource	= usb_ehci_resources,
 684};
 685
 686static struct resource usb_ohci_resources[] = {
 687	[0] = {
 688		.start	= 0xfe4f1800,
 689		.end	= 0xfe4f18ff,
 690		.flags	= IORESOURCE_MEM,
 691	},
 692	[1] = {
 693		.start	= 57,
 694		.end	= 57,
 695		.flags	= IORESOURCE_IRQ,
 696	},
 697};
 698
 699static struct platform_device usb_ohci_device = {
 700	.name		= "sh_ohci",
 701	.id		= -1,
 702	.dev = {
 703		.dma_mask = &usb_ohci_device.dev.coherent_dma_mask,
 704		.coherent_dma_mask = DMA_BIT_MASK(32),
 705	},
 706	.num_resources	= ARRAY_SIZE(usb_ohci_resources),
 707	.resource	= usb_ohci_resources,
 708};
 709
 710static struct platform_device *sh7757_devices[] __initdata = {
 711	&scif2_device,
 712	&scif3_device,
 713	&scif4_device,
 714	&tmu0_device,
 715	&tmu1_device,
 716	&dma0_device,
 717	&dma1_device,
 718	&dma2_device,
 719	&dma3_device,
 720	&spi0_device,
 721	&usb_ehci_device,
 722	&usb_ohci_device,
 723};
 724
 725static int __init sh7757_devices_setup(void)
 726{
 727	return platform_add_devices(sh7757_devices,
 728				    ARRAY_SIZE(sh7757_devices));
 729}
 730arch_initcall(sh7757_devices_setup);
 731
 732static struct platform_device *sh7757_early_devices[] __initdata = {
 733	&scif2_device,
 734	&scif3_device,
 735	&scif4_device,
 736	&tmu0_device,
 737	&tmu1_device,
 738};
 739
 740void __init plat_early_device_setup(void)
 741{
 742	early_platform_add_devices(sh7757_early_devices,
 743				   ARRAY_SIZE(sh7757_early_devices));
 744}
 745
 746enum {
 747	UNUSED = 0,
 748
 749	/* interrupt sources */
 750
 751	IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 752	IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 753	IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 754	IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
 755
 756	IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 757	IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 758	IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 759	IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
 760	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 761
 762	SDHI, DVC,
 763	IRQ8, IRQ9, IRQ11, IRQ10, IRQ12, IRQ13, IRQ14, IRQ15,
 764	TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
 765	HUDI,
 766	ARC4,
 767	DMAC0_5, DMAC6_7, DMAC8_11,
 768	SCIF0, SCIF1, SCIF2, SCIF3, SCIF4,
 769	USB0, USB1,
 770	JMC,
 771	SPI0, SPI1,
 772	TMR01, TMR23, TMR45,
 773	FRT,
 774	LPC, LPC5, LPC6, LPC7, LPC8,
 775	PECI0, PECI1, PECI2, PECI3, PECI4, PECI5,
 776	ETHERC,
 777	ADC0, ADC1,
 778	SIM,
 779	IIC0_0, IIC0_1, IIC0_2, IIC0_3,
 780	IIC1_0, IIC1_1, IIC1_2, IIC1_3,
 781	IIC2_0, IIC2_1, IIC2_2, IIC2_3,
 782	IIC3_0, IIC3_1, IIC3_2, IIC3_3,
 783	IIC4_0, IIC4_1, IIC4_2, IIC4_3,
 784	IIC5_0, IIC5_1, IIC5_2, IIC5_3,
 785	IIC6_0, IIC6_1, IIC6_2, IIC6_3,
 786	IIC7_0, IIC7_1, IIC7_2, IIC7_3,
 787	IIC8_0, IIC8_1, IIC8_2, IIC8_3,
 788	IIC9_0, IIC9_1, IIC9_2, IIC9_3,
 789	ONFICTL,
 790	MMC1, MMC2,
 791	ECCU,
 792	PCIC,
 793	G200,
 794	RSPI,
 795	SGPIO,
 796	DMINT12, DMINT13, DMINT14, DMINT15, DMINT16, DMINT17, DMINT18, DMINT19,
 797	DMINT20, DMINT21, DMINT22, DMINT23,
 798	DDRECC,
 799	TSIP,
 800	PCIE_BRIDGE,
 801	WDT0B, WDT1B, WDT2B, WDT3B, WDT4B, WDT5B, WDT6B, WDT7B, WDT8B,
 802	GETHER0, GETHER1, GETHER2,
 803	PBIA, PBIB, PBIC,
 804	DMAE2, DMAE3,
 805	SERMUX2, SERMUX3,
 806
 807	/* interrupt groups */
 808
 809	TMU012, TMU345,
 810};
 811
 812static struct intc_vect vectors[] __initdata = {
 813	INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0),
 814	INTC_VECT(SDHI, 0x4c0),
 815	INTC_VECT(DVC, 0x4e0),
 816	INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520),
 817	INTC_VECT(IRQ10, 0x540),
 818	INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
 819	INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
 820	INTC_VECT(HUDI, 0x600),
 821	INTC_VECT(ARC4, 0x620),
 822	INTC_VECT(DMAC0_5, 0x640), INTC_VECT(DMAC0_5, 0x660),
 823	INTC_VECT(DMAC0_5, 0x680), INTC_VECT(DMAC0_5, 0x6a0),
 824	INTC_VECT(DMAC0_5, 0x6c0),
 825	INTC_VECT(IRQ11, 0x6e0),
 826	INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720),
 827	INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760),
 828	INTC_VECT(DMAC0_5, 0x780), INTC_VECT(DMAC0_5, 0x7a0),
 829	INTC_VECT(DMAC6_7, 0x7c0), INTC_VECT(DMAC6_7, 0x7e0),
 830	INTC_VECT(USB0, 0x840),
 831	INTC_VECT(IRQ12, 0x880),
 832	INTC_VECT(JMC, 0x8a0),
 833	INTC_VECT(SPI1, 0x8c0),
 834	INTC_VECT(IRQ13, 0x8e0), INTC_VECT(IRQ14, 0x900),
 835	INTC_VECT(USB1, 0x920),
 836	INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20),
 837	INTC_VECT(TMR45, 0xa40),
 838	INTC_VECT(FRT, 0xa80),
 839	INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0),
 840	INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00),
 841	INTC_VECT(LPC, 0xb20),
 842	INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60),
 843	INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0),
 844	INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0),
 845	INTC_VECT(PECI0, 0xc00), INTC_VECT(PECI1, 0xc20),
 846	INTC_VECT(PECI2, 0xc40),
 847	INTC_VECT(IRQ15, 0xc60),
 848	INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0),
 849	INTC_VECT(SPI0, 0xcc0),
 850	INTC_VECT(ADC1, 0xce0),
 851	INTC_VECT(DMAC8_11, 0xd00), INTC_VECT(DMAC8_11, 0xd20),
 852	INTC_VECT(DMAC8_11, 0xd40), INTC_VECT(DMAC8_11, 0xd60),
 853	INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
 854	INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
 855	INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 856	INTC_VECT(TMU5, 0xe40),
 857	INTC_VECT(ADC0, 0xe60),
 858	INTC_VECT(SCIF4, 0xf00), INTC_VECT(SCIF4, 0xf20),
 859	INTC_VECT(SCIF4, 0xf40), INTC_VECT(SCIF4, 0xf60),
 860	INTC_VECT(IIC0_0, 0x1400), INTC_VECT(IIC0_1, 0x1420),
 861	INTC_VECT(IIC0_2, 0x1440), INTC_VECT(IIC0_3, 0x1460),
 862	INTC_VECT(IIC1_0, 0x1480), INTC_VECT(IIC1_1, 0x14e0),
 863	INTC_VECT(IIC1_2, 0x1500), INTC_VECT(IIC1_3, 0x1520),
 864	INTC_VECT(IIC2_0, 0x1540), INTC_VECT(IIC2_1, 0x1560),
 865	INTC_VECT(IIC2_2, 0x1580), INTC_VECT(IIC2_3, 0x1600),
 866	INTC_VECT(IIC3_0, 0x1620), INTC_VECT(IIC3_1, 0x1640),
 867	INTC_VECT(IIC3_2, 0x16e0), INTC_VECT(IIC3_3, 0x1700),
 868	INTC_VECT(IIC4_0, 0x17c0), INTC_VECT(IIC4_1, 0x1800),
 869	INTC_VECT(IIC4_2, 0x1820), INTC_VECT(IIC4_3, 0x1840),
 870	INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880),
 871	INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0),
 872	INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900),
 873	INTC_VECT(IIC6_2, 0x1920),
 874	INTC_VECT(ONFICTL, 0x1960),
 875	INTC_VECT(IIC6_3, 0x1980),
 876	INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00),
 877	INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40),
 878	INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80),
 879	INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40),
 880	INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80),
 881	INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20),
 882	INTC_VECT(MMC1, 0x1c60), INTC_VECT(MMC2, 0x1c80),
 883	INTC_VECT(ECCU, 0x1cc0),
 884	INTC_VECT(PCIC, 0x1ce0),
 885	INTC_VECT(G200, 0x1d00),
 886	INTC_VECT(RSPI, 0x1d80), INTC_VECT(RSPI, 0x1da0),
 887	INTC_VECT(RSPI, 0x1dc0), INTC_VECT(RSPI, 0x1de0),
 888	INTC_VECT(PECI3, 0x1ec0), INTC_VECT(PECI4, 0x1ee0),
 889	INTC_VECT(PECI5, 0x1f00),
 890	INTC_VECT(SGPIO, 0x1f80), INTC_VECT(SGPIO, 0x1fa0),
 891	INTC_VECT(SGPIO, 0x1fc0),
 892	INTC_VECT(DMINT12, 0x2400), INTC_VECT(DMINT13, 0x2420),
 893	INTC_VECT(DMINT14, 0x2440), INTC_VECT(DMINT15, 0x2460),
 894	INTC_VECT(DMINT16, 0x2480), INTC_VECT(DMINT17, 0x24e0),
 895	INTC_VECT(DMINT18, 0x2500), INTC_VECT(DMINT19, 0x2520),
 896	INTC_VECT(DMINT20, 0x2540), INTC_VECT(DMINT21, 0x2560),
 897	INTC_VECT(DMINT22, 0x2580), INTC_VECT(DMINT23, 0x2600),
 898	INTC_VECT(DDRECC, 0x2620),
 899	INTC_VECT(TSIP, 0x2640),
 900	INTC_VECT(PCIE_BRIDGE, 0x27c0),
 901	INTC_VECT(WDT0B, 0x2800), INTC_VECT(WDT1B, 0x2820),
 902	INTC_VECT(WDT2B, 0x2840), INTC_VECT(WDT3B, 0x2860),
 903	INTC_VECT(WDT4B, 0x2880), INTC_VECT(WDT5B, 0x28a0),
 904	INTC_VECT(WDT6B, 0x28c0), INTC_VECT(WDT7B, 0x28e0),
 905	INTC_VECT(WDT8B, 0x2900),
 906	INTC_VECT(GETHER0, 0x2960), INTC_VECT(GETHER1, 0x2980),
 907	INTC_VECT(GETHER2, 0x29a0),
 908	INTC_VECT(PBIA, 0x2a00), INTC_VECT(PBIB, 0x2a20),
 909	INTC_VECT(PBIC, 0x2a40),
 910	INTC_VECT(DMAE2, 0x2a60), INTC_VECT(DMAE3, 0x2a80),
 911	INTC_VECT(SERMUX2, 0x2aa0), INTC_VECT(SERMUX3, 0x2b40),
 912	INTC_VECT(LPC5, 0x2b60), INTC_VECT(LPC6, 0x2b80),
 913	INTC_VECT(LPC7, 0x2c00), INTC_VECT(LPC8, 0x2c20),
 914};
 915
 916static struct intc_group groups[] __initdata = {
 917	INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 918	INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 919};
 920
 921static struct intc_mask_reg mask_registers[] __initdata = {
 922	{ 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 923	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 924
 925	{ 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 926	  { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 927	    IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 928	    IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 929	    IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
 930	    IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 931	    IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 932	    IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 933	    IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
 934
 935	{ 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 936	  { 0, 0, 0, 0, 0, 0, 0, 0,
 937	    0, DMAC8_11, 0, PECI0, LPC, FRT, 0, TMR45,
 938	    TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0_5,
 939	    HUDI, 0, 0, SCIF3, SCIF2, SDHI, TMU345, TMU012
 940	     } },
 941
 942	{ 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
 943	  { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC,
 944	    IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1,
 945	    ADC1, 0, DMAC6_7, ADC0, SPI0, SIM, PECI2, PECI1,
 946	    ARC4, 0, SPI1, JMC, 0, 0, 0, DVC
 947	     } },
 948
 949	{ 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */
 950	  { IIC4_1, IIC4_2, IIC5_0, ONFICTL, 0, 0, SGPIO, 0,
 951	    0, G200, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3,
 952	    IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1,
 953	    IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, 0, IIC2_2
 954	     } },
 955
 956	{ 0xffd100d0, 0xffd100d4, 32, /* INT2MSKR3 / INT2MSKCR3 */
 957	  { MMC1, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, PECI5, MMC2,
 958	    IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2,
 959	    PCIC, 0, IIC4_0, 0, ECCU, RSPI, 0, IIC9_3,
 960	    IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1
 961	     } },
 962
 963	{ 0xffd20038, 0xffd2003c, 32, /* INT2MSKR4 / INT2MSKCR4 */
 964	  { WDT0B, WDT1B, WDT3B, GETHER0, 0, 0, 0, 0,
 965	    0, 0, 0, LPC7, SERMUX2, DMAE3, DMAE2, PBIC,
 966	    PBIB, PBIA, GETHER1, DMINT12, DMINT13, DMINT14, DMINT15, TSIP,
 967	    DMINT23, 0, DMINT21, LPC6, 0, DMINT16, 0, DMINT22
 968	     } },
 969
 970	{ 0xffd200d0, 0xffd200d4, 32, /* INT2MSKR5 / INT2MSKCR5 */
 971	  { 0, WDT8B, WDT7B, WDT4B, 0, DMINT20, 0, 0,
 972	    DMINT19, DMINT18, LPC5, SERMUX3, WDT2B, GETHER2, 0, 0,
 973	    0, 0, PCIE_BRIDGE, 0, 0, 0, 0, LPC8,
 974	    DDRECC, 0, WDT6B, WDT5B, 0, 0, 0, DMINT17
 975	     } },
 976};
 977
 978#define INTPRI		0xffd00010
 979#define INT2PRI0	0xffd40000
 980#define INT2PRI1	0xffd40004
 981#define INT2PRI2	0xffd40008
 982#define INT2PRI3	0xffd4000c
 983#define INT2PRI4	0xffd40010
 984#define INT2PRI5	0xffd40014
 985#define INT2PRI6	0xffd40018
 986#define INT2PRI7	0xffd4001c
 987#define INT2PRI8	0xffd400a0
 988#define INT2PRI9	0xffd400a4
 989#define INT2PRI10	0xffd400a8
 990#define INT2PRI11	0xffd400ac
 991#define INT2PRI12	0xffd400b0
 992#define INT2PRI13	0xffd400b4
 993#define INT2PRI14	0xffd400b8
 994#define INT2PRI15	0xffd400bc
 995#define INT2PRI16	0xffd10000
 996#define INT2PRI17	0xffd10004
 997#define INT2PRI18	0xffd10008
 998#define INT2PRI19	0xffd1000c
 999#define INT2PRI20	0xffd10010
1000#define INT2PRI21	0xffd10014
1001#define INT2PRI22	0xffd10018
1002#define INT2PRI23	0xffd1001c
1003#define INT2PRI24	0xffd100a0
1004#define INT2PRI25	0xffd100a4
1005#define INT2PRI26	0xffd100a8
1006#define INT2PRI27	0xffd100ac
1007#define INT2PRI28	0xffd100b0
1008#define INT2PRI29	0xffd100b4
1009#define INT2PRI30	0xffd100b8
1010#define INT2PRI31	0xffd100bc
1011#define INT2PRI32	0xffd20000
1012#define INT2PRI33	0xffd20004
1013#define INT2PRI34	0xffd20008
1014#define INT2PRI35	0xffd2000c
1015#define INT2PRI36	0xffd20010
1016#define INT2PRI37	0xffd20014
1017#define INT2PRI38	0xffd20018
1018#define INT2PRI39	0xffd2001c
1019#define INT2PRI40	0xffd200a0
1020#define INT2PRI41	0xffd200a4
1021#define INT2PRI42	0xffd200a8
1022#define INT2PRI43	0xffd200ac
1023#define INT2PRI44	0xffd200b0
1024#define INT2PRI45	0xffd200b4
1025#define INT2PRI46	0xffd200b8
1026#define INT2PRI47	0xffd200bc
1027
1028static struct intc_prio_reg prio_registers[] __initdata = {
1029	{ INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3,
1030			      IRQ4, IRQ5, IRQ6, IRQ7 } },
1031
1032	{ INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } },
1033	{ INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } },
1034	{ INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, 0, IRQ8 } },
1035	{ INT2PRI3, 0, 32, 8, { HUDI, DMAC0_5, ADC0, IRQ9 } },
1036	{ INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } },
1037	{ INT2PRI5, 0, 32, 8, { TMR45, 0, FRT, LPC } },
1038	{ INT2PRI6, 0, 32, 8, { PECI0, ETHERC, DMAC8_11, 0 } },
1039	{ INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } },
1040	{ INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } },
1041	{ INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } },
1042	{ INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2, PECI1 } },
1043	{ INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC6_7, IRQ14 } },
1044	{ INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } },
1045	{ INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } },
1046
1047	{ INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } },
1048	{ INT2PRI17, 0, 32, 8, { 0, 0, 0, IIC1_0 } },
1049	{ INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } },
1050	{ INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } },
1051	{ INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } },
1052	{ INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } },
1053	{ INT2PRI22, 0, 32, 8, { IIC9_2, MMC2, G200, 0 } },
1054	{ INT2PRI23, 0, 32, 8, { PECI5, SGPIO, IIC3_2, IIC5_1 } },
1055	{ INT2PRI24, 0, 32, 8, { PECI4, PECI3, 0, IIC1_1 } },
1056	{ INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } },
1057	{ INT2PRI26, 0, 32, 8, { ECCU, RSPI, 0, IIC9_3 } },
1058	{ INT2PRI27, 0, 32, 8, { PCIC, IIC6_0, IIC4_0, IIC6_1 } },
1059	{ INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, MMC1, IIC6_2 } },
1060	{ INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } },
1061	{ INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, ONFICTL } },
1062	{ INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } },
1063	{ INT2PRI32, 0, 32, 8, { DMINT22, 0, 0, 0 } },
1064	{ INT2PRI33, 0, 32, 8, { 0, 0, 0, DMINT16 } },
1065	{ INT2PRI34, 0, 32, 8, { 0, LPC6, DMINT21, DMINT18 } },
1066	{ INT2PRI35, 0, 32, 8, { DMINT23, TSIP, 0, DMINT19 } },
1067	{ INT2PRI36, 0, 32, 8, { DMINT20, GETHER1, PBIA, PBIB } },
1068	{ INT2PRI37, 0, 32, 8, { PBIC, DMAE2, DMAE3, SERMUX2 } },
1069	{ INT2PRI38, 0, 32, 8, { LPC7, 0, 0, 0 } },
1070	{ INT2PRI39, 0, 32, 8, { 0, 0, 0, WDT4B } },
1071	{ INT2PRI40, 0, 32, 8, { 0, 0, 0, DMINT17 } },
1072	{ INT2PRI41, 0, 32, 8, { DDRECC, 0, WDT6B, WDT5B } },
1073	{ INT2PRI42, 0, 32, 8, { 0, 0, 0, LPC8 } },
1074	{ INT2PRI43, 0, 32, 8, { 0, WDT7B, PCIE_BRIDGE, WDT8B } },
1075	{ INT2PRI44, 0, 32, 8, { WDT2B, GETHER2, 0, 0 } },
1076	{ INT2PRI45, 0, 32, 8, { 0, 0, LPC5, SERMUX3 } },
1077	{ INT2PRI46, 0, 32, 8, { WDT0B, WDT1B, WDT3B, GETHER0 } },
1078	{ INT2PRI47, 0, 32, 8, { DMINT12, DMINT13, DMINT14, DMINT15 } },
1079};
1080
1081static struct intc_sense_reg sense_registers_irq8to15[] __initdata = {
1082	{ 0xffd100f8, 32, 2, /* ICR2 */   { IRQ15, IRQ14, IRQ13, IRQ12,
1083					    IRQ11, IRQ10, IRQ9, IRQ8 } },
1084};
1085
1086static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups,
1087			 mask_registers, prio_registers,
1088			 sense_registers_irq8to15);
1089
1090/* Support for external interrupt pins in IRQ mode */
1091static struct intc_vect vectors_irq0123[] __initdata = {
1092	INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
1093	INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
1094};
1095
1096static struct intc_vect vectors_irq4567[] __initdata = {
1097	INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
1098	INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
1099};
1100
1101static struct intc_sense_reg sense_registers[] __initdata = {
1102	{ 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
1103					    IRQ4, IRQ5, IRQ6, IRQ7 } },
1104};
1105
1106static struct intc_mask_reg ack_registers[] __initdata = {
1107	{ 0xffd00024, 0, 32, /* INTREQ */
1108	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1109};
1110
1111static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7757-irq0123",
1112			     vectors_irq0123, NULL, mask_registers,
1113			     prio_registers, sense_registers, ack_registers);
1114
1115static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7757-irq4567",
1116			     vectors_irq4567, NULL, mask_registers,
1117			     prio_registers, sense_registers, ack_registers);
1118
1119/* External interrupt pins in IRL mode */
1120static struct intc_vect vectors_irl0123[] __initdata = {
1121	INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
1122	INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
1123	INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
1124	INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
1125	INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
1126	INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
1127	INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
1128	INTC_VECT(IRL0_HHHL, 0x3c0),
1129};
1130
1131static struct intc_vect vectors_irl4567[] __initdata = {
1132	INTC_VECT(IRL4_LLLL, 0x200), INTC_VECT(IRL4_LLLH, 0x220),
1133	INTC_VECT(IRL4_LLHL, 0x240), INTC_VECT(IRL4_LLHH, 0x260),
1134	INTC_VECT(IRL4_LHLL, 0x280), INTC_VECT(IRL4_LHLH, 0x2a0),
1135	INTC_VECT(IRL4_LHHL, 0x2c0), INTC_VECT(IRL4_LHHH, 0x2e0),
1136	INTC_VECT(IRL4_HLLL, 0x300), INTC_VECT(IRL4_HLLH, 0x320),
1137	INTC_VECT(IRL4_HLHL, 0x340), INTC_VECT(IRL4_HLHH, 0x360),
1138	INTC_VECT(IRL4_HHLL, 0x380), INTC_VECT(IRL4_HHLH, 0x3a0),
1139	INTC_VECT(IRL4_HHHL, 0x3c0),
1140};
1141
1142static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123,
1143			 NULL, mask_registers, NULL, NULL);
1144
1145static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567,
1146			 NULL, mask_registers, NULL, NULL);
1147
1148#define INTC_ICR0	0xffd00000
1149#define INTC_INTMSK0	0xffd00044
1150#define INTC_INTMSK1	0xffd00048
1151#define INTC_INTMSK2	0xffd40080
1152#define INTC_INTMSKCLR1	0xffd00068
1153#define INTC_INTMSKCLR2	0xffd40084
1154
1155void __init plat_irq_setup(void)
1156{
1157	/* disable IRQ3-0 + IRQ7-4 */
1158	__raw_writel(0xff000000, INTC_INTMSK0);
1159
1160	/* disable IRL3-0 + IRL7-4 */
1161	__raw_writel(0xc0000000, INTC_INTMSK1);
1162	__raw_writel(0xfffefffe, INTC_INTMSK2);
1163
1164	/* select IRL mode for IRL3-0 + IRL7-4 */
1165	__raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
1166
1167	/* disable holding function, ie enable "SH-4 Mode" */
1168	__raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
1169
1170	register_intc_controller(&intc_desc);
1171}
1172
1173void __init plat_irq_setup_pins(int mode)
1174{
1175	switch (mode) {
1176	case IRQ_MODE_IRQ7654:
1177		/* select IRQ mode for IRL7-4 */
1178		__raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
1179		register_intc_controller(&intc_desc_irq4567);
1180		break;
1181	case IRQ_MODE_IRQ3210:
1182		/* select IRQ mode for IRL3-0 */
1183		__raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
1184		register_intc_controller(&intc_desc_irq0123);
1185		break;
1186	case IRQ_MODE_IRL7654:
1187		/* enable IRL7-4 but don't provide any masking */
1188		__raw_writel(0x40000000, INTC_INTMSKCLR1);
1189		__raw_writel(0x0000fffe, INTC_INTMSKCLR2);
1190		break;
1191	case IRQ_MODE_IRL3210:
1192		/* enable IRL0-3 but don't provide any masking */
1193		__raw_writel(0x80000000, INTC_INTMSKCLR1);
1194		__raw_writel(0xfffe0000, INTC_INTMSKCLR2);
1195		break;
1196	case IRQ_MODE_IRL7654_MASK:
1197		/* enable IRL7-4 and mask using cpu intc controller */
1198		__raw_writel(0x40000000, INTC_INTMSKCLR1);
1199		register_intc_controller(&intc_desc_irl4567);
1200		break;
1201	case IRQ_MODE_IRL3210_MASK:
1202		/* enable IRL0-3 and mask using cpu intc controller */
1203		__raw_writel(0x80000000, INTC_INTMSKCLR1);
1204		register_intc_controller(&intc_desc_irl0123);
1205		break;
1206	default:
1207		BUG();
1208	}
1209}
1210
1211void __init plat_mem_setup(void)
1212{
1213}