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/arch/s390/kernel/reipl64.S

https://bitbucket.org/ndreys/linux-sunxi
Assembly | 110 lines | 105 code | 5 blank | 0 comment | 2 complexity | 710c94ebe86670c09d2bed8e22039888 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1/*
  2 *    Copyright IBM Corp 2000,2009
  3 *    Author(s): Holger Smolinski <Holger.Smolinski@de.ibm.com>,
  4 *		 Denis Joseph Barrow,
  5 */
  6
  7#include <asm/asm-offsets.h>
  8
  9#
 10# do_reipl_asm
 11# Parameter: r2 = schid of reipl device
 12#
 13
 14		.globl	do_reipl_asm
 15do_reipl_asm:	basr	%r13,0
 16.Lpg0:		lpswe	.Lnewpsw-.Lpg0(%r13)
 17.Lpg1:		# do store status of all registers
 18
 19		stg	%r1,.Lregsave-.Lpg0(%r13)
 20		lghi	%r1,0x1000
 21		stmg	%r0,%r15,__LC_GPREGS_SAVE_AREA-0x1000(%r1)
 22		lg	%r0,.Lregsave-.Lpg0(%r13)
 23		stg	%r0,__LC_GPREGS_SAVE_AREA-0x1000+8(%r1)
 24		stctg	%c0,%c15,__LC_CREGS_SAVE_AREA-0x1000(%r1)
 25		stam	%a0,%a15,__LC_AREGS_SAVE_AREA-0x1000(%r1)
 26		lg	%r10,.Ldump_pfx-.Lpg0(%r13)
 27		mvc	__LC_PREFIX_SAVE_AREA-0x1000(4,%r1),0(%r10)
 28		stfpc	__LC_FP_CREG_SAVE_AREA-0x1000(%r1)
 29		stckc	.Lclkcmp-.Lpg0(%r13)
 30		mvc	__LC_CLOCK_COMP_SAVE_AREA-0x1000(7,%r1),.Lclkcmp-.Lpg0(%r13)
 31		stpt	__LC_CPU_TIMER_SAVE_AREA-0x1000(%r1)
 32		stg	%r13, __LC_PSW_SAVE_AREA-0x1000+8(%r1)
 33
 34		lctlg	%c6,%c6,.Lall-.Lpg0(%r13)
 35		lgr	%r1,%r2
 36		mvc	__LC_PGM_NEW_PSW(16),.Lpcnew-.Lpg0(%r13)
 37		stsch	.Lschib-.Lpg0(%r13)
 38		oi	.Lschib+5-.Lpg0(%r13),0x84
 39.Lecs:  	xi	.Lschib+27-.Lpg0(%r13),0x01
 40		msch	.Lschib-.Lpg0(%r13)
 41		lghi	%r0,5
 42.Lssch:		ssch	.Liplorb-.Lpg0(%r13)
 43		jz	.L001
 44		brct	%r0,.Lssch
 45		bas	%r14,.Ldisab-.Lpg0(%r13)
 46.L001:		mvc	__LC_IO_NEW_PSW(16),.Lionew-.Lpg0(%r13)
 47.Ltpi:		lpswe	.Lwaitpsw-.Lpg0(%r13)
 48.Lcont:		c	%r1,__LC_SUBCHANNEL_ID
 49		jnz	.Ltpi
 50		clc	__LC_IO_INT_PARM(4),.Liplorb-.Lpg0(%r13)
 51		jnz	.Ltpi
 52		tsch	.Liplirb-.Lpg0(%r13)
 53		tm	.Liplirb+9-.Lpg0(%r13),0xbf
 54		jz	.L002
 55		bas	%r14,.Ldisab-.Lpg0(%r13)
 56.L002:		tm	.Liplirb+8-.Lpg0(%r13),0xf3
 57		jz	.L003
 58		bas	%r14,.Ldisab-.Lpg0(%r13)
 59.L003:		st	%r1,__LC_SUBCHANNEL_ID
 60		lhi	%r1,0		 # mode 0 = esa
 61		slr	%r0,%r0 	 # set cpuid to zero
 62		sigp	%r1,%r0,0x12	 # switch to esa mode
 63		lpsw	0
 64.Ldisab:	sll	%r14,1
 65		srl	%r14,1		 # need to kill hi bit to avoid specification exceptions.
 66		st	%r14,.Ldispsw+12-.Lpg0(%r13)
 67		lpswe	.Ldispsw-.Lpg0(%r13)
 68		.align	8
 69.Lclkcmp:	.quad	0x0000000000000000
 70.Lall:		.quad	0x00000000ff000000
 71.Ldump_pfx:	.quad	dump_prefix_page
 72.Lregsave:	.quad	0x0000000000000000
 73		.align	16
 74/*
 75 * These addresses have to be 31 bit otherwise
 76 * the sigp will throw a specifcation exception
 77 * when switching to ESA mode as bit 31 be set
 78 * in the ESA psw.
 79 * Bit 31 of the addresses has to be 0 for the
 80 * 31bit lpswe instruction a fact they appear to have
 81 * omitted from the pop.
 82 */
 83.Lnewpsw:	.quad	0x0000000080000000
 84		.quad	.Lpg1
 85.Lpcnew:	.quad	0x0000000080000000
 86		.quad	.Lecs
 87.Lionew:	.quad	0x0000000080000000
 88		.quad	.Lcont
 89.Lwaitpsw:	.quad	0x0202000080000000
 90		.quad	.Ltpi
 91.Ldispsw:	.quad	0x0002000080000000
 92		.quad	0x0000000000000000
 93.Liplccws:	.long	0x02000000,0x60000018
 94		.long	0x08000008,0x20000001
 95.Liplorb:	.long	0x0049504c,0x0040ff80
 96		.long	0x00000000+.Liplccws
 97.Lschib:	.long	0x00000000,0x00000000
 98		.long	0x00000000,0x00000000
 99		.long	0x00000000,0x00000000
100		.long	0x00000000,0x00000000
101		.long	0x00000000,0x00000000
102		.long	0x00000000,0x00000000
103.Liplirb:	.long	0x00000000,0x00000000
104		.long	0x00000000,0x00000000
105		.long	0x00000000,0x00000000
106		.long	0x00000000,0x00000000
107		.long	0x00000000,0x00000000
108		.long	0x00000000,0x00000000
109		.long	0x00000000,0x00000000
110		.long	0x00000000,0x00000000