/share/man/man4/hpet.4

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 25.\" $FreeBSD$
 26.\"
 27.Dd September 14, 2010
 28.Dt HPET 4
 29.Os
 30.Sh NAME
 31.Nm hpet
 32.Nd High Precision Event Timer driver
 33.Sh SYNOPSIS
 34To compile this driver into the kernel,
 35place the following lines in your
 36kernel configuration file:
 37.Bd -ragged -offset indent
 38.Cd "device acpi"
 39.Ed
 40.Pp
 41The following tunables are settable from the
 42.Xr loader 8 :
 43.Bl -ohang
 44.It Va hint.hpet. Ns Ar X Ns Va .allowed_irqs
 45is a 32bit mask. Each set bit allows driver to use respective IRQ,
 46if BIOS also set respective capability bit in comparator's configuration
 47register.
 48Default value is 0xffff0000, except some known broken hardware.
 49.It Va hint.hpet. Ns Ar X Ns Va .clock
 50controls event timers functionality support. Setting to 0, disables it.
 51Default value is 1.
 52.It Va hint.hpet. Ns Ar X Ns Va .legacy_route
 53controls "LegacyReplacement Route" mode. If enabled, HPET will steal IRQ0 of
 54i8254 timer and IRQ8 of RTC. Before using it, make sure that respective
 55drivers are not using interrupts, by setting also:
 56.Bd -literal
 57hint.attimer.0.clock=0
 58hint.atrtc.0.clock=0
 59.Ed
 60Default value is 0.
 61.It Va hint.hpet. Ns Ar X Ns Va .per_cpu
 62controls how much per-CPU event timers should driver attempt to register.
 63This functionality requires every comparator in a group to have own unshared
 64IRQ, so it depends on hardware capabilities and interrupts configuration.
 65Default value is 1.
 66.El
 67.Sh DESCRIPTION
 68This driver uses High Precision Event Timer hardware (part of the chipset,
 69usually enumerated via ACPI) to supply kernel with one time counter and
 70several (usually from 3 to 8) event timers.
 71This hardware includes single main counter with known increment frequency
 72(10MHz or more), and several programmable comparators (optionally with
 73automatic reload feature).
 74When value of the main counter matches current value of any comparator,
 75interrupt can be generated.
 76Depending on hardware capabilities and configuration, interrupt can be
 77delivered as regular I/O APIC interrupt (ISA or PCI) in range from 0 to 31,
 78or as Front Side Bus interrupt, alike to PCI MSI interrupts, or in so called
 79"LegacyReplacement Route" HPET can steal IRQ0 of i8254 and IRQ8 of the RTC.
 80Interrupt can be either edge- or level-triggered. In last case they could be
 81safely shared with PCI IRQs.
 82Driver prefers to use FSB interrupts, if supported, to avoid sharing.
 83If it is not possible, it uses single sharable IRQ from PCI range.
 84Other modes (LegacyReplacement and ISA IRQs) require special care to setup,
 85but could be configured manually via device hints.
 86.Pp
 87Event timers provided by the driver support both one-shot an periodic modes
 88and irrelevant to CPU power states.
 89.Pp
 90Depending on hardware capabilities and configuration, driver can expose each
 91comparator as separate event timer or group them into one or several per-CPU
 92event timers. In last case interrupt of every of those comparators within
 93group is bound to specific CPU core. This is possible only when each
 94of these comparators has own unsharable IRQ.
 95.Sh SEE ALSO
 96.Xr acpi 4 ,
 97.Xr apic 4 ,
 98.Xr atrtc 4 ,
 99.Xr attimer 4 ,
100.Xr eventtimers 4 ,
101.Xr timecounters 4
102.Sh HISTORY
103The
104.Nm
105driver first appeared in
106.Fx 6.3 .
107Support for event timers was added in
108.Fx 9.0 .