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/share/man/man4/iicbus.4

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  1.\" Copyright (c) 1998, Nicolas Souchu
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 25.\" $FreeBSD$
 26.\"
 27.Dd August 6, 1998
 28.Dt IICBUS 4
 29.Os
 30.Sh NAME
 31.Nm iicbus
 32.Nd I2C bus system
 33.Sh SYNOPSIS
 34.Cd "device iicbus"
 35.Cd "device iicbb"
 36.Pp
 37.Cd "device iic"
 38.Cd "device ic"
 39.Cd "device iicsmb"
 40.Sh DESCRIPTION
 41The
 42.Em iicbus
 43system provides a uniform, modular and architecture-independent
 44system for the implementation of drivers to control various I2C devices
 45and to utilize different I2C controllers.
 46.Sh I2C
 47I2C is an acronym for Inter Integrated Circuit bus.
 48The I2C bus was developed
 49in the early 1980's by Philips semiconductors.
 50Its purpose was to provide an
 51easy way to connect a CPU to peripheral chips in a TV-set.
 52.Pp
 53The BUS physically consists of 2 active wires and a ground connection.
 54The active wires, SDA and SCL, are both bidirectional.
 55Where SDA is the
 56Serial DAta line and SCL is the Serial CLock line.
 57.Pp
 58Every component hooked up to the bus has its own unique address whether it
 59is a CPU, LCD driver, memory, or complex function chip.
 60Each of these chips
 61can act as a receiver and/or transmitter depending on its functionality.
 62Obviously an LCD driver is only a receiver, while a memory or I/O chip can
 63both be transmitter and receiver.
 64Furthermore there may be one or
 65more BUS MASTERs.
 66.Pp
 67The BUS MASTER is the chip issuing the commands on the BUS.
 68In the I2C protocol
 69specification it is stated that the IC that initiates a data transfer on the
 70bus is considered the BUS MASTER.
 71At that time all the others are regarded to
 72as the BUS SLAVEs.
 73As mentioned before, the IC bus is a Multi-MASTER BUS.
 74This means that more than one IC capable of initiating data transfer can be
 75connected to it.
 76.Sh DEVICES
 77Some I2C device drivers are available:
 78.Pp
 79.Bl -column "Device drivers" -compact
 80.It Em Devices Ta Em Description
 81.It Sy iic Ta "general i/o operation"
 82.It Sy ic Ta "network IP interface"
 83.It Sy iicsmb Ta "I2C to SMB software bridge"
 84.El
 85.Sh INTERFACES
 86The I2C protocol may be implemented by hardware or software.
 87Software
 88interfaces rely on very simple hardware, usually two lines
 89twiddled by 2 registers.
 90Hardware interfaces are more intelligent and receive
 918-bit characters they write to the bus according to the I2C protocol.
 92.Pp
 93I2C interfaces may act on the bus as slave devices, allowing spontaneous
 94bidirectional communications, thanks to the multi-master capabilities of the
 95I2C protocol.
 96.Pp
 97Some I2C interfaces are available:
 98.Pp
 99.Bl -column "Interface drivers" -compact
100.It Em Interface Ta Em Description
101.It Sy pcf Ta "Philips PCF8584 master/slave interface"
102.It Sy iicbb Ta "generic bit-banging master-only driver"
103.It Sy lpbb Ta "parallel port specific bit-banging interface"
104.It Sy bktr Ta "Brooktree848 video chipset, hardware and software master-only interface"
105.El
106.Sh SEE ALSO
107.Xr iicbb 4 ,
108.Xr lpbb 4 ,
109.Xr pcf 4
110.Sh HISTORY
111The
112.Nm
113manual page first appeared in
114.Fx 3.0 .
115.Sh AUTHORS
116This
117manual page was written by
118.An Nicolas Souchu .