/share/man/man4/man4.i386/CPU_ELAN.4

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 25.\" $FreeBSD$
 26.\"
 27.Dd November 23, 2003
 28.Dt CPU_ELAN 4 i386
 29.Os
 30.Sh NAME
 31.Nm CPU_ELAN
 32.Nd AMD Elan 520 CPU support
 33.Sh SYNOPSIS
 34.Cd "options CPU_ELAN"
 35.Cd "options CPU_ELAN_PPS"
 36.Cd "options CPU_ELAN_XTAL"
 37.Bl -item -compact
 38.It
 39.Va machdep.elan_gpio_config
 40.It
 41.Va machdep.elan_freq
 42.El
 43.Cd "options CPU_SOEKRIS"
 44.Sh DESCRIPTION
 45The
 46.Cd "options CPU_ELAN"
 47enables support for the AMD Elan 520 CPU.
 48.Pp
 49A device
 50.Pa /dev/elan-mmcr
 51exports the MMCR register bank to userland
 52using
 53.Xr mmap 2 .
 54.Pp
 55The
 56.Tn i8254
 57timer will be adjusted to the slightly unorthodox
 58frequency 1189161 Hz (32768 * 45 * 25 / 31) employed by the Elan.
 59.Pp
 60A timecounter named
 61.Dq Li ELAN
 62is implemented using the general purpose timer 2,
 63but it will not be usable unless HZ is configured at 150 or higher.
 64This timecounter is much better than the
 65.Dq Li i8254
 66timecounter and should be
 67used at all times.
 68.Pp
 69The
 70.Va machdep.elan_gpio_config
 71.Xr sysctl 8
 72variable
 73enables configuration of the GPIO pins of the CPU.
 74The string must be exactly 32 characters long.
 75A
 76.Ql -
 77means the GPIO is unavailable.
 78A
 79.Ql l
 80(lower-case ell) configures a
 81.Xr led 4
 82device (active low).
 83A
 84.Ql L
 85configures a
 86.Xr led 4
 87device (active high).
 88A
 89.Ql \&.
 90means no configuration for this GPIO.
 91These
 92.Xr led 4
 93devices will be named
 94.Pa /dev/led/gpio%d .
 95For meaning of
 96.Ql P ,
 97.Ql e
 98and
 99.Ql E ,
100see under
101.Cd "options CPU_ELAN_PPS" .
102.Pp
103The
104.Cd "options CPU_ELAN_XTAL"
105and the
106.Va machdep.elan_freq
107.Xr sysctl 8
108variable
109can be used to set the CPU clock crystal frequency in Hz.
110The default is 33333333 Hz.
111.Pp
112The
113.Cd "options CPU_ELAN_PPS"
114enables precision timestamping using the RFC2783 PPS-API via the
115.Pa /dev/elan-mmcr
116device.
117The resolution will be approximately 125 nsec
118and the precision \(+- 125 nsec.
119(For 125 nsec read
120.Dq "4 / CPU clock crystal frequency" . )
121.Pp
122The input signal must be connected to the TMR1IN pin and
123a GPIO pin.
124The GPIO pin must be configured with a
125.Ql P
126in
127.Va machdep.elan_gpio_config .
128.Pp
129In addition, one GPIO pin can be configured with either
130.Ql e
131(active low)
132or
133.Ql E
134(active high) to become a
135.Dq echo
136output of the input signal.
137Please notice that this signal is not suitable for calibration.
138.Pp
139If the
140.Cd "options CPU_SOEKRIS"
141is given, the support will additionally be tailored to the
142Soekris Engineering 45xx series of embedded computers.
143The
144.Dq error
145led will be configured (as
146.Pa /dev/led/error )
147and the GPIO pins which are not
148available will be disabled.
149.Sh SEE ALSO
150.Xr led 4 ,
151.Xr timecounters 4 ,
152.Xr sysctl 8
153.Sh HISTORY
154The
155.Nm
156code first appeared in
157.Fx 4.7 .
158.Sh AUTHORS
159.An "Poul-Henning Kamp" Aq phk@FreeBSD.org