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/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c

https://bitbucket.org/bradfa/linux
C | 3013 lines | 2348 code | 395 blank | 270 comment | 394 complexity | 9c2d31ac9c225293592f9ad25e230349 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0

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  1. /*******************************************************************************
    2. 

    3. 

  3.   Intel 10 Gigabit PCI Express Linux driver
    4. 

  4.   Copyright(c) 1999 - 2013 Intel Corporation.
    5. 

    6. 

  6.   This program is free software; you can redistribute it and/or modify it
    7. 

  7.   under the terms and conditions of the GNU General Public License,
    8. 

  8.   version 2, as published by the Free Software Foundation.
    9. 

    10. 

  10.   This program is distributed in the hope it will be useful, but WITHOUT
    11. 

  11.   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
    12. 

  12.   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
    13. 

  13.   more details.
    14. 

    15. 

  15.   You should have received a copy of the GNU General Public License along with
    16. 

  16.   this program; if not, write to the Free Software Foundation, Inc.,
    17. 

  17.   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
    18. 

    19. 

  19.   The full GNU General Public License is included in this distribution in
    20. 

  20.   the file called "COPYING".
    21. 

    22. 

  22.   Contact Information:
    23. 

  23.   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
    24. 

  24.   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
    25. 

    26. 

  26. *******************************************************************************/
    27. 

  27. 

  28. /* ethtool support for ixgbe */
    29. 

  29. 

  30. #include <linux/interrupt.h>
    31. 

  31. #include <linux/types.h>
    32. 

  32. #include <linux/module.h>
    33. 

  33. #include <linux/slab.h>
    34. 

  34. #include <linux/pci.h>
    35. 

  35. #include <linux/netdevice.h>
    36. 

  36. #include <linux/ethtool.h>
    37. 

  37. #include <linux/vmalloc.h>
    38. 

  38. #include <linux/highmem.h>
    39. 

  39. #include <linux/uaccess.h>
    40. 

  40. 

  41. #include "ixgbe.h"
    42. 

  42. #include "ixgbe_phy.h"
    43. 

  43. 

  44. 

  45. #define IXGBE_ALL_RAR_ENTRIES 16
    46. 

  46. 

  47. enum {NETDEV_STATS, IXGBE_STATS};
    48. 

  48. 

  49. struct ixgbe_stats {
    50. 

  50. 	char stat_string[ETH_GSTRING_LEN];
    51. 

  51. 	int type;
    52. 

  52. 	int sizeof_stat;
    53. 

  53. 	int stat_offset;
    54. 

  54. };
    55. 

  55. 

  56. #define IXGBE_STAT(m)		IXGBE_STATS, \
    57. 

  57. 				sizeof(((struct ixgbe_adapter *)0)->m), \
    58. 

  58. 				offsetof(struct ixgbe_adapter, m)
    59. 

  59. #define IXGBE_NETDEV_STAT(m)	NETDEV_STATS, \
    60. 

  60. 				sizeof(((struct rtnl_link_stats64 *)0)->m), \
    61. 

  61. 				offsetof(struct rtnl_link_stats64, m)
    62. 

  62. 

  63. static const struct ixgbe_stats ixgbe_gstrings_stats[] = {
    64. 

  64. 	{"rx_packets", IXGBE_NETDEV_STAT(rx_packets)},
    65. 

  65. 	{"tx_packets", IXGBE_NETDEV_STAT(tx_packets)},
    66. 

  66. 	{"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)},
    67. 

  67. 	{"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)},
    68. 

  68. 	{"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
    69. 

  69. 	{"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
    70. 

  70. 	{"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
    71. 

  71. 	{"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
    72. 

  72. 	{"lsc_int", IXGBE_STAT(lsc_int)},
    73. 

  73. 	{"tx_busy", IXGBE_STAT(tx_busy)},
    74. 

  74. 	{"non_eop_descs", IXGBE_STAT(non_eop_descs)},
    75. 

  75. 	{"rx_errors", IXGBE_NETDEV_STAT(rx_errors)},
    76. 

  76. 	{"tx_errors", IXGBE_NETDEV_STAT(tx_errors)},
    77. 

  77. 	{"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)},
    78. 

  78. 	{"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)},
    79. 

  79. 	{"multicast", IXGBE_NETDEV_STAT(multicast)},
    80. 

  80. 	{"broadcast", IXGBE_STAT(stats.bprc)},
    81. 

  81. 	{"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
    82. 

  82. 	{"collisions", IXGBE_NETDEV_STAT(collisions)},
    83. 

  83. 	{"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)},
    84. 

  84. 	{"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)},
    85. 

  85. 	{"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)},
    86. 

  86. 	{"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
    87. 

  87. 	{"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
    88. 

  88. 	{"fdir_match", IXGBE_STAT(stats.fdirmatch)},
    89. 

  89. 	{"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
    90. 

  90. 	{"fdir_overflow", IXGBE_STAT(fdir_overflow)},
    91. 

  91. 	{"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)},
    92. 

  92. 	{"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)},
    93. 

  93. 	{"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)},
    94. 

  94. 	{"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)},
    95. 

  95. 	{"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)},
    96. 

  96. 	{"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)},
    97. 

  97. 	{"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
    98. 

  98. 	{"tx_restart_queue", IXGBE_STAT(restart_queue)},
    99. 

  99. 	{"rx_long_length_errors", IXGBE_STAT(stats.roc)},
    100. 

  100. 	{"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
    101. 

  101. 	{"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
    102. 

  102. 	{"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
    103. 

  103. 	{"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
    104. 

  104. 	{"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
    105. 

  105. 	{"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
    106. 

  106. 	{"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
    107. 

  107. 	{"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
    108. 

  108. 	{"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
    109. 

  109. 	{"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)},
    110. 

  110. 	{"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)},
    111. 

  111. 	{"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)},
    112. 

  112. 	{"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)},
    113. 

  113. #ifdef IXGBE_FCOE
    114. 

  114. 	{"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
    115. 

  115. 	{"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
    116. 

  116. 	{"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
    117. 

  117. 	{"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
    118. 

  118. 	{"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)},
    119. 

  119. 	{"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)},
    120. 

  120. 	{"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
    121. 

  121. 	{"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
    122. 

  122. #endif /* IXGBE_FCOE */
    123. 

  123. };
    124. 

  124. 

  125. /* ixgbe allocates num_tx_queues and num_rx_queues symmetrically so
    126. 

  126.  * we set the num_rx_queues to evaluate to num_tx_queues. This is
    127. 

  127.  * used because we do not have a good way to get the max number of
    128. 

  128.  * rx queues with CONFIG_RPS disabled.
    129. 

  129.  */
    130. 

  130. #define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues
    131. 

  131. 

  132. #define IXGBE_QUEUE_STATS_LEN ( \
    133. 

  133. 	(netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \
    134. 

  134. 	(sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
    135. 

  135. #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
    136. 

  136. #define IXGBE_PB_STATS_LEN ( \
    137. 

  137. 			(sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
    138. 

  138. 			 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
    139. 

  139. 			 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
    140. 

  140. 			 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
    141. 

  141. 			/ sizeof(u64))
    142. 

  142. #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
    143. 

  143.                          IXGBE_PB_STATS_LEN + \
    144. 

  144.                          IXGBE_QUEUE_STATS_LEN)
    145. 

  145. 

  146. static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
    147. 

  147. 	"Register test  (offline)", "Eeprom test    (offline)",
    148. 

  148. 	"Interrupt test (offline)", "Loopback test  (offline)",
    149. 

  149. 	"Link test   (on/offline)"
    150. 

  150. };
    151. 

  151. #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
    152. 

  152. 

  153. static int ixgbe_get_settings(struct net_device *netdev,
    154. 

  154.                               struct ethtool_cmd *ecmd)
    155. 

  155. {
    156. 

  156. 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
    157. 

  157. 	struct ixgbe_hw *hw = &adapter->hw;
    158. 

  158. 	ixgbe_link_speed supported_link;
    159. 

  159. 	u32 link_speed = 0;
    160. 

  160. 	bool autoneg = false;
    161. 

  161. 	bool link_up;
    162. 

  162. 

  163. 	hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg);
    164. 

  164. 

  165. 	/* set the supported link speeds */
    166. 

  166. 	if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
    167. 

  167. 		ecmd->supported |= SUPPORTED_10000baseT_Full;
    168. 

  168. 	if (supported_link & IXGBE_LINK_SPEED_1GB_FULL)
    169. 

  169. 		ecmd->supported |= SUPPORTED_1000baseT_Full;
    170. 

  170. 	if (supported_link & IXGBE_LINK_SPEED_100_FULL)
    171. 

  171. 		ecmd->supported |= SUPPORTED_100baseT_Full;
    172. 

  172. 

  173. 	/* set the advertised speeds */
    174. 

  174. 	if (hw->phy.autoneg_advertised) {
    175. 

  175. 		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
    176. 

  176. 			ecmd->advertising |= ADVERTISED_100baseT_Full;
    177. 

  177. 		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
    178. 

  178. 			ecmd->advertising |= ADVERTISED_10000baseT_Full;
    179. 

  179. 		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
    180. 

  180. 			ecmd->advertising |= ADVERTISED_1000baseT_Full;
    181. 

  181. 	} else {
    182. 

  182. 		/* default modes in case phy.autoneg_advertised isn't set */
    183. 

  183. 		if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
    184. 

  184. 			ecmd->advertising |= ADVERTISED_10000baseT_Full;
    185. 

  185. 		if (supported_link & IXGBE_LINK_SPEED_1GB_FULL)
    186. 

  186. 			ecmd->advertising |= ADVERTISED_1000baseT_Full;
    187. 

  187. 		if (supported_link & IXGBE_LINK_SPEED_100_FULL)
    188. 

  188. 			ecmd->advertising |= ADVERTISED_100baseT_Full;
    189. 

  189. 	}
    190. 

  190. 

  191. 	if (autoneg) {
    192. 

  192. 		ecmd->supported |= SUPPORTED_Autoneg;
    193. 

  193. 		ecmd->advertising |= ADVERTISED_Autoneg;
    194. 

  194. 		ecmd->autoneg = AUTONEG_ENABLE;
    195. 

  195. 	} else
    196. 

  196. 		ecmd->autoneg = AUTONEG_DISABLE;
    197. 

  197. 

  198. 	ecmd->transceiver = XCVR_EXTERNAL;
    199. 

  199. 

  200. 	/* Determine the remaining settings based on the PHY type. */
    201. 

  201. 	switch (adapter->hw.phy.type) {
    202. 

  202. 	case ixgbe_phy_tn:
    203. 

  203. 	case ixgbe_phy_aq:
    204. 

  204. 	case ixgbe_phy_cu_unknown:
    205. 

  205. 		ecmd->supported |= SUPPORTED_TP;
    206. 

  206. 		ecmd->advertising |= ADVERTISED_TP;
    207. 

  207. 		ecmd->port = PORT_TP;
    208. 

  208. 		break;
    209. 

  209. 	case ixgbe_phy_qt:
    210. 

  210. 		ecmd->supported |= SUPPORTED_FIBRE;
    211. 

  211. 		ecmd->advertising |= ADVERTISED_FIBRE;
    212. 

  212. 		ecmd->port = PORT_FIBRE;
    213. 

  213. 		break;
    214. 

  214. 	case ixgbe_phy_nl:
    215. 

  215. 	case ixgbe_phy_sfp_passive_tyco:
    216. 

  216. 	case ixgbe_phy_sfp_passive_unknown:
    217. 

  217. 	case ixgbe_phy_sfp_ftl:
    218. 

  218. 	case ixgbe_phy_sfp_avago:
    219. 

  219. 	case ixgbe_phy_sfp_intel:
    220. 

  220. 	case ixgbe_phy_sfp_unknown:
    221. 

  221. 		/* SFP+ devices, further checking needed */
    222. 

  222. 		switch (adapter->hw.phy.sfp_type) {
    223. 

  223. 		case ixgbe_sfp_type_da_cu:
    224. 

  224. 		case ixgbe_sfp_type_da_cu_core0:
    225. 

  225. 		case ixgbe_sfp_type_da_cu_core1:
    226. 

  226. 			ecmd->supported |= SUPPORTED_FIBRE;
    227. 

  227. 			ecmd->advertising |= ADVERTISED_FIBRE;
    228. 

  228. 			ecmd->port = PORT_DA;
    229. 

  229. 			break;
    230. 

  230. 		case ixgbe_sfp_type_sr:
    231. 

  231. 		case ixgbe_sfp_type_lr:
    232. 

  232. 		case ixgbe_sfp_type_srlr_core0:
    233. 

  233. 		case ixgbe_sfp_type_srlr_core1:
    234. 

  234. 			ecmd->supported |= SUPPORTED_FIBRE;
    235. 

  235. 			ecmd->advertising |= ADVERTISED_FIBRE;
    236. 

  236. 			ecmd->port = PORT_FIBRE;
    237. 

  237. 			break;
    238. 

  238. 		case ixgbe_sfp_type_not_present:
    239. 

  239. 			ecmd->supported |= SUPPORTED_FIBRE;
    240. 

  240. 			ecmd->advertising |= ADVERTISED_FIBRE;
    241. 

  241. 			ecmd->port = PORT_NONE;
    242. 

  242. 			break;
    243. 

  243. 		case ixgbe_sfp_type_1g_cu_core0:
    244. 

  244. 		case ixgbe_sfp_type_1g_cu_core1:
    245. 

  245. 			ecmd->supported |= SUPPORTED_TP;
    246. 

  246. 			ecmd->advertising |= ADVERTISED_TP;
    247. 

  247. 			ecmd->port = PORT_TP;
    248. 

  248. 			break;
    249. 

  249. 		case ixgbe_sfp_type_1g_sx_core0:
    250. 

  250. 		case ixgbe_sfp_type_1g_sx_core1:
    251. 

  251. 			ecmd->supported |= SUPPORTED_FIBRE;
    252. 

  252. 			ecmd->advertising |= ADVERTISED_FIBRE;
    253. 

  253. 			ecmd->port = PORT_FIBRE;
    254. 

  254. 			break;
    255. 

  255. 		case ixgbe_sfp_type_unknown:
    256. 

  256. 		default:
    257. 

  257. 			ecmd->supported |= SUPPORTED_FIBRE;
    258. 

  258. 			ecmd->advertising |= ADVERTISED_FIBRE;
    259. 

  259. 			ecmd->port = PORT_OTHER;
    260. 

  260. 			break;
    261. 

  261. 		}
    262. 

  262. 		break;
    263. 

  263. 	case ixgbe_phy_xaui:
    264. 

  264. 		ecmd->supported |= SUPPORTED_FIBRE;
    265. 

  265. 		ecmd->advertising |= ADVERTISED_FIBRE;
    266. 

  266. 		ecmd->port = PORT_NONE;
    267. 

  267. 		break;
    268. 

  268. 	case ixgbe_phy_unknown:
    269. 

  269. 	case ixgbe_phy_generic:
    270. 

  270. 	case ixgbe_phy_sfp_unsupported:
    271. 

  271. 	default:
    272. 

  272. 		ecmd->supported |= SUPPORTED_FIBRE;
    273. 

  273. 		ecmd->advertising |= ADVERTISED_FIBRE;
    274. 

  274. 		ecmd->port = PORT_OTHER;
    275. 

  275. 		break;
    276. 

  276. 	}
    277. 

  277. 

  278. 	hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
    279. 

  279. 	if (link_up) {
    280. 

  280. 		switch (link_speed) {
    281. 

  281. 		case IXGBE_LINK_SPEED_10GB_FULL:
    282. 

  282. 			ethtool_cmd_speed_set(ecmd, SPEED_10000);
    283. 

  283. 			break;
    284. 

  284. 		case IXGBE_LINK_SPEED_1GB_FULL:
    285. 

  285. 			ethtool_cmd_speed_set(ecmd, SPEED_1000);
    286. 

  286. 			break;
    287. 

  287. 		case IXGBE_LINK_SPEED_100_FULL:
    288. 

  288. 			ethtool_cmd_speed_set(ecmd, SPEED_100);
    289. 

  289. 			break;
    290. 

  290. 		default:
    291. 

  291. 			break;
    292. 

  292. 		}
    293. 

  293. 		ecmd->duplex = DUPLEX_FULL;
    294. 

  294. 	} else {
    295. 

  295. 		ethtool_cmd_speed_set(ecmd, -1);
    296. 

  296. 		ecmd->duplex = -1;
    297. 

  297. 	}
    298. 

  298. 

  299. 	return 0;
    300. 

  300. }
    301. 

  301. 

  302. static int ixgbe_set_settings(struct net_device *netdev,
    303. 

  303.                               struct ethtool_cmd *ecmd)
    304. 

  304. {
    305. 

  305. 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
    306. 

  306. 	struct ixgbe_hw *hw = &adapter->hw;
    307. 

  307. 	u32 advertised, old;
    308. 

  308. 	s32 err = 0;
    309. 

  309. 

  310. 	if ((hw->phy.media_type == ixgbe_media_type_copper) ||
    311. 

  311. 	    (hw->phy.multispeed_fiber)) {
    312. 

  312. 		/*
    313. 

  313. 		 * this function does not support duplex forcing, but can
    314. 

  314. 		 * limit the advertising of the adapter to the specified speed
    315. 

  315. 		 */
    316. 

  316. 		if (ecmd->autoneg == AUTONEG_DISABLE)
    317. 

  317. 			return -EINVAL;
    318. 

  318. 

  319. 		if (ecmd->advertising & ~ecmd->supported)
    320. 

  320. 			return -EINVAL;
    321. 

  321. 

  322. 		old = hw->phy.autoneg_advertised;
    323. 

  323. 		advertised = 0;
    324. 

  324. 		if (ecmd->advertising & ADVERTISED_10000baseT_Full)
    325. 

  325. 			advertised |= IXGBE_LINK_SPEED_10GB_FULL;
    326. 

  326. 

  327. 		if (ecmd->advertising & ADVERTISED_1000baseT_Full)
    328. 

  328. 			advertised |= IXGBE_LINK_SPEED_1GB_FULL;
    329. 

  329. 

  330. 		if (ecmd->advertising & ADVERTISED_100baseT_Full)
    331. 

  331. 			advertised |= IXGBE_LINK_SPEED_100_FULL;
    332. 

  332. 

  333. 		if (old == advertised)
    334. 

  334. 			return err;
    335. 

  335. 		/* this sets the link speed and restarts auto-neg */
    336. 

  336. 		hw->mac.autotry_restart = true;
    337. 

  337. 		err = hw->mac.ops.setup_link(hw, advertised, true);
    338. 

  338. 		if (err) {
    339. 

  339. 			e_info(probe, "setup link failed with code %d\n", err);
    340. 

  340. 			hw->mac.ops.setup_link(hw, old, true);
    341. 

  341. 		}
    342. 

  342. 	} else {
    343. 

  343. 		/* in this case we currently only support 10Gb/FULL */
    344. 

  344. 		u32 speed = ethtool_cmd_speed(ecmd);
    345. 

  345. 		if ((ecmd->autoneg == AUTONEG_ENABLE) ||
    346. 

  346. 		    (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
    347. 

  347. 		    (speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
    348. 

  348. 			return -EINVAL;
    349. 

  349. 	}
    350. 

  350. 

  351. 	return err;
    352. 

  352. }
    353. 

  353. 

  354. static void ixgbe_get_pauseparam(struct net_device *netdev,
    355. 

  355.                                  struct ethtool_pauseparam *pause)
    356. 

  356. {
    357. 

  357. 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
    358. 

  358. 	struct ixgbe_hw *hw = &adapter->hw;
    359. 

  359. 

  360. 	if (hw->fc.disable_fc_autoneg)
    361. 

  361. 		pause->autoneg = 0;
    362. 

  362. 	else
    363. 

  363. 		pause->autoneg = 1;
    364. 

  364. 

  365. 	if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
    366. 

  366. 		pause->rx_pause = 1;
    367. 

  367. 	} else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
    368. 

  368. 		pause->tx_pause = 1;
    369. 

  369. 	} else if (hw->fc.current_mode == ixgbe_fc_full) {
    370. 

  370. 		pause->rx_pause = 1;
    371. 

  371. 		pause->tx_pause = 1;
    372. 

  372. 	}
    373. 

  373. }
    374. 

  374. 

  375. static int ixgbe_set_pauseparam(struct net_device *netdev,
    376. 

  376.                                 struct ethtool_pauseparam *pause)
    377. 

  377. {
    378. 

  378. 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
    379. 

  379. 	struct ixgbe_hw *hw = &adapter->hw;
    380. 

  380. 	struct ixgbe_fc_info fc = hw->fc;
    381. 

  381. 

  382. 	/* 82598 does no support link flow control with DCB enabled */
    383. 

  383. 	if ((hw->mac.type == ixgbe_mac_82598EB) &&
    384. 

  384. 	    (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
    385. 

  385. 		return -EINVAL;
    386. 

  386. 

  387. 	/* some devices do not support autoneg of link flow control */
    388. 

  388. 	if ((pause->autoneg == AUTONEG_ENABLE) &&
    389. 

  389. 	    (ixgbe_device_supports_autoneg_fc(hw) != 0))
    390. 

  390. 		return -EINVAL;
    391. 

  391. 

  392. 	fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE);
    393. 

  393. 

  394. 	if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
    395. 

  395. 		fc.requested_mode = ixgbe_fc_full;
    396. 

  396. 	else if (pause->rx_pause && !pause->tx_pause)
    397. 

  397. 		fc.requested_mode = ixgbe_fc_rx_pause;
    398. 

  398. 	else if (!pause->rx_pause && pause->tx_pause)
    399. 

  399. 		fc.requested_mode = ixgbe_fc_tx_pause;
    400. 

  400. 	else
    401. 

  401. 		fc.requested_mode = ixgbe_fc_none;
    402. 

  402. 

  403. 	/* if the thing changed then we'll update and use new autoneg */
    404. 

  404. 	if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
    405. 

  405. 		hw->fc = fc;
    406. 

  406. 		if (netif_running(netdev))
    407. 

  407. 			ixgbe_reinit_locked(adapter);
    408. 

  408. 		else
    409. 

  409. 			ixgbe_reset(adapter);
    410. 

  410. 	}
    411. 

  411. 

  412. 	return 0;
    413. 

  413. }
    414. 

  414. 

  415. static u32 ixgbe_get_msglevel(struct net_device *netdev)
    416. 

  416. {
    417. 

  417. 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
    418. 

  418. 	return adapter->msg_enable;
    419. 

  419. }
    420. 

  420. 

  421. static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
    422. 

  422. {
    423. 

  423. 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
    424. 

  424. 	adapter->msg_enable = data;
    425. 

  425. }
    426. 

  426. 

  427. static int ixgbe_get_regs_len(struct net_device *netdev)
    428. 

  428. {
    429. 

  429. #define IXGBE_REGS_LEN  1129
    430. 

  430. 	return IXGBE_REGS_LEN * sizeof(u32);
    431. 

  431. }
    432. 

  432. 

  433. #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
    434. 

  434. 

  435. static void ixgbe_get_regs(struct net_device *netdev,
    436. 

  436.                            struct ethtool_regs *regs, void *p)
    437. 

  437. {
    438. 

  438. 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
    439. 

  439. 	struct ixgbe_hw *hw = &adapter->hw;
    440. 

  440. 	u32 *regs_buff = p;
    441. 

  441. 	u8 i;
    442. 

  442. 

  443. 	memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
    444. 

  444. 

  445. 	regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
    446. 

  446. 

  447. 	/* General Registers */
    448. 

  448. 	regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
    449. 

  449. 	regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
    450. 

  450. 	regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
    451. 

  451. 	regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
    452. 

  452. 	regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
    453. 

  453. 	regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
    454. 

  454. 	regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
    455. 

  455. 	regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
    456. 

  456. 

  457. 	/* NVM Register */
    458. 

  458. 	regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
    459. 

  459. 	regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
    460. 

  460. 	regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
    461. 

  461. 	regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
    462. 

  462. 	regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
    463. 

  463. 	regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
    464. 

  464. 	regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
    465. 

  465. 	regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
    466. 

  466. 	regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
    467. 

  467. 	regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
    468. 

  468. 

  469. 	/* Interrupt */
    470. 

  470. 	/* don't read EICR because it can clear interrupt causes, instead
    471. 

  471. 	 * read EICS which is a shadow but doesn't clear EICR */
    472. 

  472. 	regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
    473. 

  473. 	regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
    474. 

  474. 	regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
    475. 

  475. 	regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
    476. 

  476. 	regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
    477. 

  477. 	regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
    478. 

  478. 	regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
    479. 

  479. 	regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
    480. 

  480. 	regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
    481. 

  481. 	regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
    482. 

  482. 	regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
    483. 

  483. 	regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
    484. 

  484. 

  485. 	/* Flow Control */
    486. 

  486. 	regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
    487. 

  487. 	regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
    488. 

  488. 	regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
    489. 

  489. 	regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
    490. 

  490. 	regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
    491. 

  491. 	for (i = 0; i < 8; i++) {
    492. 

  492. 		switch (hw->mac.type) {
    493. 

  493. 		case ixgbe_mac_82598EB:
    494. 

  494. 			regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
    495. 

  495. 			regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
    496. 

  496. 			break;
    497. 

  497. 		case ixgbe_mac_82599EB:
    498. 

  498. 		case ixgbe_mac_X540:
    499. 

  499. 			regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i));
    500. 

  500. 			regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
    501. 

  501. 			break;
    502. 

  502. 		default:
    503. 

  503. 			break;
    504. 

  504. 		}
    505. 

  505. 	}
    506. 

  506. 	regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
    507. 

  507. 	regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
    508. 

  508. 

  509. 	/* Receive DMA */
    510. 

  510. 	for (i = 0; i < 64; i++)
    511. 

  511. 		regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
    512. 

  512. 	for (i = 0; i < 64; i++)
    513. 

  513. 		regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
    514. 

  514. 	for (i = 0; i < 64; i++)
    515. 

  515. 		regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
    516. 

  516. 	for (i = 0; i < 64; i++)
    517. 

  517. 		regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
    518. 

  518. 	for (i = 0; i < 64; i++)
    519. 

  519. 		regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
    520. 

  520. 	for (i = 0; i < 64; i++)
    521. 

  521. 		regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
    522. 

  522. 	for (i = 0; i < 16; i++)
    523. 

  523. 		regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
    524. 

  524. 	for (i = 0; i < 16; i++)
    525. 

  525. 		regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
    526. 

  526. 	regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
    527. 

  527. 	for (i = 0; i < 8; i++)
    528. 

  528. 		regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
    529. 

  529. 	regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
    530. 

  530. 	regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
    531. 

  531. 

  532. 	/* Receive */
    533. 

  533. 	regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
    534. 

  534. 	regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
    535. 

  535. 	for (i = 0; i < 16; i++)
    536. 

  536. 		regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
    537. 

  537. 	for (i = 0; i < 16; i++)
    538. 

  538. 		regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
    539. 

  539. 	regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
    540. 

  540. 	regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
    541. 

  541. 	regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
    542. 

  542. 	regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
    543. 

  543. 	regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
    544. 

  544. 	regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
    545. 

  545. 	for (i = 0; i < 8; i++)
    546. 

  546. 		regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
    547. 

  547. 	for (i = 0; i < 8; i++)
    548. 

  548. 		regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
    549. 

  549. 	regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
    550. 

  550. 

  551. 	/* Transmit */
    552. 

  552. 	for (i = 0; i < 32; i++)
    553. 

  553. 		regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
    554. 

  554. 	for (i = 0; i < 32; i++)
    555. 

  555. 		regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
    556. 

  556. 	for (i = 0; i < 32; i++)
    557. 

  557. 		regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
    558. 

  558. 	for (i = 0; i < 32; i++)
    559. 

  559. 		regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
    560. 

  560. 	for (i = 0; i < 32; i++)
    561. 

  561. 		regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
    562. 

  562. 	for (i = 0; i < 32; i++)
    563. 

  563. 		regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
    564. 

  564. 	for (i = 0; i < 32; i++)
    565. 

  565. 		regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
    566. 

  566. 	for (i = 0; i < 32; i++)
    567. 

  567. 		regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
    568. 

  568. 	regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
    569. 

  569. 	for (i = 0; i < 16; i++)
    570. 

  570. 		regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
    571. 

  571. 	regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
    572. 

  572. 	for (i = 0; i < 8; i++)
    573. 

  573. 		regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
    574. 

  574. 	regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
    575. 

  575. 

  576. 	/* Wake Up */
    577. 

  577. 	regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
    578. 

  578. 	regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
    579. 

  579. 	regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
    580. 

  580. 	regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
    581. 

  581. 	regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
    582. 

  582. 	regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
    583. 

  583. 	regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
    584. 

  584. 	regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
    585. 

  585. 	regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
    586. 

  586. 

  587. 	/* DCB */
    588. 

  588. 	regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
    589. 

  589. 	regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
    590. 

  590. 	regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
    591. 

  591. 	regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
    592. 

  592. 	for (i = 0; i < 8; i++)
    593. 

  593. 		regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
    594. 

  594. 	for (i = 0; i < 8; i++)
    595. 

  595. 		regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
    596. 

  596. 	for (i = 0; i < 8; i++)
    597. 

  597. 		regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
    598. 

  598. 	for (i = 0; i < 8; i++)
    599. 

  599. 		regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
    600. 

  600. 	for (i = 0; i < 8; i++)
    601. 

  601. 		regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
    602. 

  602. 	for (i = 0; i < 8; i++)
    603. 

  603. 		regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
    604. 

  604. 

  605. 	/* Statistics */
    606. 

  606. 	regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
    607. 

  607. 	regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
    608. 

  608. 	regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
    609. 

  609. 	regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
    610. 

  610. 	for (i = 0; i < 8; i++)
    611. 

  611. 		regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
    612. 

  612. 	regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
    613. 

  613. 	regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
    614. 

  614. 	regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
    615. 

  615. 	regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
    616. 

  616. 	regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
    617. 

  617. 	regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
    618. 

  618. 	regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
    619. 

  619. 	for (i = 0; i < 8; i++)
    620. 

  620. 		regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
    621. 

  621. 	for (i = 0; i < 8; i++)
    622. 

  622. 		regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
    623. 

  623. 	for (i = 0; i < 8; i++)
    624. 

  624. 		regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
    625. 

  625. 	for (i = 0; i < 8; i++)
    626. 

  626. 		regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
    627. 

  627. 	regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
    628. 

  628. 	regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
    629. 

  629. 	regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
    630. 

  630. 	regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
    631. 

  631. 	regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
    632. 

  632. 	regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
    633. 

  633. 	regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
    634. 

  634. 	regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
    635. 

  635. 	regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
    636. 

  636. 	regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
    637. 

  637. 	regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
    638. 

  638. 	regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
    639. 

  639. 	for (i = 0; i < 8; i++)
    640. 

  640. 		regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
    641. 

  641. 	regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
    642. 

  642. 	regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
    643. 

  643. 	regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
    644. 

  644. 	regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
    645. 

  645. 	regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
    646. 

  646. 	regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
    647. 

  647. 	regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
    648. 

  648. 	regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
    649. 

  649. 	regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
    650. 

  650. 	regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
    651. 

  651. 	regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
    652. 

  652. 	regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
    653. 

  653. 	regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
    654. 

  654. 	regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
    655. 

  655. 	regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
    656. 

  656. 	regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
    657. 

  657. 	regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
    658. 

  658. 	regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
    659. 

  659. 	regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
    660. 

  660. 	for (i = 0; i < 16; i++)
    661. 

  661. 		regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
    662. 

  662. 	for (i = 0; i < 16; i++)
    663. 

  663. 		regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
    664. 

  664. 	for (i = 0; i < 16; i++)
    665. 

  665. 		regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
    666. 

  666. 	for (i = 0; i < 16; i++)
    667. 

  667. 		regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
    668. 

  668. 

  669. 	/* MAC */
    670. 

  670. 	regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
    671. 

  671. 	regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
    672. 

  672. 	regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
    673. 

  673. 	regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
    674. 

  674. 	regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
    675. 

  675. 	regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
    676. 

  676. 	regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
    677. 

  677. 	regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
    678. 

  678. 	regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
    679. 

  679. 	regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
    680. 

  680. 	regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
    681. 

  681. 	regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
    682. 

  682. 	regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
    683. 

  683. 	regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
    684. 

  684. 	regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
    685. 

  685. 	regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
    686. 

  686. 	regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
    687. 

  687. 	regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
    688. 

  688. 	regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
    689. 

  689. 	regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
    690. 

  690. 	regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
    691. 

  691. 	regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
    692. 

  692. 	regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
    693. 

  693. 	regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
    694. 

  694. 	regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
    695. 

  695. 	regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
    696. 

  696. 	regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
    697. 

  697. 	regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
    698. 

  698. 	regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
    699. 

  699. 	regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
    700. 

  700. 	regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
    701. 

  701. 	regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
    702. 

  702. 	regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
    703. 

  703. 

  704. 	/* Diagnostic */
    705. 

  705. 	regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
    706. 

  706. 	for (i = 0; i < 8; i++)
    707. 

  707. 		regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
    708. 

  708. 	regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
    709. 

  709. 	for (i = 0; i < 4; i++)
    710. 

  710. 		regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
    711. 

  711. 	regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
    712. 

  712. 	regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
    713. 

  713. 	for (i = 0; i < 8; i++)
    714. 

  714. 		regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
    715. 

  715. 	regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
    716. 

  716. 	for (i = 0; i < 4; i++)
    717. 

  717. 		regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
    718. 

  718. 	regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
    719. 

  719. 	regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
    720. 

  720. 	regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
    721. 

  721. 	regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
    722. 

  722. 	regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
    723. 

  723. 	regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
    724. 

  724. 	regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
    725. 

  725. 	regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
    726. 

  726. 	regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
    727. 

  727. 	regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
    728. 

  728. 	regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
    729. 

  729. 	for (i = 0; i < 8; i++)
    730. 

  730. 		regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
    731. 

  731. 	regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
    732. 

  732. 	regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
    733. 

  733. 	regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
    734. 

  734. 	regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
    735. 

  735. 	regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
    736. 

  736. 	regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
    737. 

  737. 	regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
    738. 

  738. 	regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
    739. 

  739. 	regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
    740. 

  740. 

  741. 	/* 82599 X540 specific registers  */
    742. 

  742. 	regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN);
    743. 

  743. }
    744. 

  744. 

  745. static int ixgbe_get_eeprom_len(struct net_device *netdev)
    746. 

  746. {
    747. 

  747. 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
    748. 

  748. 	return adapter->hw.eeprom.word_size * 2;
    749. 

  749. }
    750. 

  750. 

  751. static int ixgbe_get_eeprom(struct net_device *netdev,
    752. 

  752.                             struct ethtool_eeprom *eeprom, u8 *bytes)
    753. 

  753. {
    754. 

  754. 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
    755. 

  755. 	struct ixgbe_hw *hw = &adapter->hw;
    756. 

  756. 	u16 *eeprom_buff;
    757. 

  757. 	int first_word, last_word, eeprom_len;
    758. 

  758. 	int ret_val = 0;
    759. 

  759. 	u16 i;
    760. 

  760. 

  761. 	if (eeprom->len == 0)
    762. 

  762. 		return -EINVAL;
    763. 

  763. 

  764. 	eeprom->magic = hw->vendor_id | (hw->device_id << 16);
    765. 

  765. 

  766. 	first_word = eeprom->offset >> 1;
    767. 

  767. 	last_word = (eeprom->offset + eeprom->len - 1) >> 1;
    768. 

  768. 	eeprom_len = last_word - first_word + 1;
    769. 

  769. 

  770. 	eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
    771. 

  771. 	if (!eeprom_buff)
    772. 

  772. 		return -ENOMEM;
    773. 

  773. 

  774. 	ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len,
    775. 

  775. 					     eeprom_buff);
    776. 

  776. 

  777. 	/* Device's eeprom is always little-endian, word addressable */
    778. 

  778. 	for (i = 0; i < eeprom_len; i++)
    779. 

  779. 		le16_to_cpus(&eeprom_buff[i]);
    780. 

  780. 

  781. 	memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
    782. 

  782. 	kfree(eeprom_buff);
    783. 

  783. 

  784. 	return ret_val;
    785. 

  785. }
    786. 

  786. 

  787. static int ixgbe_set_eeprom(struct net_device *netdev,
    788. 

  788. 			    struct ethtool_eeprom *eeprom, u8 *bytes)
    789. 

  789. {
    790. 

  790. 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
    791. 

  791. 	struct ixgbe_hw *hw = &adapter->hw;
    792. 

  792. 	u16 *eeprom_buff;
    793. 

  793. 	void *ptr;
    794. 

  794. 	int max_len, first_word, last_word, ret_val = 0;
    795. 

  795. 	u16 i;
    796. 

  796. 

  797. 	if (eeprom->len == 0)
    798. 

  798. 		return -EINVAL;
    799. 

  799. 

  800. 	if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
    801. 

  801. 		return -EINVAL;
    802. 

  802. 

  803. 	max_len = hw->eeprom.word_size * 2;
    804. 

  804. 

  805. 	first_word = eeprom->offset >> 1;
    806. 

  806. 	last_word = (eeprom->offset + eeprom->len - 1) >> 1;
    807. 

  807. 	eeprom_buff = kmalloc(max_len, GFP_KERNEL);
    808. 

  808. 	if (!eeprom_buff)
    809. 

  809. 		return -ENOMEM;
    810. 

  810. 

  811. 	ptr = eeprom_buff;
    812. 

  812. 

  813. 	if (eeprom->offset & 1) {
    814. 

  814. 		/*
    815. 

  815. 		 * need read/modify/write of first changed EEPROM word
    816. 

  816. 		 * only the second byte of the word is being modified
    817. 

  817. 		 */
    818. 

  818. 		ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]);
    819. 

  819. 		if (ret_val)
    820. 

  820. 			goto err;
    821. 

  821. 

  822. 		ptr++;
    823. 

  823. 	}
    824. 

  824. 	if ((eeprom->offset + eeprom->len) & 1) {
    825. 

  825. 		/*
    826. 

  826. 		 * need read/modify/write of last changed EEPROM word
    827. 

  827. 		 * only the first byte of the word is being modified
    828. 

  828. 		 */
    829. 

  829. 		ret_val = hw->eeprom.ops.read(hw, last_word,
    830. 

  830. 					  &eeprom_buff[last_word - first_word]);
    831. 

  831. 		if (ret_val)
    832. 

  832. 			goto err;
    833. 

  833. 	}
    834. 

  834. 

  835. 	/* Device's eeprom is always little-endian, word addressable */
    836. 

  836. 	for (i = 0; i < last_word - first_word + 1; i++)
    837. 

  837. 		le16_to_cpus(&eeprom_buff[i]);
    838. 

  838. 

  839. 	memcpy(ptr, bytes, eeprom->len);
    840. 

  840. 

  841. 	for (i = 0; i < last_word - first_word + 1; i++)
    842. 

  842. 		cpu_to_le16s(&eeprom_buff[i]);
    843. 

  843. 

  844. 	ret_val = hw->eeprom.ops.write_buffer(hw, first_word,
    845. 

  845. 					      last_word - first_word + 1,
    846. 

  846. 					      eeprom_buff);
    847. 

  847. 

  848. 	/* Update the checksum */
    849. 

  849. 	if (ret_val == 0)
    850. 

  850. 		hw->eeprom.ops.update_checksum(hw);
    851. 

  851. 

  852. err:
    853. 

  853. 	kfree(eeprom_buff);
    854. 

  854. 	return ret_val;
    855. 

  855. }
    856. 

  856. 

  857. static void ixgbe_get_drvinfo(struct net_device *netdev,
    858. 

  858.                               struct ethtool_drvinfo *drvinfo)
    859. 

  859. {
    860. 

  860. 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
    861. 

  861. 	u32 nvm_track_id;
    862. 

  862. 

  863. 	strlcpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver));
    864. 

  864. 	strlcpy(drvinfo->version, ixgbe_driver_version,
    865. 

  865. 		sizeof(drvinfo->version));
    866. 

  866. 

  867. 	nvm_track_id = (adapter->eeprom_verh << 16) |
    868. 

  868. 			adapter->eeprom_verl;
    869. 

  869. 	snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), "0x%08x",
    870. 

  870. 		 nvm_track_id);
    871. 

  871. 

  872. 	strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
    873. 

  873. 		sizeof(drvinfo->bus_info));
    874. 

  874. 	drvinfo->n_stats = IXGBE_STATS_LEN;
    875. 

  875. 	drvinfo->testinfo_len = IXGBE_TEST_LEN;
    876. 

  876. 	drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
    877. 

  877. }
    878. 

  878. 

  879. static void ixgbe_get_ringparam(struct net_device *netdev,
    880. 

  880.                                 struct ethtool_ringparam *ring)
    881. 

  881. {
    882. 

  882. 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
    883. 

  883. 	struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
    884. 

  884. 	struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
    885. 

  885. 

  886. 	ring->rx_max_pending = IXGBE_MAX_RXD;
    887. 

  887. 	ring->tx_max_pending = IXGBE_MAX_TXD;
    888. 

  888. 	ring->rx_pending = rx_ring->count;
    889. 

  889. 	ring->tx_pending = tx_ring->count;
    890. 

  890. }
    891. 

  891. 

  892. static int ixgbe_set_ringparam(struct net_device *netdev,
    893. 

  893.                                struct ethtool_ringparam *ring)
    894. 

  894. {
    895. 

  895. 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
    896. 

  896. 	struct ixgbe_ring *temp_ring;
    897. 

  897. 	int i, err = 0;
    898. 

  898. 	u32 new_rx_count, new_tx_count;
    899. 

  899. 

  900. 	if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
    901. 

  901. 		return -EINVAL;
    902. 

  902. 

  903. 	new_tx_count = clamp_t(u32, ring->tx_pending,
    904. 

  904. 			       IXGBE_MIN_TXD, IXGBE_MAX_TXD);
    905. 

  905. 	new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
    906. 

  906. 

  907. 	new_rx_count = clamp_t(u32, ring->rx_pending,
    908. 

  908. 			       IXGBE_MIN_RXD, IXGBE_MAX_RXD);
    909. 

  909. 	new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
    910. 

  910. 

  911. 	if ((new_tx_count == adapter->tx_ring_count) &&
    912. 

  912. 	    (new_rx_count == adapter->rx_ring_count)) {
    913. 

  913. 		/* nothing to do */
    914. 

  914. 		return 0;
    915. 

  915. 	}
    916. 

  916. 

  917. 	while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
    918. 

  918. 		usleep_range(1000, 2000);
    919. 

  919. 

  920. 	if (!netif_running(adapter->netdev)) {
    921. 

  921. 		for (i = 0; i < adapter->num_tx_queues; i++)
    922. 

  922. 			adapter->tx_ring[i]->count = new_tx_count;
    923. 

  923. 		for (i = 0; i < adapter->num_rx_queues; i++)
    924. 

  924. 			adapter->rx_ring[i]->count = new_rx_count;
    925. 

  925. 		adapter->tx_ring_count = new_tx_count;
    926. 

  926. 		adapter->rx_ring_count = new_rx_count;
    927. 

  927. 		goto clear_reset;
    928. 

  928. 	}
    929. 

  929. 

  930. 	/* allocate temporary buffer to store rings in */
    931. 

  931. 	i = max_t(int, adapter->num_tx_queues, adapter->num_rx_queues);
    932. 

  932. 	temp_ring = vmalloc(i * sizeof(struct ixgbe_ring));
    933. 

  933. 

  934. 	if (!temp_ring) {
    935. 

  935. 		err = -ENOMEM;
    936. 

  936. 		goto clear_reset;
    937. 

  937. 	}
    938. 

  938. 

  939. 	ixgbe_down(adapter);
    940. 

  940. 

  941. 	/*
    942. 

  942. 	 * Setup new Tx resources and free the old Tx resources in that order.
    943. 

  943. 	 * We can then assign the new resources to the rings via a memcpy.
    944. 

  944. 	 * The advantage to this approach is that we are guaranteed to still
    945. 

  945. 	 * have resources even in the case of an allocation failure.
    946. 

  946. 	 */
    947. 

  947. 	if (new_tx_count != adapter->tx_ring_count) {
    948. 

  948. 		for (i = 0; i < adapter->num_tx_queues; i++) {
    949. 

  949. 			memcpy(&temp_ring[i], adapter->tx_ring[i],
    950. 

  950. 			       sizeof(struct ixgbe_ring));
    951. 

  951. 

  952. 			temp_ring[i].count = new_tx_count;
    953. 

  953. 			err = ixgbe_setup_tx_resources(&temp_ring[i]);
    954. 

  954. 			if (err) {
    955. 

  955. 				while (i) {
    956. 

  956. 					i--;
    957. 

  957. 					ixgbe_free_tx_resources(&temp_ring[i]);
    958. 

  958. 				}
    959. 

  959. 				goto err_setup;
    960. 

  960. 			}
    961. 

  961. 		}
    962. 

  962. 

  963. 		for (i = 0; i < adapter->num_tx_queues; i++) {
    964. 

  964. 			ixgbe_free_tx_resources(adapter->tx_ring[i]);
    965. 

  965. 

  966. 			memcpy(adapter->tx_ring[i], &temp_ring[i],
    967. 

  967. 			       sizeof(struct ixgbe_ring));
    968. 

  968. 		}
    969. 

  969. 

  970. 		adapter->tx_ring_count = new_tx_count;
    971. 

  971. 	}
    972. 

  972. 

  973. 	/* Repeat the process for the Rx rings if needed */
    974. 

  974. 	if (new_rx_count != adapter->rx_ring_count) {
    975. 

  975. 		for (i = 0; i < adapter->num_rx_queues; i++) {
    976. 

  976. 			memcpy(&temp_ring[i], adapter->rx_ring[i],
    977. 

  977. 			       sizeof(struct ixgbe_ring));
    978. 

  978. 

  979. 			temp_ring[i].count = new_rx_count;
    980. 

  980. 			err = ixgbe_setup_rx_resources(&temp_ring[i]);
    981. 

  981. 			if (err) {
    982. 

  982. 				while (i) {
    983. 

  983. 					i--;
    984. 

  984. 					ixgbe_free_rx_resources(&temp_ring[i]);
    985. 

  985. 				}
    986. 

  986. 				goto err_setup;
    987. 

  987. 			}
    988. 

  988. 

  989. 		}
    990. 

  990. 

  991. 		for (i = 0; i < adapter->num_rx_queues; i++) {
    992. 

  992. 			ixgbe_free_rx_resources(adapter->rx_ring[i]);
    993. 

  993. 

  994. 			memcpy(adapter->rx_ring[i], &temp_ring[i],
    995. 

  995. 			       sizeof(struct ixgbe_ring));
    996. 

  996. 		}
    997. 

  997. 

  998. 		adapter->rx_ring_count = new_rx_count;
    999. 

  999. 	}
    1000. 

  1000. 

  1001. err_setup:
    1002. 

  1002. 	ixgbe_up(adapter);
    1003. 

  1003. 	vfree(temp_ring);
    1004. 

  1004. clear_reset:
    1005. 

  1005. 	clear_bit(__IXGBE_RESETTING, &adapter->state);
    1006. 

  1006. 	return err;
    1007. 

  1007. }
    1008. 

  1008. 

  1009. static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
    1010. 

  1010. {
    1011. 

  1011. 	switch (sset) {
    1012. 

  1012. 	case ETH_SS_TEST:
    1013. 

  1013. 		return IXGBE_TEST_LEN;
    1014. 

  1014. 	case ETH_SS_STATS:
    1015. 

  1015. 		return IXGBE_STATS_LEN;
    1016. 

  1016. 	default:
    1017. 

  1017. 		return -EOPNOTSUPP;
    1018. 

  1018. 	}
    1019. 

  1019. }
    1020. 

  1020. 

  1021. static void ixgbe_get_ethtool_stats(struct net_device *netdev,
    1022. 

  1022.                                     struct ethtool_stats *stats, u64 *data)
    1023. 

  1023. {
    1024. 

  1024. 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
    1025. 

  1025. 	struct rtnl_link_stats64 temp;
    1026. 

  1026. 	const struct rtnl_link_stats64 *net_stats;
    1027. 

  1027. 	unsigned int start;
    1028. 

  1028. 	struct ixgbe_ring *ring;
    1029. 

  1029. 	int i, j;
    1030. 

  1030. 	char *p = NULL;
    1031. 

  1031. 

  1032. 	ixgbe_update_stats(adapter);
    1033. 

  1033. 	net_stats = dev_get_stats(netdev, &temp);
    1034. 

  1034. 	for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
    1035. 

  1035. 		switch (ixgbe_gstrings_stats[i].type) {
    1036. 

  1036. 		case NETDEV_STATS:
    1037. 

  1037. 			p = (char *) net_stats +
    1038. 

  1038. 					ixgbe_gstrings_stats[i].stat_offset;
    1039. 

  1039. 			break;
    1040. 

  1040. 		case IXGBE_STATS:
    1041. 

  1041. 			p = (char *) adapter +
    1042. 

  1042. 					ixgbe_gstrings_stats[i].stat_offset;
    1043. 

  1043. 			break;
    1044. 

  1044. 		default:
    1045. 

  1045. 			data[i] = 0;
    1046. 

  1046. 			continue;
    1047. 

  1047. 		}
    1048. 

  1048. 

  1049. 		data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
    1050. 

  1050. 		           sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
    1051. 

  1051. 	}
    1052. 

  1052. 	for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) {
    1053. 

  1053. 		ring = adapter->tx_ring[j];
    1054. 

  1054. 		if (!ring) {
    1055. 

  1055. 			data[i] = 0;
    1056. 

  1056. 			data[i+1] = 0;
    1057. 

  1057. 			i += 2;
    1058. 

  1058. 			continue;
    1059. 

  1059. 		}
    1060. 

  1060. 

  1061. 		do {
    1062. 

  1062. 			start = u64_stats_fetch_begin_bh(&ring->syncp);
    1063. 

  1063. 			data[i]   = ring->stats.packets;
    1064. 

  1064. 			data[i+1] = ring->stats.bytes;
    1065. 

  1065. 		} while (u64_stats_fetch_retry_bh(&ring->syncp, start));
    1066. 

  1066. 		i += 2;
    1067. 

  1067. 	}
    1068. 

  1068. 	for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) {
    1069. 

  1069. 		ring = adapter->rx_ring[j];
    1070. 

  1070. 		if (!ring) {
    1071. 

  1071. 			data[i] = 0;
    1072. 

  1072. 			data[i+1] = 0;
    1073. 

  1073. 			i += 2;
    1074. 

  1074. 			continue;
    1075. 

  1075. 		}
    1076. 

  1076. 

  1077. 		do {
    1078. 

  1078. 			start = u64_stats_fetch_begin_bh(&ring->syncp);
    1079. 

  1079. 			data[i]   = ring->stats.packets;
    1080. 

  1080. 			data[i+1] = ring->stats.bytes;
    1081. 

  1081. 		} while (u64_stats_fetch_retry_bh(&ring->syncp, start));
    1082. 

  1082. 		i += 2;
    1083. 

  1083. 	}
    1084. 

  1084. 

  1085. 	for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
    1086. 

  1086. 		data[i++] = adapter->stats.pxontxc[j];
    1087. 

  1087. 		data[i++] = adapter->stats.pxofftxc[j];
    1088. 

  1088. 	}
    1089. 

  1089. 	for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
    1090. 

  1090. 		data[i++] = adapter->stats.pxonrxc[j];
    1091. 

  1091. 		data[i++] = adapter->stats.pxoffrxc[j];
    1092. 

  1092. 	}
    1093. 

  1093. }
    1094. 

  1094. 

  1095. static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
    1096. 

  1096.                               u8 *data)
    1097. 

  1097. {
    1098. 

  1098. 	char *p = (char *)data;
    1099. 

  1099. 	int i;
    1100. 

  1100. 

  1101. 	switch (stringset) {
    1102. 

  1102. 	case ETH_SS_TEST:
    1103. 

  1103. 		for (i = 0; i < IXGBE_TEST_LEN; i++) {
    1104. 

  1104. 			memcpy(data, ixgbe_gstrings_test[i], ETH_GSTRING_LEN);
    1105. 

  1105. 			data += ETH_GSTRING_LEN;
    1106. 

  1106. 		}
    1107. 

  1107. 		break;
    1108. 

  1108. 	case ETH_SS_STATS:
    1109. 

  1109. 		for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
    1110. 

  1110. 			memcpy(p, ixgbe_gstrings_stats[i].stat_string,
    1111. 

  1111. 			       ETH_GSTRING_LEN);
    1112. 

  1112. 			p += ETH_GSTRING_LEN;
    1113. 

  1113. 		}
    1114. 

  1114. 		for (i = 0; i < netdev->num_tx_queues; i++) {
    1115. 

  1115. 			sprintf(p, "tx_queue_%u_packets", i);
    1116. 

  1116. 			p += ETH_GSTRING_LEN;
    1117. 

  1117. 			sprintf(p, "tx_queue_%u_bytes", i);
    1118. 

  1118. 			p += ETH_GSTRING_LEN;
    1119. 

  1119. 		}
    1120. 

  1120. 		for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) {
    1121. 

  1121. 			sprintf(p, "rx_queue_%u_packets", i);
    1122. 

  1122. 			p += ETH_GSTRING_LEN;
    1123. 

  1123. 			sprintf(p, "rx_queue_%u_bytes", i);
    1124. 

  1124. 			p += ETH_GSTRING_LEN;
    1125. 

  1125. 		}
    1126. 

  1126. 		for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
    1127. 

  1127. 			sprintf(p, "tx_pb_%u_pxon", i);
    1128. 

  1128. 			p += ETH_GSTRING_LEN;
    1129. 

  1129. 			sprintf(p, "tx_pb_%u_pxoff", i);
    1130. 

  1130. 			p += ETH_GSTRING_LEN;
    1131. 

  1131. 		}
    1132. 

  1132. 		for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
    1133. 

  1133. 			sprintf(p, "rx_pb_%u_pxon", i);
    1134. 

  1134. 			p += ETH_GSTRING_LEN;
    1135. 

  1135. 			sprintf(p, "rx_pb_%u_pxoff", i);
    1136. 

  1136. 			p += ETH_GSTRING_LEN;
    1137. 

  1137. 		}
    1138. 

  1138. 		/* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
    1139. 

  1139. 		break;
    1140. 

  1140. 	}
    1141. 

  1141. }
    1142. 

  1142. 

  1143. static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
    1144. 

  1144. {
    1145. 

  1145. 	struct ixgbe_hw *hw = &adapter->hw;
    1146. 

  1146. 	bool link_up;
    1147. 

  1147. 	u32 link_speed = 0;
    1148. 

  1148. 	*data = 0;
    1149. 

  1149. 

  1150. 	hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
    1151. 

  1151. 	if (link_up)
    1152. 

  1152. 		return *data;
    1153. 

  1153. 	else
    1154. 

  1154. 		*data = 1;
    1155. 

  1155. 	return *data;
    1156. 

  1156. }
    1157. 

  1157. 

  1158. /* ethtool register test data */
    1159. 

  1159. struct ixgbe_reg_test {
    1160. 

  1160. 	u16 reg;
    1161. 

  1161. 	u8  array_len;
    1162. 

  1162. 	u8  test_type;
    1163. 

  1163. 	u32 mask;
    1164. 

  1164. 	u32 write;
    1165. 

  1165. };
    1166. 

  1166. 

  1167. /* In the hardware, registers are laid out either singly, in arrays
    1168. 

  1168.  * spaced 0x40 bytes apart, or in contiguous tables.  We assume
    1169. 

  1169.  * most tests take place on arrays or single registers (handled
    1170. 

  1170.  * as a single-element array) and special-case the tables.
    1171. 

  1171.  * Table tests are always pattern tests.
    1172. 

  1172.  *
    1173. 

  1173.  * We also make provision for some required setup steps by specifying
    1174. 

  1174.  * registers to be written without any read-back testing.
    1175. 

  1175.  */
    1176. 

  1176. 

  1177. #define PATTERN_TEST	1
    1178. 

  1178. #define SET_READ_TEST	2
    1179. 

  1179. #define WRITE_NO_TEST	3
    1180. 

  1180. #define TABLE32_TEST	4
    1181. 

  1181. #define TABLE64_TEST_LO	5
    1182. 

  1182. #define TABLE64_TEST_HI	6
    1183. 

  1183. 

  1184. /* default 82599 register test */
    1185. 

  1185. static const struct ixgbe_reg_test reg_test_82599[] = {
    1186. 

  1186. 	{ IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
    1187. 

  1187. 	{ IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
    1188. 

  1188. 	{ IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
    1189. 

  1189. 	{ IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
    1190. 

  1190. 	{ IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
    1191. 

  1191. 	{ IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
    1192. 

  1192. 	{ IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
    1193. 

  1193. 	{ IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
    1194. 

  1194. 	{ IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
    1195. 

  1195. 	{ IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
    1196. 

  1196. 	{ IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
    1197. 

  1197. 	{ IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
    1198. 

  1198. 	{ IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
    1199. 

  1199. 	{ IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
    1200. 

  1200. 	{ IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
    1201. 

  1201. 	{ IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
    1202. 

  1202. 	{ IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
    1203. 

  1203. 	{ IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
    1204. 

  1204. 	{ IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
    1205. 

  1205. 	{ 0, 0, 0, 0 }
    1206. 

  1206. };
    1207. 

  1207. 

  1208. /* default 82598 register test */
    1209. 

  1209. static const struct ixgbe_reg_test reg_test_82598[] = {
    1210. 

  1210. 	{ IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
    1211. 

  1211. 	{ IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
    1212. 

  1212. 	{ IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
    1213. 

  1213. 	{ IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
    1214. 

  1214. 	{ IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
    1215. 

  1215. 	{ IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
    1216. 

  1216. 	{ IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
    1217. 

  1217. 	/* Enable all four RX queues before testing. */
    1218. 

  1218. 	{ IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
    1219. 

  1219. 	/* RDH is read-only for 82598, only test RDT. */
    1220. 

  1220. 	{ IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
    1221. 

  1221. 	{ IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
    1222. 

  1222. 	{ IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
    1223. 

  1223. 	{ IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
    1224. 

  1224. 	{ IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
    1225. 

  1225. 	{ IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
    1226. 

  1226. 	{ IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
    1227. 

  1227. 	{ IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
    1228. 

  1228. 	{ IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
    1229. 

  1229. 	{ IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
    1230. 

  1230. 	{ IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
    1231. 

  1231. 	{ IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
    1232. 

  1232. 	{ IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
    1233. 

  1233. 	{ 0, 0, 0, 0 }
    1234. 

  1234. };
    1235. 

  1235. 

  1236. static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg,
    1237. 

  1237. 			     u32 mask, u32 write)
    1238. 

  1238. {
    1239. 

  1239. 	u32 pat, val, before;
    1240. 

  1240. 	static const u32 test_pattern[] = {
    1241. 

  1241. 		0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
    1242. 

  1242. 

  1243. 	for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {
    1244. 

  1244. 		before = readl(adapter->hw.hw_addr + reg);
    1245. 

  1245. 		writel((test_pattern[pat] & write),
    1246. 

  1246. 		       (adapter->hw.hw_addr + reg));
    1247. 

  1247. 		val = readl(adapter->hw.hw_addr + reg);
    1248. 

  1248. 		if (val != (test_pattern[pat] & write & mask)) {
    1249. 

  1249. 			e_err(drv, "pattern test reg %04X failed: got "
    1250. 

  1250. 			      "0x%08X expected 0x%08X\n",
    1251. 

  1251. 			      reg, val, (test_pattern[pat] & write & mask));
    1252. 

  1252. 			*data = reg;
    1253. 

  1253. 			writel(before, adapter->hw.hw_addr + reg);
    1254. 

  1254. 			return 1;
    1255. 

  1255. 		}
    1256. 

  1256. 		writel(before, adapter->hw.hw_addr + reg);
    1257. 

  1257. 	}
    1258. 

  1258. 	return 0;
    1259. 

  1259. }
    1260. 

  1260. 

  1261. static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg,
    1262. 

  1262. 			      u32 mask, u32 write)
    1263. 

  1263. {
    1264. 

  1264. 	u32 val, before;
    1265. 

  1265. 	before = readl(adapter->hw.hw_addr + reg);
    1266. 

  1266. 	writel((write & mask), (adapter->hw.hw_addr + reg));
    1267. 

  1267. 	val = readl(adapter->hw.hw_addr + reg);
    1268. 

  1268. 	if ((write & mask) != (val & mask)) {
    1269. 

  1269. 		e_err(drv, "set/check reg %04X test failed: got 0x%08X "
    1270. 

  1270. 		      "expected 0x%08X\n", reg, (val & mask), (write & mask));
    1271. 

  1271. 		*data = reg;
    1272. 

  1272. 		writel(before, (adapter->hw.hw_addr + reg));
    1273. 

  1273. 		return 1;
    1274. 

  1274. 	}
    1275. 

  1275. 	writel(before, (adapter->hw.hw_addr + reg));
    1276. 

  1276. 	return 0;
    1277. 

  1277. }
    1278. 

  1278. 

  1279. #define REG_PATTERN_TEST(reg, mask, write)				      \
    1280. 

  1280. 	do {								      \
    1281. 

  1281. 		if (reg_pattern_test(adapter, data, reg, mask, write))	      \
    1282. 

  1282. 			return 1;					      \
    1283. 

  1283. 	} while (0)							      \
    1284. 

  1284. 

  1285. 

  1286. #define REG_SET_AND_CHECK(reg, mask, write)				      \
    1287. 

  1287. 	do {								      \
    1288. 

  1288. 		if (reg_set_and_check(adapter, data, reg, mask, write))	      \
    1289. 

  1289. 			return 1;					      \
    1290. 

  1290. 	} while (0)							      \
    1291. 

  1291. 

  1292. static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
    1293. 

  1293. {
    1294. 

  1294. 	const struct ixgbe_reg_test *test;
    1295. 

  1295. 	u32 value, before, after;
    1296. 

  1296. 	u32 i, toggle;
    1297. 

  1297. 

  1298. 	switch (adapter->hw.mac.type) {
    1299. 

  1299. 	case ixgbe_mac_82598EB:
    1300. 

  1300. 		toggle = 0x7FFFF3FF;
    1301. 

  1301. 		test = reg_test_82598;
    1302. 

  1302. 		break;
    1303. 

  1303. 	case ixgbe_mac_82599EB:
    1304. 

  1304. 	case ixgbe_mac_X540:
    1305. 

  1305. 		toggle = 0x7FFFF30F;
    1306. 

  1306. 		test = reg_test_82599;
    1307. 

  1307. 		break;
    1308. 

  1308. 	default:
    1309. 

  1309. 		*data = 1;
    1310. 

  1310. 		return 1;
    1311. 

  1311. 		break;
    1312. 

  1312. 	}
    1313. 

  1313. 

  1314. 	/*
    1315. 

  1315. 	 * Because the status register is such a special case,
    1316. 

  1316. 	 * we handle it separately from the rest of the register
    1317. 

  1317. 	 * tests.  Some bits are read-only, some toggle, and some
    1318. 

  1318. 	 * are writeable on newer MACs.
    1319. 

  1319. 	 */
    1320. 

  1320. 	before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
    1321. 

  1321. 	value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
    1322. 

  1322. 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
    1323. 

  1323. 	after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
    1324. 

  1324. 	if (value != after) {
    1325. 

  1325. 		e_err(drv, "failed STATUS register test got: 0x%08X "
    1326. 

  1326. 		      "expected: 0x%08X\n", after, value);
    1327. 

  1327. 		*data = 1;
    1328. 

  1328. 		return 1;
    1329. 

  1329. 	}
    1330. 

  1330. 	/* restore previous status */
    1331. 

  1331. 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
    1332. 

  1332. 

  1333. 	/*
    1334. 

  1334. 	 * Perform the remainder of the register test, looping through
    1335. 

  1335. 	 * the test table until we either fail or reach the null entry.
    1336. 

  1336. 	 */
    1337. 

  1337. 	while (test->reg) {
    1338. 

  1338. 		for (i = 0; i < test->array_len; i++) {
    1339. 

  1339. 			switch (test->test_type) {
    1340. 

  1340. 			case PATTERN_TEST:
    1341. 

  1341. 				REG_PATTERN_TEST(test->reg + (i * 0x40),
    1342. 

  1342. 						 test->mask,
    1343. 

  1343. 						 test->write);
    1344. 

  1344. 				break;
    1345. 

  1345. 			case SET_READ_TEST:
    1346. 

  1346. 				REG_SET_AND_CHECK(test->reg + (i * 0x40),
    1347. 

  1347. 						  test->mask,
    1348. 

  1348. 						  test->write);
    1349. 

  1349. 				break;
    1350. 

  1350. 			case WRITE_NO_TEST:
    1351. 

  1351. 				writel(test->write,
    1352. 

  1352. 				       (adapter->hw.hw_addr + test->reg)
    1353. 

  1353. 				       + (i * 0x40));
    1354. 

  1354. 				break;
    1355. 

  1355. 			case TABLE32_TEST:
    1356. 

  1356. 				REG_PATTERN_TEST(test->reg + (i * 4),
    1357. 

  1357. 						 test->mask,
    1358. 

  1358. 						 test->write);
    1359. 

  1359. 				break;
    1360. 

  1360. 			case TABLE64_TEST_LO:
    1361. 

  1361. 				REG_PATTERN_TEST(test->reg + (i * 8),
    1362. 

  1362. 						 test->mask,
    1363. 

  1363. 						 test->write);
    1364. 

  1364. 				break;
    1365. 

  1365. 			case TABLE64_TEST_HI:
    1366. 

  1366. 				REG_PATTERN_TEST((test->reg + 4) + (i * 8),
    1367. 

  1367. 						 test->mask,
    1368. 

  1368. 						 test->write);
    1369. 

  1369. 				break;
    1370. 

  1370. 			}
    1371. 

  1371. 		}
    1372. 

  1372. 		test++;
    1373. 

  1373. 	}
    1374. 

  1374. 

  1375. 	*data = 0;
    1376. 

  1376. 	return 0;
    1377. 

  1377. }
    1378. 

  1378. 

  1379. static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
    1380. 

  1380. {
    1381. 

  1381. 	struct ixgbe_hw *hw = &adapter->hw;
    1382. 

  1382. 	if (hw->eeprom.ops.validate_checksum(hw, NULL))
    1383. 

  1383. 		*data = 1;
    1384. 

  1384. 	else
    1385. 

  1385. 		*data = 0;
    1386. 

  1386. 	return *data;
    1387. 

  1387. }
    1388. 

  1388. 

  1389. static irqreturn_t ixgbe_test_intr(int irq, void *data)
    1390. 

  1390. {
    1391. 

  1391. 	struct net_device *netdev = (struct net_device *) data;
    1392. 

  1392. 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
    1393. 

  1393. 

  1394. 	adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
    1395. 

  1395. 

  1396. 	return IRQ_HANDLED;
    1397. 

  1397. }
    1398. 

  1398. 

  1399. static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
    1400. 

  1400. {
    1401. 

  1401. 	struct net_device *netdev = adapter->netdev;
    1402. 

  1402. 	u32 mask, i = 0, shared_int = true;
    1403. 

  1403. 	u32 irq = adapter->pdev->irq;
    1404. 

  1404. 

  1405. 	*data = 0;
    1406. 

  1406. 

  1407. 	/* Hook up test interrupt handler just for this test */
    1408. 

  1408. 	if (adapter->msix_entries) {
    1409. 

  1409. 		/* NOTE: we don't test MSI-X interrupts here, yet */
    1410. 

  1410. 		return 0;
    1411. 

  1411. 	} else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
    1412. 

  1412. 		shared_int = false;
    1413. 

  1413. 		if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
    1414. 

  1414. 				netdev)) {
    1415. 

  1415. 			*data = 1;
    1416. 

  1416. 			return -1;
    1417. 

  1417. 		}
    1418. 

  1418. 	} else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
    1419. 

  1419. 	                        netdev->name, netdev)) {
    1420. 

  1420. 		shared_int = false;
    1421. 

  1421. 	} else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
    1422. 

  1422. 	                       netdev->name, netdev)) {
    1423. 

  1423. 		*data = 1;
    1424. 

  1424. 		return -1;
    1425. 

  1425. 	}
    1426. 

  1426. 	e_info(hw, "testing %s interrupt\n", shared_int ?
    1427. 

  1427. 	       "shared" : "unshared");
    1428. 

  1428. 

  1429. 	/* Disable all the interrupts */
    1430. 

  1430. 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
    1431. 

  1431. 	IXGBE_WRITE_FLUSH(&adapter->hw);
    1432. 

  1432. 	usleep_range(10000, 20000);
    1433. 

  1433. 

  1434. 	/* Test each interrupt */
    1435. 

  1435. 	for (; i < 10; i++) {
    1436. 

  1436. 		/* Interrupt to test */
    1437. 

  1437. 		mask = 1 << i;
    1438. 

  1438. 

  1439. 		if (!shared_int) {
    1440. 

  1440. 			/*
    1441. 

  1441. 			 * Disable the interrupts to be reported in
    1442. 

  1442. 			 * the cause register and then force the same
    1443. 

  1443. 			 * interrupt and see if one gets posted.  If
    1444. 

  1444. 			 * an interrupt was posted to the bus, the
    1445. 

  1445. 			 * test failed.
    1446. 

  1446. 			 */
    1447. 

  1447. 			adapter->test_icr = 0;
    1448. 

  1448. 			IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
    1449. 

  1449. 			                ~mask & 0x00007FFF);
    1450. 

  1450. 			IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
    1451. 

  1451. 			                ~mask & 0x00007FFF);
    1452. 

  1452. 			IXGBE_WRITE_FLUSH(&adapter->hw);
    1453. 

  1453. 			usleep_range(10000, 20000);
    1454. 

  1454. 

  1455. 			if (adapter->test_icr & mask) {
    1456. 

  1456. 				*data = 3;
    1457. 

  1457. 				break;
    1458. 

  1458. 			}
    1459. 

  1459. 		}
    1460. 

  1460. 

  1461. 		/*
    1462. 

  1462. 		 * Enable the interrupt to be reported in the cause
    1463. 

  1463. 		 * register and then force the same interrupt and see
    1464. 

  1464. 		 * if one gets posted.  If an interrupt was not posted
    1465. 

  1465. 		 * to the bus, the test failed.
    1466. 

  1466. 		 */
    1467. 

  1467. 		adapter->test_icr = 0;
    1468. 

  1468. 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
    1469. 

  1469. 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
    1470. 

  1470. 		IXGBE_WRITE_FLUSH(&adapter->hw);
    1471. 

  1471. 		usleep_range(10000, 20000);
    1472. 

  1472. 

  1473. 		if (!(adapter->test_icr &mask)) {
    1474. 

  1474. 			*data = 4;
    1475. 

  1475. 			break;
    1476. 

  1476. 		}
    1477. 

  1477. 

  1478. 		if (!shared_int) {
    1479. 

  1479. 			/*
    1480. 

  1480. 			 * Disable the other interrupts to be reported in
    1481. 

  1481. 			 * the cause register and then force the other
    1482. 

  1482. 			 * interrupts and see if any get posted.  If
    1483. 

  1483. 			 * an interrupt was posted to the bus, the
    1484. 

  1484. 			 * test failed.
    1485. 

  1485. 			 */
    1486. 

  1486. 			adapter->test_icr = 0;
    1487. 

  1487. 			IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
    1488. 

  1488. 			                ~mask & 0x00007FFF);
    1489. 

  1489. 			IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
    1490. 

  1490. 			                ~mask & 0x00007FFF);
    1491. 

  1491. 			IXGBE_WRITE_FLUSH(&adapter->hw);
    1492. 

  1492. 			usleep_range(10000, 20000);
    1493. 

  1493. 

  1494. 			if (adapter->test_icr) {
    1495. 

  1495. 				*data = 5;
    1496. 

  1496. 				break;
    1497. 

  1497. 			}
    1498. 

  1498. 		}
    1499. 

  1499. 	}
    1500. 

  1500. 

  1501. 	/* Disable all the interrupts */
    1502. 

  1502. 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
    1503. 

  1503. 	IXGBE_WRITE_FLUSH(&adapter->hw);
    1504. 

  1504. 	usleep_range(10000, 20000);
    1505. 

  1505. 

  1506. 	/* Unhook test interrupt handler */
    1507. 

  1507. 	free_irq(irq, netdev);
    1508. 

  1508. 

  1509. 	return *data;
    1510. 

  1510. }
    1511. 

  1511. 

  1512. static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
    1513. 

  1513. {
    1514. 

  1514. 	struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
    1515. 

  1515. 	struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
    1516. 

  1516. 	struct ixgbe_hw *hw = &adapter->hw;
    1517. 

  1517. 	u32 reg_ctl;
    1518. 

  1518. 

  1519. 	/* shut down the DMA engines now so they can be reinitialized later */
    1520. 

  1520. 

  1521. 	/* first Rx */
    1522. 

  1522. 	reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
    1523. 

  1523. 	reg_ctl &= ~IXGBE_RXCTRL_RXEN;
    1524. 

  1524. 	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
    1525. 

  1525. 	ixgbe_disable_rx_queue(adapter, rx_ring);
    1526. 

  1526. 

  1527. 	/* now Tx */
    1528. 

  1528. 	reg_ctl = IXGBE_RE…
    1529.

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