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/drivers/gpu/drm/i915/i915_irq.c

https://bitbucket.org/digetx/picasso-kernel
C | 2775 lines | 2007 code | 491 blank | 277 comment | 343 complexity | 32a4a86ef09027a5b54f6bdceb024da0 MD5 | raw file
Possible License(s): AGPL-1.0, GPL-2.0, LGPL-2.0

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  1. /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
  2. */
  3. /*
  4. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  5. * All Rights Reserved.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the
  9. * "Software"), to deal in the Software without restriction, including
  10. * without limitation the rights to use, copy, modify, merge, publish,
  11. * distribute, sub license, and/or sell copies of the Software, and to
  12. * permit persons to whom the Software is furnished to do so, subject to
  13. * the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the
  16. * next paragraph) shall be included in all copies or substantial portions
  17. * of the Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26. *
  27. */
  28. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  29. #include <linux/sysrq.h>
  30. #include <linux/slab.h>
  31. #include <drm/drmP.h>
  32. #include <drm/i915_drm.h>
  33. #include "i915_drv.h"
  34. #include "i915_trace.h"
  35. #include "intel_drv.h"
  36. /* For display hotplug interrupt */
  37. static void
  38. ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  39. {
  40. if ((dev_priv->irq_mask & mask) != 0) {
  41. dev_priv->irq_mask &= ~mask;
  42. I915_WRITE(DEIMR, dev_priv->irq_mask);
  43. POSTING_READ(DEIMR);
  44. }
  45. }
  46. static inline void
  47. ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  48. {
  49. if ((dev_priv->irq_mask & mask) != mask) {
  50. dev_priv->irq_mask |= mask;
  51. I915_WRITE(DEIMR, dev_priv->irq_mask);
  52. POSTING_READ(DEIMR);
  53. }
  54. }
  55. void
  56. i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  57. {
  58. if ((dev_priv->pipestat[pipe] & mask) != mask) {
  59. u32 reg = PIPESTAT(pipe);
  60. dev_priv->pipestat[pipe] |= mask;
  61. /* Enable the interrupt, clear any pending status */
  62. I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  63. POSTING_READ(reg);
  64. }
  65. }
  66. void
  67. i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  68. {
  69. if ((dev_priv->pipestat[pipe] & mask) != 0) {
  70. u32 reg = PIPESTAT(pipe);
  71. dev_priv->pipestat[pipe] &= ~mask;
  72. I915_WRITE(reg, dev_priv->pipestat[pipe]);
  73. POSTING_READ(reg);
  74. }
  75. }
  76. /**
  77. * intel_enable_asle - enable ASLE interrupt for OpRegion
  78. */
  79. void intel_enable_asle(struct drm_device *dev)
  80. {
  81. drm_i915_private_t *dev_priv = dev->dev_private;
  82. unsigned long irqflags;
  83. /* FIXME: opregion/asle for VLV */
  84. if (IS_VALLEYVIEW(dev))
  85. return;
  86. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  87. if (HAS_PCH_SPLIT(dev))
  88. ironlake_enable_display_irq(dev_priv, DE_GSE);
  89. else {
  90. i915_enable_pipestat(dev_priv, 1,
  91. PIPE_LEGACY_BLC_EVENT_ENABLE);
  92. if (INTEL_INFO(dev)->gen >= 4)
  93. i915_enable_pipestat(dev_priv, 0,
  94. PIPE_LEGACY_BLC_EVENT_ENABLE);
  95. }
  96. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  97. }
  98. /**
  99. * i915_pipe_enabled - check if a pipe is enabled
  100. * @dev: DRM device
  101. * @pipe: pipe to check
  102. *
  103. * Reading certain registers when the pipe is disabled can hang the chip.
  104. * Use this routine to make sure the PLL is running and the pipe is active
  105. * before reading such registers if unsure.
  106. */
  107. static int
  108. i915_pipe_enabled(struct drm_device *dev, int pipe)
  109. {
  110. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  111. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  112. pipe);
  113. return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
  114. }
  115. /* Called from drm generic code, passed a 'crtc', which
  116. * we use as a pipe index
  117. */
  118. static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
  119. {
  120. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  121. unsigned long high_frame;
  122. unsigned long low_frame;
  123. u32 high1, high2, low;
  124. if (!i915_pipe_enabled(dev, pipe)) {
  125. DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
  126. "pipe %c\n", pipe_name(pipe));
  127. return 0;
  128. }
  129. high_frame = PIPEFRAME(pipe);
  130. low_frame = PIPEFRAMEPIXEL(pipe);
  131. /*
  132. * High & low register fields aren't synchronized, so make sure
  133. * we get a low value that's stable across two reads of the high
  134. * register.
  135. */
  136. do {
  137. high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
  138. low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
  139. high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
  140. } while (high1 != high2);
  141. high1 >>= PIPE_FRAME_HIGH_SHIFT;
  142. low >>= PIPE_FRAME_LOW_SHIFT;
  143. return (high1 << 8) | low;
  144. }
  145. static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
  146. {
  147. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  148. int reg = PIPE_FRMCOUNT_GM45(pipe);
  149. if (!i915_pipe_enabled(dev, pipe)) {
  150. DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
  151. "pipe %c\n", pipe_name(pipe));
  152. return 0;
  153. }
  154. return I915_READ(reg);
  155. }
  156. static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
  157. int *vpos, int *hpos)
  158. {
  159. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  160. u32 vbl = 0, position = 0;
  161. int vbl_start, vbl_end, htotal, vtotal;
  162. bool in_vbl = true;
  163. int ret = 0;
  164. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  165. pipe);
  166. if (!i915_pipe_enabled(dev, pipe)) {
  167. DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
  168. "pipe %c\n", pipe_name(pipe));
  169. return 0;
  170. }
  171. /* Get vtotal. */
  172. vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
  173. if (INTEL_INFO(dev)->gen >= 4) {
  174. /* No obvious pixelcount register. Only query vertical
  175. * scanout position from Display scan line register.
  176. */
  177. position = I915_READ(PIPEDSL(pipe));
  178. /* Decode into vertical scanout position. Don't have
  179. * horizontal scanout position.
  180. */
  181. *vpos = position & 0x1fff;
  182. *hpos = 0;
  183. } else {
  184. /* Have access to pixelcount since start of frame.
  185. * We can split this into vertical and horizontal
  186. * scanout position.
  187. */
  188. position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
  189. htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
  190. *vpos = position / htotal;
  191. *hpos = position - (*vpos * htotal);
  192. }
  193. /* Query vblank area. */
  194. vbl = I915_READ(VBLANK(cpu_transcoder));
  195. /* Test position against vblank region. */
  196. vbl_start = vbl & 0x1fff;
  197. vbl_end = (vbl >> 16) & 0x1fff;
  198. if ((*vpos < vbl_start) || (*vpos > vbl_end))
  199. in_vbl = false;
  200. /* Inside "upper part" of vblank area? Apply corrective offset: */
  201. if (in_vbl && (*vpos >= vbl_start))
  202. *vpos = *vpos - vtotal;
  203. /* Readouts valid? */
  204. if (vbl > 0)
  205. ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
  206. /* In vblank? */
  207. if (in_vbl)
  208. ret |= DRM_SCANOUTPOS_INVBL;
  209. return ret;
  210. }
  211. static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
  212. int *max_error,
  213. struct timeval *vblank_time,
  214. unsigned flags)
  215. {
  216. struct drm_crtc *crtc;
  217. if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
  218. DRM_ERROR("Invalid crtc %d\n", pipe);
  219. return -EINVAL;
  220. }
  221. /* Get drm_crtc to timestamp: */
  222. crtc = intel_get_crtc_for_pipe(dev, pipe);
  223. if (crtc == NULL) {
  224. DRM_ERROR("Invalid crtc %d\n", pipe);
  225. return -EINVAL;
  226. }
  227. if (!crtc->enabled) {
  228. DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
  229. return -EBUSY;
  230. }
  231. /* Helper routine in DRM core does all the work: */
  232. return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
  233. vblank_time, flags,
  234. crtc);
  235. }
  236. /*
  237. * Handle hotplug events outside the interrupt handler proper.
  238. */
  239. static void i915_hotplug_work_func(struct work_struct *work)
  240. {
  241. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  242. hotplug_work);
  243. struct drm_device *dev = dev_priv->dev;
  244. struct drm_mode_config *mode_config = &dev->mode_config;
  245. struct intel_encoder *encoder;
  246. mutex_lock(&mode_config->mutex);
  247. DRM_DEBUG_KMS("running encoder hotplug functions\n");
  248. list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
  249. if (encoder->hot_plug)
  250. encoder->hot_plug(encoder);
  251. mutex_unlock(&mode_config->mutex);
  252. /* Just fire off a uevent and let userspace tell us what to do */
  253. drm_helper_hpd_irq_event(dev);
  254. }
  255. /* defined intel_pm.c */
  256. extern spinlock_t mchdev_lock;
  257. static void ironlake_handle_rps_change(struct drm_device *dev)
  258. {
  259. drm_i915_private_t *dev_priv = dev->dev_private;
  260. u32 busy_up, busy_down, max_avg, min_avg;
  261. u8 new_delay;
  262. unsigned long flags;
  263. spin_lock_irqsave(&mchdev_lock, flags);
  264. I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
  265. new_delay = dev_priv->ips.cur_delay;
  266. I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
  267. busy_up = I915_READ(RCPREVBSYTUPAVG);
  268. busy_down = I915_READ(RCPREVBSYTDNAVG);
  269. max_avg = I915_READ(RCBMAXAVG);
  270. min_avg = I915_READ(RCBMINAVG);
  271. /* Handle RCS change request from hw */
  272. if (busy_up > max_avg) {
  273. if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
  274. new_delay = dev_priv->ips.cur_delay - 1;
  275. if (new_delay < dev_priv->ips.max_delay)
  276. new_delay = dev_priv->ips.max_delay;
  277. } else if (busy_down < min_avg) {
  278. if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
  279. new_delay = dev_priv->ips.cur_delay + 1;
  280. if (new_delay > dev_priv->ips.min_delay)
  281. new_delay = dev_priv->ips.min_delay;
  282. }
  283. if (ironlake_set_drps(dev, new_delay))
  284. dev_priv->ips.cur_delay = new_delay;
  285. spin_unlock_irqrestore(&mchdev_lock, flags);
  286. return;
  287. }
  288. static void notify_ring(struct drm_device *dev,
  289. struct intel_ring_buffer *ring)
  290. {
  291. struct drm_i915_private *dev_priv = dev->dev_private;
  292. if (ring->obj == NULL)
  293. return;
  294. trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
  295. wake_up_all(&ring->irq_queue);
  296. if (i915_enable_hangcheck) {
  297. dev_priv->hangcheck_count = 0;
  298. mod_timer(&dev_priv->hangcheck_timer,
  299. round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
  300. }
  301. }
  302. static void gen6_pm_rps_work(struct work_struct *work)
  303. {
  304. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  305. rps.work);
  306. u32 pm_iir, pm_imr;
  307. u8 new_delay;
  308. spin_lock_irq(&dev_priv->rps.lock);
  309. pm_iir = dev_priv->rps.pm_iir;
  310. dev_priv->rps.pm_iir = 0;
  311. pm_imr = I915_READ(GEN6_PMIMR);
  312. I915_WRITE(GEN6_PMIMR, 0);
  313. spin_unlock_irq(&dev_priv->rps.lock);
  314. if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
  315. return;
  316. mutex_lock(&dev_priv->rps.hw_lock);
  317. if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
  318. new_delay = dev_priv->rps.cur_delay + 1;
  319. else
  320. new_delay = dev_priv->rps.cur_delay - 1;
  321. /* sysfs frequency interfaces may have snuck in while servicing the
  322. * interrupt
  323. */
  324. if (!(new_delay > dev_priv->rps.max_delay ||
  325. new_delay < dev_priv->rps.min_delay)) {
  326. gen6_set_rps(dev_priv->dev, new_delay);
  327. }
  328. mutex_unlock(&dev_priv->rps.hw_lock);
  329. }
  330. /**
  331. * ivybridge_parity_work - Workqueue called when a parity error interrupt
  332. * occurred.
  333. * @work: workqueue struct
  334. *
  335. * Doesn't actually do anything except notify userspace. As a consequence of
  336. * this event, userspace should try to remap the bad rows since statistically
  337. * it is likely the same row is more likely to go bad again.
  338. */
  339. static void ivybridge_parity_work(struct work_struct *work)
  340. {
  341. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  342. l3_parity.error_work);
  343. u32 error_status, row, bank, subbank;
  344. char *parity_event[5];
  345. uint32_t misccpctl;
  346. unsigned long flags;
  347. /* We must turn off DOP level clock gating to access the L3 registers.
  348. * In order to prevent a get/put style interface, acquire struct mutex
  349. * any time we access those registers.
  350. */
  351. mutex_lock(&dev_priv->dev->struct_mutex);
  352. misccpctl = I915_READ(GEN7_MISCCPCTL);
  353. I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
  354. POSTING_READ(GEN7_MISCCPCTL);
  355. error_status = I915_READ(GEN7_L3CDERRST1);
  356. row = GEN7_PARITY_ERROR_ROW(error_status);
  357. bank = GEN7_PARITY_ERROR_BANK(error_status);
  358. subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
  359. I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
  360. GEN7_L3CDERRST1_ENABLE);
  361. POSTING_READ(GEN7_L3CDERRST1);
  362. I915_WRITE(GEN7_MISCCPCTL, misccpctl);
  363. spin_lock_irqsave(&dev_priv->irq_lock, flags);
  364. dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
  365. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  366. spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
  367. mutex_unlock(&dev_priv->dev->struct_mutex);
  368. parity_event[0] = "L3_PARITY_ERROR=1";
  369. parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
  370. parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
  371. parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
  372. parity_event[4] = NULL;
  373. kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
  374. KOBJ_CHANGE, parity_event);
  375. DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
  376. row, bank, subbank);
  377. kfree(parity_event[3]);
  378. kfree(parity_event[2]);
  379. kfree(parity_event[1]);
  380. }
  381. static void ivybridge_handle_parity_error(struct drm_device *dev)
  382. {
  383. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  384. unsigned long flags;
  385. if (!HAS_L3_GPU_CACHE(dev))
  386. return;
  387. spin_lock_irqsave(&dev_priv->irq_lock, flags);
  388. dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
  389. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  390. spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
  391. queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
  392. }
  393. static void snb_gt_irq_handler(struct drm_device *dev,
  394. struct drm_i915_private *dev_priv,
  395. u32 gt_iir)
  396. {
  397. if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
  398. GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
  399. notify_ring(dev, &dev_priv->ring[RCS]);
  400. if (gt_iir & GEN6_BSD_USER_INTERRUPT)
  401. notify_ring(dev, &dev_priv->ring[VCS]);
  402. if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
  403. notify_ring(dev, &dev_priv->ring[BCS]);
  404. if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
  405. GT_GEN6_BSD_CS_ERROR_INTERRUPT |
  406. GT_RENDER_CS_ERROR_INTERRUPT)) {
  407. DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
  408. i915_handle_error(dev, false);
  409. }
  410. if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
  411. ivybridge_handle_parity_error(dev);
  412. }
  413. static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
  414. u32 pm_iir)
  415. {
  416. unsigned long flags;
  417. /*
  418. * IIR bits should never already be set because IMR should
  419. * prevent an interrupt from being shown in IIR. The warning
  420. * displays a case where we've unsafely cleared
  421. * dev_priv->rps.pm_iir. Although missing an interrupt of the same
  422. * type is not a problem, it displays a problem in the logic.
  423. *
  424. * The mask bit in IMR is cleared by dev_priv->rps.work.
  425. */
  426. spin_lock_irqsave(&dev_priv->rps.lock, flags);
  427. dev_priv->rps.pm_iir |= pm_iir;
  428. I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
  429. POSTING_READ(GEN6_PMIMR);
  430. spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
  431. queue_work(dev_priv->wq, &dev_priv->rps.work);
  432. }
  433. static irqreturn_t valleyview_irq_handler(int irq, void *arg)
  434. {
  435. struct drm_device *dev = (struct drm_device *) arg;
  436. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  437. u32 iir, gt_iir, pm_iir;
  438. irqreturn_t ret = IRQ_NONE;
  439. unsigned long irqflags;
  440. int pipe;
  441. u32 pipe_stats[I915_MAX_PIPES];
  442. bool blc_event;
  443. atomic_inc(&dev_priv->irq_received);
  444. while (true) {
  445. iir = I915_READ(VLV_IIR);
  446. gt_iir = I915_READ(GTIIR);
  447. pm_iir = I915_READ(GEN6_PMIIR);
  448. if (gt_iir == 0 && pm_iir == 0 && iir == 0)
  449. goto out;
  450. ret = IRQ_HANDLED;
  451. snb_gt_irq_handler(dev, dev_priv, gt_iir);
  452. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  453. for_each_pipe(pipe) {
  454. int reg = PIPESTAT(pipe);
  455. pipe_stats[pipe] = I915_READ(reg);
  456. /*
  457. * Clear the PIPE*STAT regs before the IIR
  458. */
  459. if (pipe_stats[pipe] & 0x8000ffff) {
  460. if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  461. DRM_DEBUG_DRIVER("pipe %c underrun\n",
  462. pipe_name(pipe));
  463. I915_WRITE(reg, pipe_stats[pipe]);
  464. }
  465. }
  466. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  467. for_each_pipe(pipe) {
  468. if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
  469. drm_handle_vblank(dev, pipe);
  470. if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
  471. intel_prepare_page_flip(dev, pipe);
  472. intel_finish_page_flip(dev, pipe);
  473. }
  474. }
  475. /* Consume port. Then clear IIR or we'll miss events */
  476. if (iir & I915_DISPLAY_PORT_INTERRUPT) {
  477. u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
  478. DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
  479. hotplug_status);
  480. if (hotplug_status & dev_priv->hotplug_supported_mask)
  481. queue_work(dev_priv->wq,
  482. &dev_priv->hotplug_work);
  483. I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
  484. I915_READ(PORT_HOTPLUG_STAT);
  485. }
  486. if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
  487. blc_event = true;
  488. if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
  489. gen6_queue_rps_work(dev_priv, pm_iir);
  490. I915_WRITE(GTIIR, gt_iir);
  491. I915_WRITE(GEN6_PMIIR, pm_iir);
  492. I915_WRITE(VLV_IIR, iir);
  493. }
  494. out:
  495. return ret;
  496. }
  497. static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
  498. {
  499. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  500. int pipe;
  501. if (pch_iir & SDE_HOTPLUG_MASK)
  502. queue_work(dev_priv->wq, &dev_priv->hotplug_work);
  503. if (pch_iir & SDE_AUDIO_POWER_MASK)
  504. DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
  505. (pch_iir & SDE_AUDIO_POWER_MASK) >>
  506. SDE_AUDIO_POWER_SHIFT);
  507. if (pch_iir & SDE_GMBUS)
  508. DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
  509. if (pch_iir & SDE_AUDIO_HDCP_MASK)
  510. DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
  511. if (pch_iir & SDE_AUDIO_TRANS_MASK)
  512. DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
  513. if (pch_iir & SDE_POISON)
  514. DRM_ERROR("PCH poison interrupt\n");
  515. if (pch_iir & SDE_FDI_MASK)
  516. for_each_pipe(pipe)
  517. DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
  518. pipe_name(pipe),
  519. I915_READ(FDI_RX_IIR(pipe)));
  520. if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
  521. DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
  522. if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
  523. DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
  524. if (pch_iir & SDE_TRANSB_FIFO_UNDER)
  525. DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
  526. if (pch_iir & SDE_TRANSA_FIFO_UNDER)
  527. DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
  528. }
  529. static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
  530. {
  531. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  532. int pipe;
  533. if (pch_iir & SDE_HOTPLUG_MASK_CPT)
  534. queue_work(dev_priv->wq, &dev_priv->hotplug_work);
  535. if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
  536. DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
  537. (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
  538. SDE_AUDIO_POWER_SHIFT_CPT);
  539. if (pch_iir & SDE_AUX_MASK_CPT)
  540. DRM_DEBUG_DRIVER("AUX channel interrupt\n");
  541. if (pch_iir & SDE_GMBUS_CPT)
  542. DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
  543. if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
  544. DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
  545. if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
  546. DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
  547. if (pch_iir & SDE_FDI_MASK_CPT)
  548. for_each_pipe(pipe)
  549. DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
  550. pipe_name(pipe),
  551. I915_READ(FDI_RX_IIR(pipe)));
  552. }
  553. static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
  554. {
  555. struct drm_device *dev = (struct drm_device *) arg;
  556. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  557. u32 de_iir, gt_iir, de_ier, pm_iir;
  558. irqreturn_t ret = IRQ_NONE;
  559. int i;
  560. atomic_inc(&dev_priv->irq_received);
  561. /* disable master interrupt before clearing iir */
  562. de_ier = I915_READ(DEIER);
  563. I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
  564. gt_iir = I915_READ(GTIIR);
  565. if (gt_iir) {
  566. snb_gt_irq_handler(dev, dev_priv, gt_iir);
  567. I915_WRITE(GTIIR, gt_iir);
  568. ret = IRQ_HANDLED;
  569. }
  570. de_iir = I915_READ(DEIIR);
  571. if (de_iir) {
  572. if (de_iir & DE_GSE_IVB)
  573. intel_opregion_gse_intr(dev);
  574. for (i = 0; i < 3; i++) {
  575. if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
  576. drm_handle_vblank(dev, i);
  577. if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
  578. intel_prepare_page_flip(dev, i);
  579. intel_finish_page_flip_plane(dev, i);
  580. }
  581. }
  582. /* check event from PCH */
  583. if (de_iir & DE_PCH_EVENT_IVB) {
  584. u32 pch_iir = I915_READ(SDEIIR);
  585. cpt_irq_handler(dev, pch_iir);
  586. /* clear PCH hotplug event before clear CPU irq */
  587. I915_WRITE(SDEIIR, pch_iir);
  588. }
  589. I915_WRITE(DEIIR, de_iir);
  590. ret = IRQ_HANDLED;
  591. }
  592. pm_iir = I915_READ(GEN6_PMIIR);
  593. if (pm_iir) {
  594. if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
  595. gen6_queue_rps_work(dev_priv, pm_iir);
  596. I915_WRITE(GEN6_PMIIR, pm_iir);
  597. ret = IRQ_HANDLED;
  598. }
  599. I915_WRITE(DEIER, de_ier);
  600. POSTING_READ(DEIER);
  601. return ret;
  602. }
  603. static void ilk_gt_irq_handler(struct drm_device *dev,
  604. struct drm_i915_private *dev_priv,
  605. u32 gt_iir)
  606. {
  607. if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
  608. notify_ring(dev, &dev_priv->ring[RCS]);
  609. if (gt_iir & GT_BSD_USER_INTERRUPT)
  610. notify_ring(dev, &dev_priv->ring[VCS]);
  611. }
  612. static irqreturn_t ironlake_irq_handler(int irq, void *arg)
  613. {
  614. struct drm_device *dev = (struct drm_device *) arg;
  615. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  616. int ret = IRQ_NONE;
  617. u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
  618. atomic_inc(&dev_priv->irq_received);
  619. /* disable master interrupt before clearing iir */
  620. de_ier = I915_READ(DEIER);
  621. I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
  622. POSTING_READ(DEIER);
  623. de_iir = I915_READ(DEIIR);
  624. gt_iir = I915_READ(GTIIR);
  625. pch_iir = I915_READ(SDEIIR);
  626. pm_iir = I915_READ(GEN6_PMIIR);
  627. if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
  628. (!IS_GEN6(dev) || pm_iir == 0))
  629. goto done;
  630. ret = IRQ_HANDLED;
  631. if (IS_GEN5(dev))
  632. ilk_gt_irq_handler(dev, dev_priv, gt_iir);
  633. else
  634. snb_gt_irq_handler(dev, dev_priv, gt_iir);
  635. if (de_iir & DE_GSE)
  636. intel_opregion_gse_intr(dev);
  637. if (de_iir & DE_PIPEA_VBLANK)
  638. drm_handle_vblank(dev, 0);
  639. if (de_iir & DE_PIPEB_VBLANK)
  640. drm_handle_vblank(dev, 1);
  641. if (de_iir & DE_PLANEA_FLIP_DONE) {
  642. intel_prepare_page_flip(dev, 0);
  643. intel_finish_page_flip_plane(dev, 0);
  644. }
  645. if (de_iir & DE_PLANEB_FLIP_DONE) {
  646. intel_prepare_page_flip(dev, 1);
  647. intel_finish_page_flip_plane(dev, 1);
  648. }
  649. /* check event from PCH */
  650. if (de_iir & DE_PCH_EVENT) {
  651. if (HAS_PCH_CPT(dev))
  652. cpt_irq_handler(dev, pch_iir);
  653. else
  654. ibx_irq_handler(dev, pch_iir);
  655. }
  656. if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
  657. ironlake_handle_rps_change(dev);
  658. if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
  659. gen6_queue_rps_work(dev_priv, pm_iir);
  660. /* should clear PCH hotplug event before clear CPU irq */
  661. I915_WRITE(SDEIIR, pch_iir);
  662. I915_WRITE(GTIIR, gt_iir);
  663. I915_WRITE(DEIIR, de_iir);
  664. I915_WRITE(GEN6_PMIIR, pm_iir);
  665. done:
  666. I915_WRITE(DEIER, de_ier);
  667. POSTING_READ(DEIER);
  668. return ret;
  669. }
  670. /**
  671. * i915_error_work_func - do process context error handling work
  672. * @work: work struct
  673. *
  674. * Fire an error uevent so userspace can see that a hang or error
  675. * was detected.
  676. */
  677. static void i915_error_work_func(struct work_struct *work)
  678. {
  679. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  680. error_work);
  681. struct drm_device *dev = dev_priv->dev;
  682. char *error_event[] = { "ERROR=1", NULL };
  683. char *reset_event[] = { "RESET=1", NULL };
  684. char *reset_done_event[] = { "ERROR=0", NULL };
  685. kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
  686. if (atomic_read(&dev_priv->mm.wedged)) {
  687. DRM_DEBUG_DRIVER("resetting chip\n");
  688. kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
  689. if (!i915_reset(dev)) {
  690. atomic_set(&dev_priv->mm.wedged, 0);
  691. kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
  692. }
  693. complete_all(&dev_priv->error_completion);
  694. }
  695. }
  696. /* NB: please notice the memset */
  697. static void i915_get_extra_instdone(struct drm_device *dev,
  698. uint32_t *instdone)
  699. {
  700. struct drm_i915_private *dev_priv = dev->dev_private;
  701. memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
  702. switch(INTEL_INFO(dev)->gen) {
  703. case 2:
  704. case 3:
  705. instdone[0] = I915_READ(INSTDONE);
  706. break;
  707. case 4:
  708. case 5:
  709. case 6:
  710. instdone[0] = I915_READ(INSTDONE_I965);
  711. instdone[1] = I915_READ(INSTDONE1);
  712. break;
  713. default:
  714. WARN_ONCE(1, "Unsupported platform\n");
  715. case 7:
  716. instdone[0] = I915_READ(GEN7_INSTDONE_1);
  717. instdone[1] = I915_READ(GEN7_SC_INSTDONE);
  718. instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
  719. instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
  720. break;
  721. }
  722. }
  723. #ifdef CONFIG_DEBUG_FS
  724. static struct drm_i915_error_object *
  725. i915_error_object_create(struct drm_i915_private *dev_priv,
  726. struct drm_i915_gem_object *src)
  727. {
  728. struct drm_i915_error_object *dst;
  729. int i, count;
  730. u32 reloc_offset;
  731. if (src == NULL || src->pages == NULL)
  732. return NULL;
  733. count = src->base.size / PAGE_SIZE;
  734. dst = kmalloc(sizeof(*dst) + count * sizeof(u32 *), GFP_ATOMIC);
  735. if (dst == NULL)
  736. return NULL;
  737. reloc_offset = src->gtt_offset;
  738. for (i = 0; i < count; i++) {
  739. unsigned long flags;
  740. void *d;
  741. d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
  742. if (d == NULL)
  743. goto unwind;
  744. local_irq_save(flags);
  745. if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
  746. src->has_global_gtt_mapping) {
  747. void __iomem *s;
  748. /* Simply ignore tiling or any overlapping fence.
  749. * It's part of the error state, and this hopefully
  750. * captures what the GPU read.
  751. */
  752. s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
  753. reloc_offset);
  754. memcpy_fromio(d, s, PAGE_SIZE);
  755. io_mapping_unmap_atomic(s);
  756. } else {
  757. struct page *page;
  758. void *s;
  759. page = i915_gem_object_get_page(src, i);
  760. drm_clflush_pages(&page, 1);
  761. s = kmap_atomic(page);
  762. memcpy(d, s, PAGE_SIZE);
  763. kunmap_atomic(s);
  764. drm_clflush_pages(&page, 1);
  765. }
  766. local_irq_restore(flags);
  767. dst->pages[i] = d;
  768. reloc_offset += PAGE_SIZE;
  769. }
  770. dst->page_count = count;
  771. dst->gtt_offset = src->gtt_offset;
  772. return dst;
  773. unwind:
  774. while (i--)
  775. kfree(dst->pages[i]);
  776. kfree(dst);
  777. return NULL;
  778. }
  779. static void
  780. i915_error_object_free(struct drm_i915_error_object *obj)
  781. {
  782. int page;
  783. if (obj == NULL)
  784. return;
  785. for (page = 0; page < obj->page_count; page++)
  786. kfree(obj->pages[page]);
  787. kfree(obj);
  788. }
  789. void
  790. i915_error_state_free(struct kref *error_ref)
  791. {
  792. struct drm_i915_error_state *error = container_of(error_ref,
  793. typeof(*error), ref);
  794. int i;
  795. for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
  796. i915_error_object_free(error->ring[i].batchbuffer);
  797. i915_error_object_free(error->ring[i].ringbuffer);
  798. kfree(error->ring[i].requests);
  799. }
  800. kfree(error->active_bo);
  801. kfree(error->overlay);
  802. kfree(error);
  803. }
  804. static void capture_bo(struct drm_i915_error_buffer *err,
  805. struct drm_i915_gem_object *obj)
  806. {
  807. err->size = obj->base.size;
  808. err->name = obj->base.name;
  809. err->rseqno = obj->last_read_seqno;
  810. err->wseqno = obj->last_write_seqno;
  811. err->gtt_offset = obj->gtt_offset;
  812. err->read_domains = obj->base.read_domains;
  813. err->write_domain = obj->base.write_domain;
  814. err->fence_reg = obj->fence_reg;
  815. err->pinned = 0;
  816. if (obj->pin_count > 0)
  817. err->pinned = 1;
  818. if (obj->user_pin_count > 0)
  819. err->pinned = -1;
  820. err->tiling = obj->tiling_mode;
  821. err->dirty = obj->dirty;
  822. err->purgeable = obj->madv != I915_MADV_WILLNEED;
  823. err->ring = obj->ring ? obj->ring->id : -1;
  824. err->cache_level = obj->cache_level;
  825. }
  826. static u32 capture_active_bo(struct drm_i915_error_buffer *err,
  827. int count, struct list_head *head)
  828. {
  829. struct drm_i915_gem_object *obj;
  830. int i = 0;
  831. list_for_each_entry(obj, head, mm_list) {
  832. capture_bo(err++, obj);
  833. if (++i == count)
  834. break;
  835. }
  836. return i;
  837. }
  838. static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
  839. int count, struct list_head *head)
  840. {
  841. struct drm_i915_gem_object *obj;
  842. int i = 0;
  843. list_for_each_entry(obj, head, gtt_list) {
  844. if (obj->pin_count == 0)
  845. continue;
  846. capture_bo(err++, obj);
  847. if (++i == count)
  848. break;
  849. }
  850. return i;
  851. }
  852. static void i915_gem_record_fences(struct drm_device *dev,
  853. struct drm_i915_error_state *error)
  854. {
  855. struct drm_i915_private *dev_priv = dev->dev_private;
  856. int i;
  857. /* Fences */
  858. switch (INTEL_INFO(dev)->gen) {
  859. case 7:
  860. case 6:
  861. for (i = 0; i < 16; i++)
  862. error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
  863. break;
  864. case 5:
  865. case 4:
  866. for (i = 0; i < 16; i++)
  867. error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
  868. break;
  869. case 3:
  870. if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
  871. for (i = 0; i < 8; i++)
  872. error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
  873. case 2:
  874. for (i = 0; i < 8; i++)
  875. error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
  876. break;
  877. }
  878. }
  879. static struct drm_i915_error_object *
  880. i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
  881. struct intel_ring_buffer *ring)
  882. {
  883. struct drm_i915_gem_object *obj;
  884. u32 seqno;
  885. if (!ring->get_seqno)
  886. return NULL;
  887. if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
  888. u32 acthd = I915_READ(ACTHD);
  889. if (WARN_ON(ring->id != RCS))
  890. return NULL;
  891. obj = ring->private;
  892. if (acthd >= obj->gtt_offset &&
  893. acthd < obj->gtt_offset + obj->base.size)
  894. return i915_error_object_create(dev_priv, obj);
  895. }
  896. seqno = ring->get_seqno(ring, false);
  897. list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
  898. if (obj->ring != ring)
  899. continue;
  900. if (i915_seqno_passed(seqno, obj->last_read_seqno))
  901. continue;
  902. if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
  903. continue;
  904. /* We need to copy these to an anonymous buffer as the simplest
  905. * method to avoid being overwritten by userspace.
  906. */
  907. return i915_error_object_create(dev_priv, obj);
  908. }
  909. return NULL;
  910. }
  911. static void i915_record_ring_state(struct drm_device *dev,
  912. struct drm_i915_error_state *error,
  913. struct intel_ring_buffer *ring)
  914. {
  915. struct drm_i915_private *dev_priv = dev->dev_private;
  916. if (INTEL_INFO(dev)->gen >= 6) {
  917. error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
  918. error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
  919. error->semaphore_mboxes[ring->id][0]
  920. = I915_READ(RING_SYNC_0(ring->mmio_base));
  921. error->semaphore_mboxes[ring->id][1]
  922. = I915_READ(RING_SYNC_1(ring->mmio_base));
  923. error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
  924. error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
  925. }
  926. if (INTEL_INFO(dev)->gen >= 4) {
  927. error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
  928. error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
  929. error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
  930. error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
  931. error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
  932. if (ring->id == RCS)
  933. error->bbaddr = I915_READ64(BB_ADDR);
  934. } else {
  935. error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
  936. error->ipeir[ring->id] = I915_READ(IPEIR);
  937. error->ipehr[ring->id] = I915_READ(IPEHR);
  938. error->instdone[ring->id] = I915_READ(INSTDONE);
  939. }
  940. error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
  941. error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
  942. error->seqno[ring->id] = ring->get_seqno(ring, false);
  943. error->acthd[ring->id] = intel_ring_get_active_head(ring);
  944. error->head[ring->id] = I915_READ_HEAD(ring);
  945. error->tail[ring->id] = I915_READ_TAIL(ring);
  946. error->ctl[ring->id] = I915_READ_CTL(ring);
  947. error->cpu_ring_head[ring->id] = ring->head;
  948. error->cpu_ring_tail[ring->id] = ring->tail;
  949. }
  950. static void i915_gem_record_rings(struct drm_device *dev,
  951. struct drm_i915_error_state *error)
  952. {
  953. struct drm_i915_private *dev_priv = dev->dev_private;
  954. struct intel_ring_buffer *ring;
  955. struct drm_i915_gem_request *request;
  956. int i, count;
  957. for_each_ring(ring, dev_priv, i) {
  958. i915_record_ring_state(dev, error, ring);
  959. error->ring[i].batchbuffer =
  960. i915_error_first_batchbuffer(dev_priv, ring);
  961. error->ring[i].ringbuffer =
  962. i915_error_object_create(dev_priv, ring->obj);
  963. count = 0;
  964. list_for_each_entry(request, &ring->request_list, list)
  965. count++;
  966. error->ring[i].num_requests = count;
  967. error->ring[i].requests =
  968. kmalloc(count*sizeof(struct drm_i915_error_request),
  969. GFP_ATOMIC);
  970. if (error->ring[i].requests == NULL) {
  971. error->ring[i].num_requests = 0;
  972. continue;
  973. }
  974. count = 0;
  975. list_for_each_entry(request, &ring->request_list, list) {
  976. struct drm_i915_error_request *erq;
  977. erq = &error->ring[i].requests[count++];
  978. erq->seqno = request->seqno;
  979. erq->jiffies = request->emitted_jiffies;
  980. erq->tail = request->tail;
  981. }
  982. }
  983. }
  984. /**
  985. * i915_capture_error_state - capture an error record for later analysis
  986. * @dev: drm device
  987. *
  988. * Should be called when an error is detected (either a hang or an error
  989. * interrupt) to capture error state from the time of the error. Fills
  990. * out a structure which becomes available in debugfs for user level tools
  991. * to pick up.
  992. */
  993. static void i915_capture_error_state(struct drm_device *dev)
  994. {
  995. struct drm_i915_private *dev_priv = dev->dev_private;
  996. struct drm_i915_gem_object *obj;
  997. struct drm_i915_error_state *error;
  998. unsigned long flags;
  999. int i, pipe;
  1000. spin_lock_irqsave(&dev_priv->error_lock, flags);
  1001. error = dev_priv->first_error;
  1002. spin_unlock_irqrestore(&dev_priv->error_lock, flags);
  1003. if (error)
  1004. return;
  1005. /* Account for pipe specific data like PIPE*STAT */
  1006. error = kzalloc(sizeof(*error), GFP_ATOMIC);
  1007. if (!error) {
  1008. DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
  1009. return;
  1010. }
  1011. DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
  1012. dev->primary->index);
  1013. kref_init(&error->ref);
  1014. error->eir = I915_READ(EIR);
  1015. error->pgtbl_er = I915_READ(PGTBL_ER);
  1016. error->ccid = I915_READ(CCID);
  1017. if (HAS_PCH_SPLIT(dev))
  1018. error->ier = I915_READ(DEIER) | I915_READ(GTIER);
  1019. else if (IS_VALLEYVIEW(dev))
  1020. error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
  1021. else if (IS_GEN2(dev))
  1022. error->ier = I915_READ16(IER);
  1023. else
  1024. error->ier = I915_READ(IER);
  1025. if (INTEL_INFO(dev)->gen >= 6)
  1026. error->derrmr = I915_READ(DERRMR);
  1027. if (IS_VALLEYVIEW(dev))
  1028. error->forcewake = I915_READ(FORCEWAKE_VLV);
  1029. else if (INTEL_INFO(dev)->gen >= 7)
  1030. error->forcewake = I915_READ(FORCEWAKE_MT);
  1031. else if (INTEL_INFO(dev)->gen == 6)
  1032. error->forcewake = I915_READ(FORCEWAKE);
  1033. for_each_pipe(pipe)
  1034. error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
  1035. if (INTEL_INFO(dev)->gen >= 6) {
  1036. error->error = I915_READ(ERROR_GEN6);
  1037. error->done_reg = I915_READ(DONE_REG);
  1038. }
  1039. if (INTEL_INFO(dev)->gen == 7)
  1040. error->err_int = I915_READ(GEN7_ERR_INT);
  1041. i915_get_extra_instdone(dev, error->extra_instdone);
  1042. i915_gem_record_fences(dev, error);
  1043. i915_gem_record_rings(dev, error);
  1044. /* Record buffers on the active and pinned lists. */
  1045. error->active_bo = NULL;
  1046. error->pinned_bo = NULL;
  1047. i = 0;
  1048. list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
  1049. i++;
  1050. error->active_bo_count = i;
  1051. list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
  1052. if (obj->pin_count)
  1053. i++;
  1054. error->pinned_bo_count = i - error->active_bo_count;
  1055. error->active_bo = NULL;
  1056. error->pinned_bo = NULL;
  1057. if (i) {
  1058. error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
  1059. GFP_ATOMIC);
  1060. if (error->active_bo)
  1061. error->pinned_bo =
  1062. error->active_bo + error->active_bo_count;
  1063. }
  1064. if (error->active_bo)
  1065. error->active_bo_count =
  1066. capture_active_bo(error->active_bo,
  1067. error->active_bo_count,
  1068. &dev_priv->mm.active_list);
  1069. if (error->pinned_bo)
  1070. error->pinned_bo_count =
  1071. capture_pinned_bo(error->pinned_bo,
  1072. error->pinned_bo_count,
  1073. &dev_priv->mm.bound_list);
  1074. do_gettimeofday(&error->time);
  1075. error->overlay = intel_overlay_capture_error_state(dev);
  1076. error->display = intel_display_capture_error_state(dev);
  1077. spin_lock_irqsave(&dev_priv->error_lock, flags);
  1078. if (dev_priv->first_error == NULL) {
  1079. dev_priv->first_error = error;
  1080. error = NULL;
  1081. }
  1082. spin_unlock_irqrestore(&dev_priv->error_lock, flags);
  1083. if (error)
  1084. i915_error_state_free(&error->ref);
  1085. }
  1086. void i915_destroy_error_state(struct drm_device *dev)
  1087. {
  1088. struct drm_i915_private *dev_priv = dev->dev_private;
  1089. struct drm_i915_error_state *error;
  1090. unsigned long flags;
  1091. spin_lock_irqsave(&dev_priv->error_lock, flags);
  1092. error = dev_priv->first_error;
  1093. dev_priv->first_error = NULL;
  1094. spin_unlock_irqrestore(&dev_priv->error_lock, flags);
  1095. if (error)
  1096. kref_put(&error->ref, i915_error_state_free);
  1097. }
  1098. #else
  1099. #define i915_capture_error_state(x)
  1100. #endif
  1101. static void i915_report_and_clear_eir(struct drm_device *dev)
  1102. {
  1103. struct drm_i915_private *dev_priv = dev->dev_private;
  1104. uint32_t instdone[I915_NUM_INSTDONE_REG];
  1105. u32 eir = I915_READ(EIR);
  1106. int pipe, i;
  1107. if (!eir)
  1108. return;
  1109. pr_err("render error detected, EIR: 0x%08x\n", eir);
  1110. i915_get_extra_instdone(dev, instdone);
  1111. if (IS_G4X(dev)) {
  1112. if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
  1113. u32 ipeir = I915_READ(IPEIR_I965);
  1114. pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
  1115. pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
  1116. for (i = 0; i < ARRAY_SIZE(instdone); i++)
  1117. pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
  1118. pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
  1119. pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
  1120. I915_WRITE(IPEIR_I965, ipeir);
  1121. POSTING_READ(IPEIR_I965);
  1122. }
  1123. if (eir & GM45_ERROR_PAGE_TABLE) {
  1124. u32 pgtbl_err = I915_READ(PGTBL_ER);
  1125. pr_err("page table error\n");
  1126. pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
  1127. I915_WRITE(PGTBL_ER, pgtbl_err);
  1128. POSTING_READ(PGTBL_ER);
  1129. }
  1130. }
  1131. if (!IS_GEN2(dev)) {
  1132. if (eir & I915_ERROR_PAGE_TABLE) {
  1133. u32 pgtbl_err = I915_READ(PGTBL_ER);
  1134. pr_err("page table error\n");
  1135. pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
  1136. I915_WRITE(PGTBL_ER, pgtbl_err);
  1137. POSTING_READ(PGTBL_ER);
  1138. }
  1139. }
  1140. if (eir & I915_ERROR_MEMORY_REFRESH) {
  1141. pr_err("memory refresh error:\n");
  1142. for_each_pipe(pipe)
  1143. pr_err("pipe %c stat: 0x%08x\n",
  1144. pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
  1145. /* pipestat has already been acked */
  1146. }
  1147. if (eir & I915_ERROR_INSTRUCTION) {
  1148. pr_err("instruction error\n");
  1149. pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
  1150. for (i = 0; i < ARRAY_SIZE(instdone); i++)
  1151. pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
  1152. if (INTEL_INFO(dev)->gen < 4) {
  1153. u32 ipeir = I915_READ(IPEIR);
  1154. pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
  1155. pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
  1156. pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
  1157. I915_WRITE(IPEIR, ipeir);
  1158. POSTING_READ(IPEIR);
  1159. } else {
  1160. u32 ipeir = I915_READ(IPEIR_I965);
  1161. pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
  1162. pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
  1163. pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
  1164. pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
  1165. I915_WRITE(IPEIR_I965, ipeir);
  1166. POSTING_READ(IPEIR_I965);
  1167. }
  1168. }
  1169. I915_WRITE(EIR, eir);
  1170. POSTING_READ(EIR);
  1171. eir = I915_READ(EIR);
  1172. if (eir) {
  1173. /*
  1174. * some errors might have become stuck,
  1175. * mask them.
  1176. */
  1177. DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
  1178. I915_WRITE(EMR, I915_READ(EMR) | eir);
  1179. I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  1180. }
  1181. }
  1182. /**
  1183. * i915_handle_error - handle an error interrupt
  1184. * @dev: drm device
  1185. *
  1186. * Do some basic checking of regsiter state at error interrupt time and
  1187. * dump it to the syslog. Also call i915_capture_error_state() to make
  1188. * sure we get a record and make it available in debugfs. Fire a uevent
  1189. * so userspace knows something bad happened (should trigger collection
  1190. * of a ring dump etc.).
  1191. */
  1192. void i915_handle_error(struct drm_device *dev, bool wedged)
  1193. {
  1194. struct drm_i915_private *dev_priv = dev->dev_private;
  1195. struct intel_ring_buffer *ring;
  1196. int i;
  1197. i915_capture_error_state(dev);
  1198. i915_report_and_clear_eir(dev);
  1199. if (wedged) {
  1200. INIT_COMPLETION(dev_priv->error_completion);
  1201. atomic_set(&dev_priv->mm.wedged, 1);
  1202. /*
  1203. * Wakeup waiting processes so they don't hang
  1204. */
  1205. for_each_ring(ring, dev_priv, i)
  1206. wake_up_all(&ring->irq_queue);
  1207. }
  1208. queue_work(dev_priv->wq, &dev_priv->error_work);
  1209. }
  1210. static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
  1211. {
  1212. drm_i915_private_t *dev_priv = dev->dev_private;
  1213. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  1214. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1215. struct drm_i915_gem_object *obj;
  1216. struct intel_unpin_work *work;
  1217. unsigned long flags;
  1218. bool stall_detected;
  1219. /* Ignore early vblank irqs */
  1220. if (intel_crtc == NULL)
  1221. return;
  1222. spin_lock_irqsave(&dev->event_lock, flags);
  1223. work = intel_crtc->unpin_work;
  1224. if (work == NULL ||
  1225. atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
  1226. !work->enable_stall_check) {
  1227. /* Either the pending flip IRQ arrived, or we're too early. Don't check */
  1228. spin_unlock_irqrestore(&dev->event_lock, flags);
  1229. return;
  1230. }
  1231. /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
  1232. obj = work->pending_flip_obj;
  1233. if (INTEL_INFO(dev)->gen >= 4) {
  1234. int dspsurf = DSPSURF(intel_crtc->plane);
  1235. stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
  1236. obj->gtt_offset;
  1237. } else {
  1238. int dspaddr = DSPADDR(intel_crtc->plane);
  1239. stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
  1240. crtc->y * crtc->fb->pitches[0] +
  1241. crtc->x * crtc->fb->bits_per_pixel/8);
  1242. }
  1243. spin_unlock_irqrestore(&dev->event_lock, flags);
  1244. if (stall_detected) {
  1245. DRM_DEBUG_DRIVER("Pageflip stall detected\n");
  1246. intel_prepare_page_flip(dev, intel_crtc->plane);
  1247. }
  1248. }
  1249. /* Called from drm generic code, passed 'crtc' which
  1250. * we use as a pipe index
  1251. */
  1252. static int i915_enable_vblank(struct drm_device *dev, int pipe)
  1253. {
  1254. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1255. unsigned long irqflags;
  1256. if (!i915_pipe_enabled(dev, pipe))
  1257. return -EINVAL;
  1258. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1259. if (INTEL_INFO(dev)->gen >= 4)
  1260. i915_enable_pipestat(dev_priv, pipe,
  1261. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1262. else
  1263. i915_enable_pipestat(dev_priv, pipe,
  1264. PIPE_VBLANK_INTERRUPT_ENABLE);
  1265. /* maintain vblank delivery even in deep C-states */
  1266. if (dev_priv->info->gen == 3)
  1267. I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
  1268. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1269. return 0;
  1270. }
  1271. static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
  1272. {
  1273. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1274. unsigned long irqflags;
  1275. if (!i915_pipe_enabled(dev, pipe))
  1276. return -EINVAL;
  1277. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1278. ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
  1279. DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
  1280. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1281. return 0;
  1282. }
  1283. static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
  1284. {
  1285. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1286. unsigned long irqflags;
  1287. if (!i915_pipe_enabled(dev, pipe))
  1288. return -EINVAL;
  1289. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1290. ironlake_enable_display_irq(dev_priv,
  1291. DE_PIPEA_VBLANK_IVB << (5 * pipe));
  1292. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1293. return 0;
  1294. }
  1295. static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
  1296. {
  1297. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1298. unsigned long irqflags;
  1299. u32 imr;
  1300. if (!i915_pipe_enabled(dev, pipe))
  1301. return -EINVAL;
  1302. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1303. imr = I915_READ(VLV_IMR);
  1304. if (pipe == 0)
  1305. imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
  1306. else
  1307. imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
  1308. I915_WRITE(VLV_IMR, imr);
  1309. i915_enable_pipestat(dev_priv, pipe,
  1310. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1311. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1312. return 0;
  1313. }
  1314. /* Called from drm generic code, passed 'crtc' which
  1315. * we use as a pipe index
  1316. */
  1317. static void i915_disable_vblank(struct drm_device *dev, int pipe)
  1318. {
  1319. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1320. unsigned long irqflags;
  1321. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1322. if (dev_priv->info->gen == 3)
  1323. I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
  1324. i915_disable_pipestat(dev_priv, pipe,
  1325. PIPE_VBLANK_INTERRUPT_ENABLE |
  1326. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1327. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1328. }
  1329. static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
  1330. {
  1331. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1332. unsigned long irqflags;
  1333. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1334. ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
  1335. DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
  1336. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1337. }
  1338. static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
  1339. {
  1340. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1341. unsigned long irqflags;
  1342. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1343. ironlake_disable_display_irq(dev_priv,
  1344. DE_PIPEA_VBLANK_IVB << (pipe * 5));
  1345. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1346. }
  1347. static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
  1348. {
  1349. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1350. unsigned long irqflags;
  1351. u32 imr;
  1352. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1353. i915_disable_pipestat(dev_priv, pipe,
  1354. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1355. imr = I915_READ(VLV_IMR);
  1356. if (pipe == 0)
  1357. imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
  1358. else
  1359. imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
  1360. I915_WRITE(VLV_IMR, imr);
  1361. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1362. }
  1363. static u32
  1364. ring_last_seqno(struct intel_ring_buffer *ring)
  1365. {
  1366. return list_entry(ring->request_list.prev,
  1367. struct drm_i915_gem_request, list)->seqno;
  1368. }
  1369. static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
  1370. {
  1371. if (list_empty(&ring->request_list) ||
  1372. i915_seqno_passed(ring->get_seqno(ring, false),
  1373. ring_last_seqno(ring))) {
  1374. /* Issue a wake-up to catch stuck h/w. */
  1375. if (waitqueue_active(&ring->irq_queue)) {
  1376. DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
  1377. ring->name);
  1378. wake_up_all(&ring->irq_queue);
  1379. *err = true;
  1380. }
  1381. return true;
  1382. }
  1383. return false;
  1384. }
  1385. static bool kick_ring(struct intel_ring_buffer *ring)
  1386. {
  1387. struct drm_device *dev = ring->dev;
  1388. struct drm_i915_private *dev_priv = dev->dev_private;
  1389. u32 tmp = I915_READ_CTL(ring);
  1390. if (tmp & RING_WAIT) {
  1391. DRM_ERROR("Kicking stuck wait on %s\n",
  1392. ring->name);
  1393. I915_WRITE_CTL(ring, tmp);
  1394. return true;
  1395. }
  1396. return false;
  1397. }
  1398. static bool i915_hangcheck_hung(struct drm_device *dev)
  1399. {
  1400. drm_i915_private_t *dev_priv = dev->dev_private;
  1401. if (dev_priv->hangcheck_count++ > 1) {
  1402. bool hung = true;
  1403. DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
  1404. i915_handle_error(dev, true);
  1405. if (!IS_GEN2(dev)) {
  1406. struct intel_ring_buffer *ring;
  1407. int i;
  1408. /* Is the chip hanging on a WAIT_FOR_EVENT?
  1409. * If so we can simply poke the RB_WAIT bit
  1410. * and break the hang. This should work on
  1411. * all but the second generation chipsets.
  1412. */
  1413. for_each_ring(ring, dev_priv, i)
  1414. hung &= !kick_ring(ring);
  1415. }
  1416. return hung;
  1417. }
  1418. return false;
  1419. }
  1420. /**
  1421. * This is called when the chip hasn't reported back with completed
  1422. * batchbuffers in a long time. The first time this is called we simply record
  1423. * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
  1424. * again, we assume the chip is wedged and try to fix it.
  1425. */
  1426. void i915_hangcheck_elapsed(unsigned long data)
  1427. {
  1428. struct drm_device *dev = (struct drm_device *)data;
  1429. drm_i915_private_t *dev_priv = dev->dev_private;
  1430. uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
  1431. struct intel_ring_buffer *ring;
  1432. bool err = false, idle;
  1433. int i;
  1434. if (!i915_enable_hangcheck)
  1435. return;
  1436. memset(acthd, 0, sizeof(acthd));
  1437. idle = true;
  1438. for_each_ring(ring, dev_priv, i) {
  1439. idle &= i915_hangcheck_ring_idle(ring, &err);
  1440. acthd[i] = intel_ring_get_active_head(ring);
  1441. }
  1442. /* If all work is done then ACTHD clearly hasn't advanced. */
  1443. if (idle) {
  1444. if (err) {
  1445. if (i915_hangcheck_hung(dev))
  1446. return;
  1447. goto repeat;
  1448. }
  1449. dev_priv->hangcheck_count = 0;
  1450. return;
  1451. }
  1452. i915_get_extra_instdone(dev, instdone);
  1453. if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
  1454. memcmp(dev_priv->prev_instdone, instdone, sizeof(instdone)) == 0) {
  1455. if (i915_hangcheck_hung(dev))
  1456. return;
  1457. } else {
  1458. dev_priv->hangcheck_count = 0;
  1459. memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
  1460. memcpy(dev_priv->prev_instdone, instdone, sizeof(instdone));
  1461. }
  1462. repeat:
  1463. /* Reset timer case chip hangs without another request being added */
  1464. mod_timer(&dev_priv->hangcheck_timer,
  1465. round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
  1466. }
  1467. /* drm_dma.h hooks
  1468. */
  1469. static void ironlake_irq_preinstall(struct drm_device *dev)
  1470. {
  1471. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1472. atomic_set(&dev_priv->irq_received, 0);
  1473. I915_WRITE(HWSTAM, 0xeffe);
  1474. /* XXX hotplug from PCH */
  1475. I915_WRITE(DEIMR, 0xffffffff);
  1476. I915_WRITE(DEIER, 0x0);
  1477. POSTING_READ(DEIER);
  1478. /* and GT */
  1479. I915_WRITE(GTIMR, 0xffffffff);
  1480. I915_WRITE(GTIER, 0x0);
  1481. POSTING_READ(GTIER);
  1482. /* south display irq */
  1483. I915_WRITE(SDEIMR, 0xffffffff);
  1484. I915_WRITE(SDEIER, 0x0);
  1485. POSTING_READ(SDEIER);
  1486. }
  1487. static void valleyview_irq_preinstall(struct drm_device *dev)
  1488. {
  1489. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1490. int pipe;
  1491. atomic_set(&dev_priv->irq_received, 0);
  1492. /* VLV magic */
  1493. I915_WRITE(VLV_IMR, 0);
  1494. I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
  1495. I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
  1496. I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
  1497. /* and GT */
  1498. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1499. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1500. I915_WRITE(GTIMR, 0xffffffff);
  1501. I915_WRITE(GTIER, 0x0);
  1502. POSTING_READ(GTIER);
  1503. I915_WRITE(DPINVGTT, 0xff);
  1504. I915_WRITE(PORT_HOTPLUG_EN, 0);
  1505. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  1506. for_each_pip

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