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/sound/pci/vx222/vx222_ops.c

https://bitbucket.org/evzijst/gittest
C | 1004 lines | 696 code | 129 blank | 179 comment | 55 complexity | 884dd9c53aec00ae8c77b0ad225b5f40 MD5 | raw file
   1/*
   2 * Driver for Digigram VX222 V2/Mic soundcards
   3 *
   4 * VX222-specific low-level routines
   5 *
   6 * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de>
   7 *
   8 *   This program is free software; you can redistribute it and/or modify
   9 *   it under the terms of the GNU General Public License as published by
  10 *   the Free Software Foundation; either version 2 of the License, or
  11 *   (at your option) any later version.
  12 *
  13 *   This program is distributed in the hope that it will be useful,
  14 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 *   GNU General Public License for more details.
  17 *
  18 *   You should have received a copy of the GNU General Public License
  19 *   along with this program; if not, write to the Free Software
  20 *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  21 */
  22
  23#include <sound/driver.h>
  24#include <linux/delay.h>
  25#include <linux/device.h>
  26#include <linux/firmware.h>
  27#include <sound/core.h>
  28#include <sound/control.h>
  29#include <asm/io.h>
  30#include "vx222.h"
  31
  32
  33static int vx2_reg_offset[VX_REG_MAX] = {
  34	[VX_ICR]    = 0x00,
  35	[VX_CVR]    = 0x04,
  36	[VX_ISR]    = 0x08,
  37	[VX_IVR]    = 0x0c,
  38	[VX_RXH]    = 0x14,
  39	[VX_RXM]    = 0x18,
  40	[VX_RXL]    = 0x1c,
  41	[VX_DMA]    = 0x10,
  42	[VX_CDSP]   = 0x20,
  43	[VX_CFG]    = 0x24,
  44	[VX_RUER]   = 0x28,
  45	[VX_DATA]   = 0x2c,
  46	[VX_STATUS] = 0x30,
  47	[VX_LOFREQ] = 0x34,
  48	[VX_HIFREQ] = 0x38,
  49	[VX_CSUER]  = 0x3c,
  50	[VX_SELMIC] = 0x40,
  51	[VX_COMPOT] = 0x44, // Write: POTENTIOMETER ; Read: COMPRESSION LEVEL activate
  52	[VX_SCOMPR] = 0x48, // Read: COMPRESSION THRESHOLD activate
  53	[VX_GLIMIT] = 0x4c, // Read: LEVEL LIMITATION activate
  54	[VX_INTCSR] = 0x4c, // VX_INTCSR_REGISTER_OFFSET
  55	[VX_CNTRL]  = 0x50,		// VX_CNTRL_REGISTER_OFFSET
  56	[VX_GPIOC]  = 0x54,		// VX_GPIOC (new with PLX9030)
  57};
  58
  59static int vx2_reg_index[VX_REG_MAX] = {
  60	[VX_ICR]	= 1,
  61	[VX_CVR]	= 1,
  62	[VX_ISR]	= 1,
  63	[VX_IVR]	= 1,
  64	[VX_RXH]	= 1,
  65	[VX_RXM]	= 1,
  66	[VX_RXL]	= 1,
  67	[VX_DMA]	= 1,
  68	[VX_CDSP]	= 1,
  69	[VX_CFG]	= 1,
  70	[VX_RUER]	= 1,
  71	[VX_DATA]	= 1,
  72	[VX_STATUS]	= 1,
  73	[VX_LOFREQ]	= 1,
  74	[VX_HIFREQ]	= 1,
  75	[VX_CSUER]	= 1,
  76	[VX_SELMIC]	= 1,
  77	[VX_COMPOT]	= 1,
  78	[VX_SCOMPR]	= 1,
  79	[VX_GLIMIT]	= 1,
  80	[VX_INTCSR]	= 0,	/* on the PLX */
  81	[VX_CNTRL]	= 0,	/* on the PLX */
  82	[VX_GPIOC]	= 0,	/* on the PLX */
  83};
  84
  85inline static unsigned long vx2_reg_addr(vx_core_t *_chip, int reg)
  86{
  87	struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
  88	return chip->port[vx2_reg_index[reg]] + vx2_reg_offset[reg];
  89}
  90
  91/**
  92 * snd_vx_inb - read a byte from the register
  93 * @offset: register enum
  94 */
  95static unsigned char vx2_inb(vx_core_t *chip, int offset)
  96{
  97	return inb(vx2_reg_addr(chip, offset));
  98}
  99
 100/**
 101 * snd_vx_outb - write a byte on the register
 102 * @offset: the register offset
 103 * @val: the value to write
 104 */
 105static void vx2_outb(vx_core_t *chip, int offset, unsigned char val)
 106{
 107	outb(val, vx2_reg_addr(chip, offset));
 108	//printk("outb: %x -> %x\n", val, vx2_reg_addr(chip, offset));
 109}
 110
 111/**
 112 * snd_vx_inl - read a 32bit word from the register
 113 * @offset: register enum
 114 */
 115static unsigned int vx2_inl(vx_core_t *chip, int offset)
 116{
 117	return inl(vx2_reg_addr(chip, offset));
 118}
 119
 120/**
 121 * snd_vx_outl - write a 32bit word on the register
 122 * @offset: the register enum
 123 * @val: the value to write
 124 */
 125static void vx2_outl(vx_core_t *chip, int offset, unsigned int val)
 126{
 127	// printk("outl: %x -> %x\n", val, vx2_reg_addr(chip, offset));
 128	outl(val, vx2_reg_addr(chip, offset));
 129}
 130
 131/*
 132 * redefine macros to call directly
 133 */
 134#undef vx_inb
 135#define vx_inb(chip,reg)	vx2_inb((vx_core_t*)(chip), VX_##reg)
 136#undef vx_outb
 137#define vx_outb(chip,reg,val)	vx2_outb((vx_core_t*)(chip), VX_##reg, val)
 138#undef vx_inl
 139#define vx_inl(chip,reg)	vx2_inl((vx_core_t*)(chip), VX_##reg)
 140#undef vx_outl
 141#define vx_outl(chip,reg,val)	vx2_outl((vx_core_t*)(chip), VX_##reg, val)
 142
 143
 144/*
 145 * vx_reset_dsp - reset the DSP
 146 */
 147
 148#define XX_DSP_RESET_WAIT_TIME		2	/* ms */
 149
 150static void vx2_reset_dsp(vx_core_t *_chip)
 151{
 152	struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
 153
 154	/* set the reset dsp bit to 0 */
 155	vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_DSP_RESET_MASK);
 156
 157	snd_vx_delay(_chip, XX_DSP_RESET_WAIT_TIME);
 158
 159	chip->regCDSP |= VX_CDSP_DSP_RESET_MASK;
 160	/* set the reset dsp bit to 1 */
 161	vx_outl(chip, CDSP, chip->regCDSP);
 162}
 163
 164
 165static int vx2_test_xilinx(vx_core_t *_chip)
 166{
 167	struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
 168	unsigned int data;
 169
 170	snd_printdd("testing xilinx...\n");
 171	/* This test uses several write/read sequences on TEST0 and TEST1 bits
 172	 * to figure out whever or not the xilinx was correctly loaded
 173	 */
 174
 175	/* We write 1 on CDSP.TEST0. We should get 0 on STATUS.TEST0. */
 176	vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST0_MASK);
 177	vx_inl(chip, ISR);
 178	data = vx_inl(chip, STATUS);
 179	if ((data & VX_STATUS_VAL_TEST0_MASK) == VX_STATUS_VAL_TEST0_MASK) {
 180		snd_printdd("bad!\n");
 181		return -ENODEV;
 182	}
 183
 184	/* We write 0 on CDSP.TEST0. We should get 1 on STATUS.TEST0. */
 185	vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST0_MASK);
 186	vx_inl(chip, ISR);
 187	data = vx_inl(chip, STATUS);
 188	if (! (data & VX_STATUS_VAL_TEST0_MASK)) {
 189		snd_printdd("bad! #2\n");
 190		return -ENODEV;
 191	}
 192
 193	if (_chip->type == VX_TYPE_BOARD) {
 194		/* not implemented on VX_2_BOARDS */
 195		/* We write 1 on CDSP.TEST1. We should get 0 on STATUS.TEST1. */
 196		vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST1_MASK);
 197		vx_inl(chip, ISR);
 198		data = vx_inl(chip, STATUS);
 199		if ((data & VX_STATUS_VAL_TEST1_MASK) == VX_STATUS_VAL_TEST1_MASK) {
 200			snd_printdd("bad! #3\n");
 201			return -ENODEV;
 202		}
 203
 204		/* We write 0 on CDSP.TEST1. We should get 1 on STATUS.TEST1. */
 205		vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST1_MASK);
 206		vx_inl(chip, ISR);
 207		data = vx_inl(chip, STATUS);
 208		if (! (data & VX_STATUS_VAL_TEST1_MASK)) {
 209			snd_printdd("bad! #4\n");
 210			return -ENODEV;
 211		}
 212	}
 213	snd_printdd("ok, xilinx fine.\n");
 214	return 0;
 215}
 216
 217
 218/**
 219 * vx_setup_pseudo_dma - set up the pseudo dma read/write mode.
 220 * @do_write: 0 = read, 1 = set up for DMA write
 221 */
 222static void vx2_setup_pseudo_dma(vx_core_t *chip, int do_write)
 223{
 224	/* Interrupt mode and HREQ pin enabled for host transmit data transfers
 225	 * (in case of the use of the pseudo-dma facility).
 226	 */
 227	vx_outl(chip, ICR, do_write ? ICR_TREQ : ICR_RREQ);
 228
 229	/* Reset the pseudo-dma register (in case of the use of the
 230	 * pseudo-dma facility).
 231	 */
 232	vx_outl(chip, RESET_DMA, 0);
 233}
 234
 235/*
 236 * vx_release_pseudo_dma - disable the pseudo-DMA mode
 237 */
 238inline static void vx2_release_pseudo_dma(vx_core_t *chip)
 239{
 240	/* HREQ pin disabled. */
 241	vx_outl(chip, ICR, 0);
 242}
 243
 244
 245
 246/* pseudo-dma write */
 247static void vx2_dma_write(vx_core_t *chip, snd_pcm_runtime_t *runtime,
 248			  vx_pipe_t *pipe, int count)
 249{
 250	unsigned long port = vx2_reg_addr(chip, VX_DMA);
 251	int offset = pipe->hw_ptr;
 252	u32 *addr = (u32 *)(runtime->dma_area + offset);
 253
 254	snd_assert(count % 4 == 0, return);
 255
 256	vx2_setup_pseudo_dma(chip, 1);
 257
 258	/* Transfer using pseudo-dma.
 259	 */
 260	if (offset + count > pipe->buffer_bytes) {
 261		int length = pipe->buffer_bytes - offset;
 262		count -= length;
 263		length >>= 2; /* in 32bit words */
 264		/* Transfer using pseudo-dma. */
 265		while (length-- > 0) {
 266			outl(cpu_to_le32(*addr), port);
 267			addr++;
 268		}
 269		addr = (u32 *)runtime->dma_area;
 270		pipe->hw_ptr = 0;
 271	}
 272	pipe->hw_ptr += count;
 273	count >>= 2; /* in 32bit words */
 274	/* Transfer using pseudo-dma. */
 275	while (count-- > 0) {
 276		outl(cpu_to_le32(*addr), port);
 277		addr++;
 278	}
 279
 280	vx2_release_pseudo_dma(chip);
 281}
 282
 283
 284/* pseudo dma read */
 285static void vx2_dma_read(vx_core_t *chip, snd_pcm_runtime_t *runtime,
 286			 vx_pipe_t *pipe, int count)
 287{
 288	int offset = pipe->hw_ptr;
 289	u32 *addr = (u32 *)(runtime->dma_area + offset);
 290	unsigned long port = vx2_reg_addr(chip, VX_DMA);
 291
 292	snd_assert(count % 4 == 0, return);
 293
 294	vx2_setup_pseudo_dma(chip, 0);
 295	/* Transfer using pseudo-dma.
 296	 */
 297	if (offset + count > pipe->buffer_bytes) {
 298		int length = pipe->buffer_bytes - offset;
 299		count -= length;
 300		length >>= 2; /* in 32bit words */
 301		/* Transfer using pseudo-dma. */
 302		while (length-- > 0)
 303			*addr++ = le32_to_cpu(inl(port));
 304		addr = (u32 *)runtime->dma_area;
 305		pipe->hw_ptr = 0;
 306	}
 307	pipe->hw_ptr += count;
 308	count >>= 2; /* in 32bit words */
 309	/* Transfer using pseudo-dma. */
 310	while (count-- > 0)
 311		*addr++ = le32_to_cpu(inl(port));
 312
 313	vx2_release_pseudo_dma(chip);
 314}
 315
 316#define VX_XILINX_RESET_MASK        0x40000000
 317#define VX_USERBIT0_MASK            0x00000004
 318#define VX_USERBIT1_MASK            0x00000020
 319#define VX_CNTRL_REGISTER_VALUE     0x00172012
 320
 321/*
 322 * transfer counts bits to PLX
 323 */
 324static int put_xilinx_data(vx_core_t *chip, unsigned int port, unsigned int counts, unsigned char data)
 325{
 326	unsigned int i;
 327
 328	for (i = 0; i < counts; i++) {
 329		unsigned int val;
 330
 331		/* set the clock bit to 0. */
 332		val = VX_CNTRL_REGISTER_VALUE & ~VX_USERBIT0_MASK;
 333		vx2_outl(chip, port, val);
 334		vx2_inl(chip, port);
 335		udelay(1);
 336
 337		if (data & (1 << i))
 338			val |= VX_USERBIT1_MASK;
 339		else
 340			val &= ~VX_USERBIT1_MASK;
 341		vx2_outl(chip, port, val);
 342		vx2_inl(chip, port);
 343
 344		/* set the clock bit to 1. */
 345		val |= VX_USERBIT0_MASK;
 346		vx2_outl(chip, port, val);
 347		vx2_inl(chip, port);
 348		udelay(1);
 349	}
 350	return 0;
 351}
 352
 353/*
 354 * load the xilinx image
 355 */
 356static int vx2_load_xilinx_binary(vx_core_t *chip, const struct firmware *xilinx)
 357{
 358	unsigned int i;
 359	unsigned int port;
 360	unsigned char *image;
 361
 362	/* XILINX reset (wait at least 1 milisecond between reset on and off). */
 363	vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE | VX_XILINX_RESET_MASK);
 364	vx_inl(chip, CNTRL);
 365	snd_vx_delay(chip, 10);
 366	vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE);
 367	vx_inl(chip, CNTRL);
 368	snd_vx_delay(chip, 10);
 369
 370	if (chip->type == VX_TYPE_BOARD)
 371		port = VX_CNTRL;
 372	else
 373		port = VX_GPIOC; /* VX222 V2 and VX222_MIC_BOARD with new PLX9030 use this register */
 374
 375	image = xilinx->data;
 376	for (i = 0; i < xilinx->size; i++, image++) {
 377		if (put_xilinx_data(chip, port, 8, *image) < 0)
 378			return -EINVAL;
 379		/* don't take too much time in this loop... */
 380		cond_resched();
 381	}
 382	put_xilinx_data(chip, port, 4, 0xff); /* end signature */
 383
 384	snd_vx_delay(chip, 200);
 385
 386	/* test after loading (is buggy with VX222) */
 387	if (chip->type != VX_TYPE_BOARD) {
 388		/* Test if load successful: test bit 8 of register GPIOC (VX222: use CNTRL) ! */
 389		i = vx_inl(chip, GPIOC);
 390		if (i & 0x0100)
 391			return 0;
 392		snd_printk(KERN_ERR "vx222: xilinx test failed after load, GPIOC=0x%x\n", i);
 393		return -EINVAL;
 394	}
 395
 396	return 0;
 397}
 398
 399	
 400/*
 401 * load the boot/dsp images
 402 */
 403static int vx2_load_dsp(vx_core_t *vx, int index, const struct firmware *dsp)
 404{
 405	int err;
 406
 407	switch (index) {
 408	case 1:
 409		/* xilinx image */
 410		if ((err = vx2_load_xilinx_binary(vx, dsp)) < 0)
 411			return err;
 412		if ((err = vx2_test_xilinx(vx)) < 0)
 413			return err;
 414		return 0;
 415	case 2:
 416		/* DSP boot */
 417		return snd_vx_dsp_boot(vx, dsp);
 418	case 3:
 419		/* DSP image */
 420		return snd_vx_dsp_load(vx, dsp);
 421	default:
 422		snd_BUG();
 423		return -EINVAL;
 424	}
 425}
 426
 427
 428/*
 429 * vx_test_and_ack - test and acknowledge interrupt
 430 *
 431 * called from irq hander, too
 432 *
 433 * spinlock held!
 434 */
 435static int vx2_test_and_ack(vx_core_t *chip)
 436{
 437	/* not booted yet? */
 438	if (! (chip->chip_status & VX_STAT_XILINX_LOADED))
 439		return -ENXIO;
 440
 441	if (! (vx_inl(chip, STATUS) & VX_STATUS_MEMIRQ_MASK))
 442		return -EIO;
 443	
 444	/* ok, interrupts generated, now ack it */
 445	/* set ACQUIT bit up and down */
 446	vx_outl(chip, STATUS, 0);
 447	/* useless read just to spend some time and maintain
 448	 * the ACQUIT signal up for a while ( a bus cycle )
 449	 */
 450	vx_inl(chip, STATUS);
 451	/* ack */
 452	vx_outl(chip, STATUS, VX_STATUS_MEMIRQ_MASK);
 453	/* useless read just to spend some time and maintain
 454	 * the ACQUIT signal up for a while ( a bus cycle ) */
 455	vx_inl(chip, STATUS);
 456	/* clear */
 457	vx_outl(chip, STATUS, 0);
 458
 459	return 0;
 460}
 461
 462
 463/*
 464 * vx_validate_irq - enable/disable IRQ
 465 */
 466static void vx2_validate_irq(vx_core_t *_chip, int enable)
 467{
 468	struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
 469
 470	/* Set the interrupt enable bit to 1 in CDSP register */
 471	if (enable) {
 472		/* Set the PCI interrupt enable bit to 1.*/
 473		vx_outl(chip, INTCSR, VX_INTCSR_VALUE|VX_PCI_INTERRUPT_MASK);
 474		chip->regCDSP |= VX_CDSP_VALID_IRQ_MASK;
 475	} else {
 476		/* Set the PCI interrupt enable bit to 0. */
 477		vx_outl(chip, INTCSR, VX_INTCSR_VALUE&~VX_PCI_INTERRUPT_MASK);
 478		chip->regCDSP &= ~VX_CDSP_VALID_IRQ_MASK;
 479	}
 480	vx_outl(chip, CDSP, chip->regCDSP);
 481}
 482
 483
 484/*
 485 * write an AKM codec data (24bit)
 486 */
 487static void vx2_write_codec_reg(vx_core_t *chip, unsigned int data)
 488{
 489	unsigned int i;
 490
 491	vx_inl(chip, HIFREQ);
 492
 493	/* We have to send 24 bits (3 x 8 bits). Start with most signif. Bit */
 494	for (i = 0; i < 24; i++, data <<= 1)
 495		vx_outl(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0));
 496	/* Terminate access to codec registers */
 497	vx_inl(chip, RUER);
 498}
 499
 500
 501#define AKM_CODEC_POWER_CONTROL_CMD 0xA007
 502#define AKM_CODEC_RESET_ON_CMD      0xA100
 503#define AKM_CODEC_RESET_OFF_CMD     0xA103
 504#define AKM_CODEC_CLOCK_FORMAT_CMD  0xA240
 505#define AKM_CODEC_MUTE_CMD          0xA38D
 506#define AKM_CODEC_UNMUTE_CMD        0xA30D
 507#define AKM_CODEC_LEFT_LEVEL_CMD    0xA400
 508#define AKM_CODEC_RIGHT_LEVEL_CMD   0xA500
 509
 510static const u8 vx2_akm_gains_lut[VX2_AKM_LEVEL_MAX+1] = {
 511    0x7f,       // [000] =  +0.000 dB  ->  AKM(0x7f) =  +0.000 dB  error(+0.000 dB)
 512    0x7d,       // [001] =  -0.500 dB  ->  AKM(0x7d) =  -0.572 dB  error(-0.072 dB)
 513    0x7c,       // [002] =  -1.000 dB  ->  AKM(0x7c) =  -0.873 dB  error(+0.127 dB)
 514    0x7a,       // [003] =  -1.500 dB  ->  AKM(0x7a) =  -1.508 dB  error(-0.008 dB)
 515    0x79,       // [004] =  -2.000 dB  ->  AKM(0x79) =  -1.844 dB  error(+0.156 dB)
 516    0x77,       // [005] =  -2.500 dB  ->  AKM(0x77) =  -2.557 dB  error(-0.057 dB)
 517    0x76,       // [006] =  -3.000 dB  ->  AKM(0x76) =  -2.937 dB  error(+0.063 dB)
 518    0x75,       // [007] =  -3.500 dB  ->  AKM(0x75) =  -3.334 dB  error(+0.166 dB)
 519    0x73,       // [008] =  -4.000 dB  ->  AKM(0x73) =  -4.188 dB  error(-0.188 dB)
 520    0x72,       // [009] =  -4.500 dB  ->  AKM(0x72) =  -4.648 dB  error(-0.148 dB)
 521    0x71,       // [010] =  -5.000 dB  ->  AKM(0x71) =  -5.134 dB  error(-0.134 dB)
 522    0x70,       // [011] =  -5.500 dB  ->  AKM(0x70) =  -5.649 dB  error(-0.149 dB)
 523    0x6f,       // [012] =  -6.000 dB  ->  AKM(0x6f) =  -6.056 dB  error(-0.056 dB)
 524    0x6d,       // [013] =  -6.500 dB  ->  AKM(0x6d) =  -6.631 dB  error(-0.131 dB)
 525    0x6c,       // [014] =  -7.000 dB  ->  AKM(0x6c) =  -6.933 dB  error(+0.067 dB)
 526    0x6a,       // [015] =  -7.500 dB  ->  AKM(0x6a) =  -7.571 dB  error(-0.071 dB)
 527    0x69,       // [016] =  -8.000 dB  ->  AKM(0x69) =  -7.909 dB  error(+0.091 dB)
 528    0x67,       // [017] =  -8.500 dB  ->  AKM(0x67) =  -8.626 dB  error(-0.126 dB)
 529    0x66,       // [018] =  -9.000 dB  ->  AKM(0x66) =  -9.008 dB  error(-0.008 dB)
 530    0x65,       // [019] =  -9.500 dB  ->  AKM(0x65) =  -9.407 dB  error(+0.093 dB)
 531    0x64,       // [020] = -10.000 dB  ->  AKM(0x64) =  -9.826 dB  error(+0.174 dB)
 532    0x62,       // [021] = -10.500 dB  ->  AKM(0x62) = -10.730 dB  error(-0.230 dB)
 533    0x61,       // [022] = -11.000 dB  ->  AKM(0x61) = -11.219 dB  error(-0.219 dB)
 534    0x60,       // [023] = -11.500 dB  ->  AKM(0x60) = -11.738 dB  error(-0.238 dB)
 535    0x5f,       // [024] = -12.000 dB  ->  AKM(0x5f) = -12.149 dB  error(-0.149 dB)
 536    0x5e,       // [025] = -12.500 dB  ->  AKM(0x5e) = -12.434 dB  error(+0.066 dB)
 537    0x5c,       // [026] = -13.000 dB  ->  AKM(0x5c) = -13.033 dB  error(-0.033 dB)
 538    0x5b,       // [027] = -13.500 dB  ->  AKM(0x5b) = -13.350 dB  error(+0.150 dB)
 539    0x59,       // [028] = -14.000 dB  ->  AKM(0x59) = -14.018 dB  error(-0.018 dB)
 540    0x58,       // [029] = -14.500 dB  ->  AKM(0x58) = -14.373 dB  error(+0.127 dB)
 541    0x56,       // [030] = -15.000 dB  ->  AKM(0x56) = -15.130 dB  error(-0.130 dB)
 542    0x55,       // [031] = -15.500 dB  ->  AKM(0x55) = -15.534 dB  error(-0.034 dB)
 543    0x54,       // [032] = -16.000 dB  ->  AKM(0x54) = -15.958 dB  error(+0.042 dB)
 544    0x53,       // [033] = -16.500 dB  ->  AKM(0x53) = -16.404 dB  error(+0.096 dB)
 545    0x52,       // [034] = -17.000 dB  ->  AKM(0x52) = -16.874 dB  error(+0.126 dB)
 546    0x51,       // [035] = -17.500 dB  ->  AKM(0x51) = -17.371 dB  error(+0.129 dB)
 547    0x50,       // [036] = -18.000 dB  ->  AKM(0x50) = -17.898 dB  error(+0.102 dB)
 548    0x4e,       // [037] = -18.500 dB  ->  AKM(0x4e) = -18.605 dB  error(-0.105 dB)
 549    0x4d,       // [038] = -19.000 dB  ->  AKM(0x4d) = -18.905 dB  error(+0.095 dB)
 550    0x4b,       // [039] = -19.500 dB  ->  AKM(0x4b) = -19.538 dB  error(-0.038 dB)
 551    0x4a,       // [040] = -20.000 dB  ->  AKM(0x4a) = -19.872 dB  error(+0.128 dB)
 552    0x48,       // [041] = -20.500 dB  ->  AKM(0x48) = -20.583 dB  error(-0.083 dB)
 553    0x47,       // [042] = -21.000 dB  ->  AKM(0x47) = -20.961 dB  error(+0.039 dB)
 554    0x46,       // [043] = -21.500 dB  ->  AKM(0x46) = -21.356 dB  error(+0.144 dB)
 555    0x44,       // [044] = -22.000 dB  ->  AKM(0x44) = -22.206 dB  error(-0.206 dB)
 556    0x43,       // [045] = -22.500 dB  ->  AKM(0x43) = -22.664 dB  error(-0.164 dB)
 557    0x42,       // [046] = -23.000 dB  ->  AKM(0x42) = -23.147 dB  error(-0.147 dB)
 558    0x41,       // [047] = -23.500 dB  ->  AKM(0x41) = -23.659 dB  error(-0.159 dB)
 559    0x40,       // [048] = -24.000 dB  ->  AKM(0x40) = -24.203 dB  error(-0.203 dB)
 560    0x3f,       // [049] = -24.500 dB  ->  AKM(0x3f) = -24.635 dB  error(-0.135 dB)
 561    0x3e,       // [050] = -25.000 dB  ->  AKM(0x3e) = -24.935 dB  error(+0.065 dB)
 562    0x3c,       // [051] = -25.500 dB  ->  AKM(0x3c) = -25.569 dB  error(-0.069 dB)
 563    0x3b,       // [052] = -26.000 dB  ->  AKM(0x3b) = -25.904 dB  error(+0.096 dB)
 564    0x39,       // [053] = -26.500 dB  ->  AKM(0x39) = -26.615 dB  error(-0.115 dB)
 565    0x38,       // [054] = -27.000 dB  ->  AKM(0x38) = -26.994 dB  error(+0.006 dB)
 566    0x37,       // [055] = -27.500 dB  ->  AKM(0x37) = -27.390 dB  error(+0.110 dB)
 567    0x36,       // [056] = -28.000 dB  ->  AKM(0x36) = -27.804 dB  error(+0.196 dB)
 568    0x34,       // [057] = -28.500 dB  ->  AKM(0x34) = -28.699 dB  error(-0.199 dB)
 569    0x33,       // [058] = -29.000 dB  ->  AKM(0x33) = -29.183 dB  error(-0.183 dB)
 570    0x32,       // [059] = -29.500 dB  ->  AKM(0x32) = -29.696 dB  error(-0.196 dB)
 571    0x31,       // [060] = -30.000 dB  ->  AKM(0x31) = -30.241 dB  error(-0.241 dB)
 572    0x31,       // [061] = -30.500 dB  ->  AKM(0x31) = -30.241 dB  error(+0.259 dB)
 573    0x30,       // [062] = -31.000 dB  ->  AKM(0x30) = -30.823 dB  error(+0.177 dB)
 574    0x2e,       // [063] = -31.500 dB  ->  AKM(0x2e) = -31.610 dB  error(-0.110 dB)
 575    0x2d,       // [064] = -32.000 dB  ->  AKM(0x2d) = -31.945 dB  error(+0.055 dB)
 576    0x2b,       // [065] = -32.500 dB  ->  AKM(0x2b) = -32.659 dB  error(-0.159 dB)
 577    0x2a,       // [066] = -33.000 dB  ->  AKM(0x2a) = -33.038 dB  error(-0.038 dB)
 578    0x29,       // [067] = -33.500 dB  ->  AKM(0x29) = -33.435 dB  error(+0.065 dB)
 579    0x28,       // [068] = -34.000 dB  ->  AKM(0x28) = -33.852 dB  error(+0.148 dB)
 580    0x27,       // [069] = -34.500 dB  ->  AKM(0x27) = -34.289 dB  error(+0.211 dB)
 581    0x25,       // [070] = -35.000 dB  ->  AKM(0x25) = -35.235 dB  error(-0.235 dB)
 582    0x24,       // [071] = -35.500 dB  ->  AKM(0x24) = -35.750 dB  error(-0.250 dB)
 583    0x24,       // [072] = -36.000 dB  ->  AKM(0x24) = -35.750 dB  error(+0.250 dB)
 584    0x23,       // [073] = -36.500 dB  ->  AKM(0x23) = -36.297 dB  error(+0.203 dB)
 585    0x22,       // [074] = -37.000 dB  ->  AKM(0x22) = -36.881 dB  error(+0.119 dB)
 586    0x21,       // [075] = -37.500 dB  ->  AKM(0x21) = -37.508 dB  error(-0.008 dB)
 587    0x20,       // [076] = -38.000 dB  ->  AKM(0x20) = -38.183 dB  error(-0.183 dB)
 588    0x1f,       // [077] = -38.500 dB  ->  AKM(0x1f) = -38.726 dB  error(-0.226 dB)
 589    0x1e,       // [078] = -39.000 dB  ->  AKM(0x1e) = -39.108 dB  error(-0.108 dB)
 590    0x1d,       // [079] = -39.500 dB  ->  AKM(0x1d) = -39.507 dB  error(-0.007 dB)
 591    0x1c,       // [080] = -40.000 dB  ->  AKM(0x1c) = -39.926 dB  error(+0.074 dB)
 592    0x1b,       // [081] = -40.500 dB  ->  AKM(0x1b) = -40.366 dB  error(+0.134 dB)
 593    0x1a,       // [082] = -41.000 dB  ->  AKM(0x1a) = -40.829 dB  error(+0.171 dB)
 594    0x19,       // [083] = -41.500 dB  ->  AKM(0x19) = -41.318 dB  error(+0.182 dB)
 595    0x18,       // [084] = -42.000 dB  ->  AKM(0x18) = -41.837 dB  error(+0.163 dB)
 596    0x17,       // [085] = -42.500 dB  ->  AKM(0x17) = -42.389 dB  error(+0.111 dB)
 597    0x16,       // [086] = -43.000 dB  ->  AKM(0x16) = -42.978 dB  error(+0.022 dB)
 598    0x15,       // [087] = -43.500 dB  ->  AKM(0x15) = -43.610 dB  error(-0.110 dB)
 599    0x14,       // [088] = -44.000 dB  ->  AKM(0x14) = -44.291 dB  error(-0.291 dB)
 600    0x14,       // [089] = -44.500 dB  ->  AKM(0x14) = -44.291 dB  error(+0.209 dB)
 601    0x13,       // [090] = -45.000 dB  ->  AKM(0x13) = -45.031 dB  error(-0.031 dB)
 602    0x12,       // [091] = -45.500 dB  ->  AKM(0x12) = -45.840 dB  error(-0.340 dB)
 603    0x12,       // [092] = -46.000 dB  ->  AKM(0x12) = -45.840 dB  error(+0.160 dB)
 604    0x11,       // [093] = -46.500 dB  ->  AKM(0x11) = -46.731 dB  error(-0.231 dB)
 605    0x11,       // [094] = -47.000 dB  ->  AKM(0x11) = -46.731 dB  error(+0.269 dB)
 606    0x10,       // [095] = -47.500 dB  ->  AKM(0x10) = -47.725 dB  error(-0.225 dB)
 607    0x10,       // [096] = -48.000 dB  ->  AKM(0x10) = -47.725 dB  error(+0.275 dB)
 608    0x0f,       // [097] = -48.500 dB  ->  AKM(0x0f) = -48.553 dB  error(-0.053 dB)
 609    0x0e,       // [098] = -49.000 dB  ->  AKM(0x0e) = -49.152 dB  error(-0.152 dB)
 610    0x0d,       // [099] = -49.500 dB  ->  AKM(0x0d) = -49.796 dB  error(-0.296 dB)
 611    0x0d,       // [100] = -50.000 dB  ->  AKM(0x0d) = -49.796 dB  error(+0.204 dB)
 612    0x0c,       // [101] = -50.500 dB  ->  AKM(0x0c) = -50.491 dB  error(+0.009 dB)
 613    0x0b,       // [102] = -51.000 dB  ->  AKM(0x0b) = -51.247 dB  error(-0.247 dB)
 614    0x0b,       // [103] = -51.500 dB  ->  AKM(0x0b) = -51.247 dB  error(+0.253 dB)
 615    0x0a,       // [104] = -52.000 dB  ->  AKM(0x0a) = -52.075 dB  error(-0.075 dB)
 616    0x0a,       // [105] = -52.500 dB  ->  AKM(0x0a) = -52.075 dB  error(+0.425 dB)
 617    0x09,       // [106] = -53.000 dB  ->  AKM(0x09) = -52.990 dB  error(+0.010 dB)
 618    0x09,       // [107] = -53.500 dB  ->  AKM(0x09) = -52.990 dB  error(+0.510 dB)
 619    0x08,       // [108] = -54.000 dB  ->  AKM(0x08) = -54.013 dB  error(-0.013 dB)
 620    0x08,       // [109] = -54.500 dB  ->  AKM(0x08) = -54.013 dB  error(+0.487 dB)
 621    0x07,       // [110] = -55.000 dB  ->  AKM(0x07) = -55.173 dB  error(-0.173 dB)
 622    0x07,       // [111] = -55.500 dB  ->  AKM(0x07) = -55.173 dB  error(+0.327 dB)
 623    0x06,       // [112] = -56.000 dB  ->  AKM(0x06) = -56.512 dB  error(-0.512 dB)
 624    0x06,       // [113] = -56.500 dB  ->  AKM(0x06) = -56.512 dB  error(-0.012 dB)
 625    0x06,       // [114] = -57.000 dB  ->  AKM(0x06) = -56.512 dB  error(+0.488 dB)
 626    0x05,       // [115] = -57.500 dB  ->  AKM(0x05) = -58.095 dB  error(-0.595 dB)
 627    0x05,       // [116] = -58.000 dB  ->  AKM(0x05) = -58.095 dB  error(-0.095 dB)
 628    0x05,       // [117] = -58.500 dB  ->  AKM(0x05) = -58.095 dB  error(+0.405 dB)
 629    0x05,       // [118] = -59.000 dB  ->  AKM(0x05) = -58.095 dB  error(+0.905 dB)
 630    0x04,       // [119] = -59.500 dB  ->  AKM(0x04) = -60.034 dB  error(-0.534 dB)
 631    0x04,       // [120] = -60.000 dB  ->  AKM(0x04) = -60.034 dB  error(-0.034 dB)
 632    0x04,       // [121] = -60.500 dB  ->  AKM(0x04) = -60.034 dB  error(+0.466 dB)
 633    0x04,       // [122] = -61.000 dB  ->  AKM(0x04) = -60.034 dB  error(+0.966 dB)
 634    0x03,       // [123] = -61.500 dB  ->  AKM(0x03) = -62.532 dB  error(-1.032 dB)
 635    0x03,       // [124] = -62.000 dB  ->  AKM(0x03) = -62.532 dB  error(-0.532 dB)
 636    0x03,       // [125] = -62.500 dB  ->  AKM(0x03) = -62.532 dB  error(-0.032 dB)
 637    0x03,       // [126] = -63.000 dB  ->  AKM(0x03) = -62.532 dB  error(+0.468 dB)
 638    0x03,       // [127] = -63.500 dB  ->  AKM(0x03) = -62.532 dB  error(+0.968 dB)
 639    0x03,       // [128] = -64.000 dB  ->  AKM(0x03) = -62.532 dB  error(+1.468 dB)
 640    0x02,       // [129] = -64.500 dB  ->  AKM(0x02) = -66.054 dB  error(-1.554 dB)
 641    0x02,       // [130] = -65.000 dB  ->  AKM(0x02) = -66.054 dB  error(-1.054 dB)
 642    0x02,       // [131] = -65.500 dB  ->  AKM(0x02) = -66.054 dB  error(-0.554 dB)
 643    0x02,       // [132] = -66.000 dB  ->  AKM(0x02) = -66.054 dB  error(-0.054 dB)
 644    0x02,       // [133] = -66.500 dB  ->  AKM(0x02) = -66.054 dB  error(+0.446 dB)
 645    0x02,       // [134] = -67.000 dB  ->  AKM(0x02) = -66.054 dB  error(+0.946 dB)
 646    0x02,       // [135] = -67.500 dB  ->  AKM(0x02) = -66.054 dB  error(+1.446 dB)
 647    0x02,       // [136] = -68.000 dB  ->  AKM(0x02) = -66.054 dB  error(+1.946 dB)
 648    0x02,       // [137] = -68.500 dB  ->  AKM(0x02) = -66.054 dB  error(+2.446 dB)
 649    0x02,       // [138] = -69.000 dB  ->  AKM(0x02) = -66.054 dB  error(+2.946 dB)
 650    0x01,       // [139] = -69.500 dB  ->  AKM(0x01) = -72.075 dB  error(-2.575 dB)
 651    0x01,       // [140] = -70.000 dB  ->  AKM(0x01) = -72.075 dB  error(-2.075 dB)
 652    0x01,       // [141] = -70.500 dB  ->  AKM(0x01) = -72.075 dB  error(-1.575 dB)
 653    0x01,       // [142] = -71.000 dB  ->  AKM(0x01) = -72.075 dB  error(-1.075 dB)
 654    0x01,       // [143] = -71.500 dB  ->  AKM(0x01) = -72.075 dB  error(-0.575 dB)
 655    0x01,       // [144] = -72.000 dB  ->  AKM(0x01) = -72.075 dB  error(-0.075 dB)
 656    0x01,       // [145] = -72.500 dB  ->  AKM(0x01) = -72.075 dB  error(+0.425 dB)
 657    0x01,       // [146] = -73.000 dB  ->  AKM(0x01) = -72.075 dB  error(+0.925 dB)
 658    0x00};      // [147] = -73.500 dB  ->  AKM(0x00) =  mute       error(+infini)
 659
 660/*
 661 * pseudo-codec write entry
 662 */
 663static void vx2_write_akm(vx_core_t *chip, int reg, unsigned int data)
 664{
 665	unsigned int val;
 666
 667	if (reg == XX_CODEC_DAC_CONTROL_REGISTER) {
 668		vx2_write_codec_reg(chip, data ? AKM_CODEC_MUTE_CMD : AKM_CODEC_UNMUTE_CMD);
 669		return;
 670	}
 671
 672	/* `data' is a value between 0x0 and VX2_AKM_LEVEL_MAX = 0x093, in the case of the AKM codecs, we need
 673	   a look up table, as there is no linear matching between the driver codec values
 674	   and the real dBu value
 675	*/
 676	snd_assert(data < sizeof(vx2_akm_gains_lut), return);
 677
 678	switch (reg) {
 679	case XX_CODEC_LEVEL_LEFT_REGISTER:
 680		val = AKM_CODEC_LEFT_LEVEL_CMD;
 681		break;
 682	case XX_CODEC_LEVEL_RIGHT_REGISTER:
 683		val = AKM_CODEC_RIGHT_LEVEL_CMD;
 684		break;
 685	default:
 686		snd_BUG();
 687		return;
 688	}
 689	val |= vx2_akm_gains_lut[data];
 690
 691	vx2_write_codec_reg(chip, val);
 692}
 693
 694
 695/*
 696 * write codec bit for old VX222 board
 697 */
 698static void vx2_old_write_codec_bit(vx_core_t *chip, int codec, unsigned int data)
 699{
 700	int i;
 701
 702	/* activate access to codec registers */
 703	vx_inl(chip, HIFREQ);
 704
 705	for (i = 0; i < 24; i++, data <<= 1)
 706		vx_outl(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0));
 707
 708	/* Terminate access to codec registers */
 709	vx_inl(chip, RUER);
 710}
 711
 712
 713/*
 714 * reset codec bit
 715 */
 716static void vx2_reset_codec(vx_core_t *_chip)
 717{
 718	struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
 719
 720	/* Set the reset CODEC bit to 0. */
 721	vx_outl(chip, CDSP, chip->regCDSP &~ VX_CDSP_CODEC_RESET_MASK);
 722	vx_inl(chip, CDSP);
 723	snd_vx_delay(_chip, 10);
 724	/* Set the reset CODEC bit to 1. */
 725	chip->regCDSP |= VX_CDSP_CODEC_RESET_MASK;
 726	vx_outl(chip, CDSP, chip->regCDSP);
 727	vx_inl(chip, CDSP);
 728	if (_chip->type == VX_TYPE_BOARD) {
 729		snd_vx_delay(_chip, 1);
 730		return;
 731	}
 732
 733	snd_vx_delay(_chip, 5);  /* additionnel wait time for AKM's */
 734
 735	vx2_write_codec_reg(_chip, AKM_CODEC_POWER_CONTROL_CMD); /* DAC power up, ADC power up, Vref power down */
 736	
 737	vx2_write_codec_reg(_chip, AKM_CODEC_CLOCK_FORMAT_CMD); /* default */
 738	vx2_write_codec_reg(_chip, AKM_CODEC_MUTE_CMD); /* Mute = ON ,Deemphasis = OFF */
 739	vx2_write_codec_reg(_chip, AKM_CODEC_RESET_OFF_CMD); /* DAC and ADC normal operation */
 740
 741	if (_chip->type == VX_TYPE_MIC) {
 742		/* set up the micro input selector */
 743		chip->regSELMIC =  MICRO_SELECT_INPUT_NORM |
 744			MICRO_SELECT_PREAMPLI_G_0 |
 745			MICRO_SELECT_NOISE_T_52DB;
 746
 747		/* reset phantom power supply */
 748		chip->regSELMIC &= ~MICRO_SELECT_PHANTOM_ALIM;
 749
 750		vx_outl(_chip, SELMIC, chip->regSELMIC);
 751	}
 752}
 753
 754
 755/*
 756 * change the audio source
 757 */
 758static void vx2_change_audio_source(vx_core_t *_chip, int src)
 759{
 760	struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
 761
 762	switch (src) {
 763	case VX_AUDIO_SRC_DIGITAL:
 764		chip->regCFG |= VX_CFG_DATAIN_SEL_MASK;
 765		break;
 766	default:
 767		chip->regCFG &= ~VX_CFG_DATAIN_SEL_MASK;
 768		break;
 769	}
 770	vx_outl(chip, CFG, chip->regCFG);
 771}
 772
 773
 774/*
 775 * set the clock source
 776 */
 777static void vx2_set_clock_source(vx_core_t *_chip, int source)
 778{
 779	struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
 780
 781	if (source == INTERNAL_QUARTZ)
 782		chip->regCFG &= ~VX_CFG_CLOCKIN_SEL_MASK;
 783	else
 784		chip->regCFG |= VX_CFG_CLOCKIN_SEL_MASK;
 785	vx_outl(chip, CFG, chip->regCFG);
 786}
 787
 788/*
 789 * reset the board
 790 */
 791static void vx2_reset_board(vx_core_t *_chip, int cold_reset)
 792{
 793	struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
 794
 795	/* initialize the register values */
 796	chip->regCDSP = VX_CDSP_CODEC_RESET_MASK | VX_CDSP_DSP_RESET_MASK ;
 797	chip->regCFG = 0;
 798}
 799
 800
 801
 802/*
 803 * input level controls for VX222 Mic
 804 */
 805
 806/* Micro level is specified to be adjustable from -96dB to 63 dB (board coded 0x00 ... 318),
 807 * 318 = 210 + 36 + 36 + 36   (210 = +9dB variable) (3 * 36 = 3 steps of 18dB pre ampli)
 808 * as we will mute if less than -110dB, so let's simply use line input coded levels and add constant offset !
 809 */
 810#define V2_MICRO_LEVEL_RANGE        (318 - 255)
 811
 812static void vx2_set_input_level(struct snd_vx222 *chip)
 813{
 814	int i, miclevel, preamp;
 815	unsigned int data;
 816
 817	miclevel = chip->mic_level;
 818	miclevel += V2_MICRO_LEVEL_RANGE; /* add 318 - 0xff */
 819	preamp = 0;
 820        while (miclevel > 210) { /* limitation to +9dB of 3310 real gain */
 821		preamp++;	/* raise pre ampli + 18dB */
 822		miclevel -= (18 * 2);   /* lower level 18 dB (*2 because of 0.5 dB steps !) */
 823        }
 824	snd_assert(preamp < 4, return);
 825
 826	/* set pre-amp level */
 827	chip->regSELMIC &= ~MICRO_SELECT_PREAMPLI_MASK;
 828	chip->regSELMIC |= (preamp << MICRO_SELECT_PREAMPLI_OFFSET) & MICRO_SELECT_PREAMPLI_MASK;
 829	vx_outl(chip, SELMIC, chip->regSELMIC);
 830
 831	data = (unsigned int)miclevel << 16 |
 832		(unsigned int)chip->input_level[1] << 8 |
 833		(unsigned int)chip->input_level[0];
 834	vx_inl(chip, DATA); /* Activate input level programming */
 835
 836	/* We have to send 32 bits (4 x 8 bits) */
 837	for (i = 0; i < 32; i++, data <<= 1)
 838		vx_outl(chip, DATA, ((data & 0x80000000) ? VX_DATA_CODEC_MASK : 0));
 839
 840	vx_inl(chip, RUER); /* Terminate input level programming */
 841}
 842
 843
 844#define MIC_LEVEL_MAX	0xff
 845
 846/*
 847 * controls API for input levels
 848 */
 849
 850/* input levels */
 851static int vx_input_level_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
 852{
 853	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 854	uinfo->count = 2;
 855	uinfo->value.integer.min = 0;
 856	uinfo->value.integer.max = MIC_LEVEL_MAX;
 857	return 0;
 858}
 859
 860static int vx_input_level_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
 861{
 862	vx_core_t *_chip = snd_kcontrol_chip(kcontrol);
 863	struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
 864	down(&_chip->mixer_mutex);
 865	ucontrol->value.integer.value[0] = chip->input_level[0];
 866	ucontrol->value.integer.value[1] = chip->input_level[1];
 867	up(&_chip->mixer_mutex);
 868	return 0;
 869}
 870
 871static int vx_input_level_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
 872{
 873	vx_core_t *_chip = snd_kcontrol_chip(kcontrol);
 874	struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
 875	down(&_chip->mixer_mutex);
 876	if (chip->input_level[0] != ucontrol->value.integer.value[0] ||
 877	    chip->input_level[1] != ucontrol->value.integer.value[1]) {
 878		chip->input_level[0] = ucontrol->value.integer.value[0];
 879		chip->input_level[1] = ucontrol->value.integer.value[1];
 880		vx2_set_input_level(chip);
 881		up(&_chip->mixer_mutex);
 882		return 1;
 883	}
 884	up(&_chip->mixer_mutex);
 885	return 0;
 886}
 887
 888/* mic level */
 889static int vx_mic_level_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
 890{
 891	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 892	uinfo->count = 1;
 893	uinfo->value.integer.min = 0;
 894	uinfo->value.integer.max = MIC_LEVEL_MAX;
 895	return 0;
 896}
 897
 898static int vx_mic_level_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
 899{
 900	vx_core_t *_chip = snd_kcontrol_chip(kcontrol);
 901	struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
 902	ucontrol->value.integer.value[0] = chip->mic_level;
 903	return 0;
 904}
 905
 906static int vx_mic_level_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
 907{
 908	vx_core_t *_chip = snd_kcontrol_chip(kcontrol);
 909	struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
 910	down(&_chip->mixer_mutex);
 911	if (chip->mic_level != ucontrol->value.integer.value[0]) {
 912		chip->mic_level = ucontrol->value.integer.value[0];
 913		vx2_set_input_level(chip);
 914		up(&_chip->mixer_mutex);
 915		return 1;
 916	}
 917	up(&_chip->mixer_mutex);
 918	return 0;
 919}
 920
 921static snd_kcontrol_new_t vx_control_input_level = {
 922	.iface =	SNDRV_CTL_ELEM_IFACE_MIXER,
 923	.name =		"Capture Volume",
 924	.info =		vx_input_level_info,
 925	.get =		vx_input_level_get,
 926	.put =		vx_input_level_put,
 927};
 928
 929static snd_kcontrol_new_t vx_control_mic_level = {
 930	.iface =	SNDRV_CTL_ELEM_IFACE_MIXER,
 931	.name =		"Mic Capture Volume",
 932	.info =		vx_mic_level_info,
 933	.get =		vx_mic_level_get,
 934	.put =		vx_mic_level_put,
 935};
 936
 937/*
 938 * FIXME: compressor/limiter implementation is missing yet...
 939 */
 940
 941static int vx2_add_mic_controls(vx_core_t *_chip)
 942{
 943	struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
 944	int err;
 945
 946	if (_chip->type != VX_TYPE_MIC)
 947		return 0;
 948
 949	/* mute input levels */
 950	chip->input_level[0] = chip->input_level[1] = 0;
 951	chip->mic_level = 0;
 952	vx2_set_input_level(chip);
 953
 954	/* controls */
 955	if ((err = snd_ctl_add(_chip->card, snd_ctl_new1(&vx_control_input_level, chip))) < 0)
 956		return err;
 957	if ((err = snd_ctl_add(_chip->card, snd_ctl_new1(&vx_control_mic_level, chip))) < 0)
 958		return err;
 959
 960	return 0;
 961}
 962
 963
 964/*
 965 * callbacks
 966 */
 967struct snd_vx_ops vx222_ops = {
 968	.in8 = vx2_inb,
 969	.in32 = vx2_inl,
 970	.out8 = vx2_outb,
 971	.out32 = vx2_outl,
 972	.test_and_ack = vx2_test_and_ack,
 973	.validate_irq = vx2_validate_irq,
 974	.akm_write = vx2_write_akm,
 975	.reset_codec = vx2_reset_codec,
 976	.change_audio_source = vx2_change_audio_source,
 977	.set_clock_source = vx2_set_clock_source,
 978	.load_dsp = vx2_load_dsp,
 979	.reset_dsp = vx2_reset_dsp,
 980	.reset_board = vx2_reset_board,
 981	.dma_write = vx2_dma_write,
 982	.dma_read = vx2_dma_read,
 983	.add_controls = vx2_add_mic_controls,
 984};
 985
 986/* for old VX222 board */
 987struct snd_vx_ops vx222_old_ops = {
 988	.in8 = vx2_inb,
 989	.in32 = vx2_inl,
 990	.out8 = vx2_outb,
 991	.out32 = vx2_outl,
 992	.test_and_ack = vx2_test_and_ack,
 993	.validate_irq = vx2_validate_irq,
 994	.write_codec = vx2_old_write_codec_bit,
 995	.reset_codec = vx2_reset_codec,
 996	.change_audio_source = vx2_change_audio_source,
 997	.set_clock_source = vx2_set_clock_source,
 998	.load_dsp = vx2_load_dsp,
 999	.reset_dsp = vx2_reset_dsp,
1000	.reset_board = vx2_reset_board,
1001	.dma_write = vx2_dma_write,
1002	.dma_read = vx2_dma_read,
1003};
1004