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/sound/pci/vx222/vx222_ops.c

https://bitbucket.org/evzijst/gittest
C | 1004 lines | 696 code | 129 blank | 179 comment | 55 complexity | 884dd9c53aec00ae8c77b0ad225b5f40 MD5 | raw file
Possible License(s): CC-BY-SA-3.0, GPL-2.0, LGPL-2.0
  1. /*
  2. * Driver for Digigram VX222 V2/Mic soundcards
  3. *
  4. * VX222-specific low-level routines
  5. *
  6. * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include <sound/driver.h>
  23. #include <linux/delay.h>
  24. #include <linux/device.h>
  25. #include <linux/firmware.h>
  26. #include <sound/core.h>
  27. #include <sound/control.h>
  28. #include <asm/io.h>
  29. #include "vx222.h"
  30. static int vx2_reg_offset[VX_REG_MAX] = {
  31. [VX_ICR] = 0x00,
  32. [VX_CVR] = 0x04,
  33. [VX_ISR] = 0x08,
  34. [VX_IVR] = 0x0c,
  35. [VX_RXH] = 0x14,
  36. [VX_RXM] = 0x18,
  37. [VX_RXL] = 0x1c,
  38. [VX_DMA] = 0x10,
  39. [VX_CDSP] = 0x20,
  40. [VX_CFG] = 0x24,
  41. [VX_RUER] = 0x28,
  42. [VX_DATA] = 0x2c,
  43. [VX_STATUS] = 0x30,
  44. [VX_LOFREQ] = 0x34,
  45. [VX_HIFREQ] = 0x38,
  46. [VX_CSUER] = 0x3c,
  47. [VX_SELMIC] = 0x40,
  48. [VX_COMPOT] = 0x44, // Write: POTENTIOMETER ; Read: COMPRESSION LEVEL activate
  49. [VX_SCOMPR] = 0x48, // Read: COMPRESSION THRESHOLD activate
  50. [VX_GLIMIT] = 0x4c, // Read: LEVEL LIMITATION activate
  51. [VX_INTCSR] = 0x4c, // VX_INTCSR_REGISTER_OFFSET
  52. [VX_CNTRL] = 0x50, // VX_CNTRL_REGISTER_OFFSET
  53. [VX_GPIOC] = 0x54, // VX_GPIOC (new with PLX9030)
  54. };
  55. static int vx2_reg_index[VX_REG_MAX] = {
  56. [VX_ICR] = 1,
  57. [VX_CVR] = 1,
  58. [VX_ISR] = 1,
  59. [VX_IVR] = 1,
  60. [VX_RXH] = 1,
  61. [VX_RXM] = 1,
  62. [VX_RXL] = 1,
  63. [VX_DMA] = 1,
  64. [VX_CDSP] = 1,
  65. [VX_CFG] = 1,
  66. [VX_RUER] = 1,
  67. [VX_DATA] = 1,
  68. [VX_STATUS] = 1,
  69. [VX_LOFREQ] = 1,
  70. [VX_HIFREQ] = 1,
  71. [VX_CSUER] = 1,
  72. [VX_SELMIC] = 1,
  73. [VX_COMPOT] = 1,
  74. [VX_SCOMPR] = 1,
  75. [VX_GLIMIT] = 1,
  76. [VX_INTCSR] = 0, /* on the PLX */
  77. [VX_CNTRL] = 0, /* on the PLX */
  78. [VX_GPIOC] = 0, /* on the PLX */
  79. };
  80. inline static unsigned long vx2_reg_addr(vx_core_t *_chip, int reg)
  81. {
  82. struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
  83. return chip->port[vx2_reg_index[reg]] + vx2_reg_offset[reg];
  84. }
  85. /**
  86. * snd_vx_inb - read a byte from the register
  87. * @offset: register enum
  88. */
  89. static unsigned char vx2_inb(vx_core_t *chip, int offset)
  90. {
  91. return inb(vx2_reg_addr(chip, offset));
  92. }
  93. /**
  94. * snd_vx_outb - write a byte on the register
  95. * @offset: the register offset
  96. * @val: the value to write
  97. */
  98. static void vx2_outb(vx_core_t *chip, int offset, unsigned char val)
  99. {
  100. outb(val, vx2_reg_addr(chip, offset));
  101. //printk("outb: %x -> %x\n", val, vx2_reg_addr(chip, offset));
  102. }
  103. /**
  104. * snd_vx_inl - read a 32bit word from the register
  105. * @offset: register enum
  106. */
  107. static unsigned int vx2_inl(vx_core_t *chip, int offset)
  108. {
  109. return inl(vx2_reg_addr(chip, offset));
  110. }
  111. /**
  112. * snd_vx_outl - write a 32bit word on the register
  113. * @offset: the register enum
  114. * @val: the value to write
  115. */
  116. static void vx2_outl(vx_core_t *chip, int offset, unsigned int val)
  117. {
  118. // printk("outl: %x -> %x\n", val, vx2_reg_addr(chip, offset));
  119. outl(val, vx2_reg_addr(chip, offset));
  120. }
  121. /*
  122. * redefine macros to call directly
  123. */
  124. #undef vx_inb
  125. #define vx_inb(chip,reg) vx2_inb((vx_core_t*)(chip), VX_##reg)
  126. #undef vx_outb
  127. #define vx_outb(chip,reg,val) vx2_outb((vx_core_t*)(chip), VX_##reg, val)
  128. #undef vx_inl
  129. #define vx_inl(chip,reg) vx2_inl((vx_core_t*)(chip), VX_##reg)
  130. #undef vx_outl
  131. #define vx_outl(chip,reg,val) vx2_outl((vx_core_t*)(chip), VX_##reg, val)
  132. /*
  133. * vx_reset_dsp - reset the DSP
  134. */
  135. #define XX_DSP_RESET_WAIT_TIME 2 /* ms */
  136. static void vx2_reset_dsp(vx_core_t *_chip)
  137. {
  138. struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
  139. /* set the reset dsp bit to 0 */
  140. vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_DSP_RESET_MASK);
  141. snd_vx_delay(_chip, XX_DSP_RESET_WAIT_TIME);
  142. chip->regCDSP |= VX_CDSP_DSP_RESET_MASK;
  143. /* set the reset dsp bit to 1 */
  144. vx_outl(chip, CDSP, chip->regCDSP);
  145. }
  146. static int vx2_test_xilinx(vx_core_t *_chip)
  147. {
  148. struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
  149. unsigned int data;
  150. snd_printdd("testing xilinx...\n");
  151. /* This test uses several write/read sequences on TEST0 and TEST1 bits
  152. * to figure out whever or not the xilinx was correctly loaded
  153. */
  154. /* We write 1 on CDSP.TEST0. We should get 0 on STATUS.TEST0. */
  155. vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST0_MASK);
  156. vx_inl(chip, ISR);
  157. data = vx_inl(chip, STATUS);
  158. if ((data & VX_STATUS_VAL_TEST0_MASK) == VX_STATUS_VAL_TEST0_MASK) {
  159. snd_printdd("bad!\n");
  160. return -ENODEV;
  161. }
  162. /* We write 0 on CDSP.TEST0. We should get 1 on STATUS.TEST0. */
  163. vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST0_MASK);
  164. vx_inl(chip, ISR);
  165. data = vx_inl(chip, STATUS);
  166. if (! (data & VX_STATUS_VAL_TEST0_MASK)) {
  167. snd_printdd("bad! #2\n");
  168. return -ENODEV;
  169. }
  170. if (_chip->type == VX_TYPE_BOARD) {
  171. /* not implemented on VX_2_BOARDS */
  172. /* We write 1 on CDSP.TEST1. We should get 0 on STATUS.TEST1. */
  173. vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST1_MASK);
  174. vx_inl(chip, ISR);
  175. data = vx_inl(chip, STATUS);
  176. if ((data & VX_STATUS_VAL_TEST1_MASK) == VX_STATUS_VAL_TEST1_MASK) {
  177. snd_printdd("bad! #3\n");
  178. return -ENODEV;
  179. }
  180. /* We write 0 on CDSP.TEST1. We should get 1 on STATUS.TEST1. */
  181. vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST1_MASK);
  182. vx_inl(chip, ISR);
  183. data = vx_inl(chip, STATUS);
  184. if (! (data & VX_STATUS_VAL_TEST1_MASK)) {
  185. snd_printdd("bad! #4\n");
  186. return -ENODEV;
  187. }
  188. }
  189. snd_printdd("ok, xilinx fine.\n");
  190. return 0;
  191. }
  192. /**
  193. * vx_setup_pseudo_dma - set up the pseudo dma read/write mode.
  194. * @do_write: 0 = read, 1 = set up for DMA write
  195. */
  196. static void vx2_setup_pseudo_dma(vx_core_t *chip, int do_write)
  197. {
  198. /* Interrupt mode and HREQ pin enabled for host transmit data transfers
  199. * (in case of the use of the pseudo-dma facility).
  200. */
  201. vx_outl(chip, ICR, do_write ? ICR_TREQ : ICR_RREQ);
  202. /* Reset the pseudo-dma register (in case of the use of the
  203. * pseudo-dma facility).
  204. */
  205. vx_outl(chip, RESET_DMA, 0);
  206. }
  207. /*
  208. * vx_release_pseudo_dma - disable the pseudo-DMA mode
  209. */
  210. inline static void vx2_release_pseudo_dma(vx_core_t *chip)
  211. {
  212. /* HREQ pin disabled. */
  213. vx_outl(chip, ICR, 0);
  214. }
  215. /* pseudo-dma write */
  216. static void vx2_dma_write(vx_core_t *chip, snd_pcm_runtime_t *runtime,
  217. vx_pipe_t *pipe, int count)
  218. {
  219. unsigned long port = vx2_reg_addr(chip, VX_DMA);
  220. int offset = pipe->hw_ptr;
  221. u32 *addr = (u32 *)(runtime->dma_area + offset);
  222. snd_assert(count % 4 == 0, return);
  223. vx2_setup_pseudo_dma(chip, 1);
  224. /* Transfer using pseudo-dma.
  225. */
  226. if (offset + count > pipe->buffer_bytes) {
  227. int length = pipe->buffer_bytes - offset;
  228. count -= length;
  229. length >>= 2; /* in 32bit words */
  230. /* Transfer using pseudo-dma. */
  231. while (length-- > 0) {
  232. outl(cpu_to_le32(*addr), port);
  233. addr++;
  234. }
  235. addr = (u32 *)runtime->dma_area;
  236. pipe->hw_ptr = 0;
  237. }
  238. pipe->hw_ptr += count;
  239. count >>= 2; /* in 32bit words */
  240. /* Transfer using pseudo-dma. */
  241. while (count-- > 0) {
  242. outl(cpu_to_le32(*addr), port);
  243. addr++;
  244. }
  245. vx2_release_pseudo_dma(chip);
  246. }
  247. /* pseudo dma read */
  248. static void vx2_dma_read(vx_core_t *chip, snd_pcm_runtime_t *runtime,
  249. vx_pipe_t *pipe, int count)
  250. {
  251. int offset = pipe->hw_ptr;
  252. u32 *addr = (u32 *)(runtime->dma_area + offset);
  253. unsigned long port = vx2_reg_addr(chip, VX_DMA);
  254. snd_assert(count % 4 == 0, return);
  255. vx2_setup_pseudo_dma(chip, 0);
  256. /* Transfer using pseudo-dma.
  257. */
  258. if (offset + count > pipe->buffer_bytes) {
  259. int length = pipe->buffer_bytes - offset;
  260. count -= length;
  261. length >>= 2; /* in 32bit words */
  262. /* Transfer using pseudo-dma. */
  263. while (length-- > 0)
  264. *addr++ = le32_to_cpu(inl(port));
  265. addr = (u32 *)runtime->dma_area;
  266. pipe->hw_ptr = 0;
  267. }
  268. pipe->hw_ptr += count;
  269. count >>= 2; /* in 32bit words */
  270. /* Transfer using pseudo-dma. */
  271. while (count-- > 0)
  272. *addr++ = le32_to_cpu(inl(port));
  273. vx2_release_pseudo_dma(chip);
  274. }
  275. #define VX_XILINX_RESET_MASK 0x40000000
  276. #define VX_USERBIT0_MASK 0x00000004
  277. #define VX_USERBIT1_MASK 0x00000020
  278. #define VX_CNTRL_REGISTER_VALUE 0x00172012
  279. /*
  280. * transfer counts bits to PLX
  281. */
  282. static int put_xilinx_data(vx_core_t *chip, unsigned int port, unsigned int counts, unsigned char data)
  283. {
  284. unsigned int i;
  285. for (i = 0; i < counts; i++) {
  286. unsigned int val;
  287. /* set the clock bit to 0. */
  288. val = VX_CNTRL_REGISTER_VALUE & ~VX_USERBIT0_MASK;
  289. vx2_outl(chip, port, val);
  290. vx2_inl(chip, port);
  291. udelay(1);
  292. if (data & (1 << i))
  293. val |= VX_USERBIT1_MASK;
  294. else
  295. val &= ~VX_USERBIT1_MASK;
  296. vx2_outl(chip, port, val);
  297. vx2_inl(chip, port);
  298. /* set the clock bit to 1. */
  299. val |= VX_USERBIT0_MASK;
  300. vx2_outl(chip, port, val);
  301. vx2_inl(chip, port);
  302. udelay(1);
  303. }
  304. return 0;
  305. }
  306. /*
  307. * load the xilinx image
  308. */
  309. static int vx2_load_xilinx_binary(vx_core_t *chip, const struct firmware *xilinx)
  310. {
  311. unsigned int i;
  312. unsigned int port;
  313. unsigned char *image;
  314. /* XILINX reset (wait at least 1 milisecond between reset on and off). */
  315. vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE | VX_XILINX_RESET_MASK);
  316. vx_inl(chip, CNTRL);
  317. snd_vx_delay(chip, 10);
  318. vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE);
  319. vx_inl(chip, CNTRL);
  320. snd_vx_delay(chip, 10);
  321. if (chip->type == VX_TYPE_BOARD)
  322. port = VX_CNTRL;
  323. else
  324. port = VX_GPIOC; /* VX222 V2 and VX222_MIC_BOARD with new PLX9030 use this register */
  325. image = xilinx->data;
  326. for (i = 0; i < xilinx->size; i++, image++) {
  327. if (put_xilinx_data(chip, port, 8, *image) < 0)
  328. return -EINVAL;
  329. /* don't take too much time in this loop... */
  330. cond_resched();
  331. }
  332. put_xilinx_data(chip, port, 4, 0xff); /* end signature */
  333. snd_vx_delay(chip, 200);
  334. /* test after loading (is buggy with VX222) */
  335. if (chip->type != VX_TYPE_BOARD) {
  336. /* Test if load successful: test bit 8 of register GPIOC (VX222: use CNTRL) ! */
  337. i = vx_inl(chip, GPIOC);
  338. if (i & 0x0100)
  339. return 0;
  340. snd_printk(KERN_ERR "vx222: xilinx test failed after load, GPIOC=0x%x\n", i);
  341. return -EINVAL;
  342. }
  343. return 0;
  344. }
  345. /*
  346. * load the boot/dsp images
  347. */
  348. static int vx2_load_dsp(vx_core_t *vx, int index, const struct firmware *dsp)
  349. {
  350. int err;
  351. switch (index) {
  352. case 1:
  353. /* xilinx image */
  354. if ((err = vx2_load_xilinx_binary(vx, dsp)) < 0)
  355. return err;
  356. if ((err = vx2_test_xilinx(vx)) < 0)
  357. return err;
  358. return 0;
  359. case 2:
  360. /* DSP boot */
  361. return snd_vx_dsp_boot(vx, dsp);
  362. case 3:
  363. /* DSP image */
  364. return snd_vx_dsp_load(vx, dsp);
  365. default:
  366. snd_BUG();
  367. return -EINVAL;
  368. }
  369. }
  370. /*
  371. * vx_test_and_ack - test and acknowledge interrupt
  372. *
  373. * called from irq hander, too
  374. *
  375. * spinlock held!
  376. */
  377. static int vx2_test_and_ack(vx_core_t *chip)
  378. {
  379. /* not booted yet? */
  380. if (! (chip->chip_status & VX_STAT_XILINX_LOADED))
  381. return -ENXIO;
  382. if (! (vx_inl(chip, STATUS) & VX_STATUS_MEMIRQ_MASK))
  383. return -EIO;
  384. /* ok, interrupts generated, now ack it */
  385. /* set ACQUIT bit up and down */
  386. vx_outl(chip, STATUS, 0);
  387. /* useless read just to spend some time and maintain
  388. * the ACQUIT signal up for a while ( a bus cycle )
  389. */
  390. vx_inl(chip, STATUS);
  391. /* ack */
  392. vx_outl(chip, STATUS, VX_STATUS_MEMIRQ_MASK);
  393. /* useless read just to spend some time and maintain
  394. * the ACQUIT signal up for a while ( a bus cycle ) */
  395. vx_inl(chip, STATUS);
  396. /* clear */
  397. vx_outl(chip, STATUS, 0);
  398. return 0;
  399. }
  400. /*
  401. * vx_validate_irq - enable/disable IRQ
  402. */
  403. static void vx2_validate_irq(vx_core_t *_chip, int enable)
  404. {
  405. struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
  406. /* Set the interrupt enable bit to 1 in CDSP register */
  407. if (enable) {
  408. /* Set the PCI interrupt enable bit to 1.*/
  409. vx_outl(chip, INTCSR, VX_INTCSR_VALUE|VX_PCI_INTERRUPT_MASK);
  410. chip->regCDSP |= VX_CDSP_VALID_IRQ_MASK;
  411. } else {
  412. /* Set the PCI interrupt enable bit to 0. */
  413. vx_outl(chip, INTCSR, VX_INTCSR_VALUE&~VX_PCI_INTERRUPT_MASK);
  414. chip->regCDSP &= ~VX_CDSP_VALID_IRQ_MASK;
  415. }
  416. vx_outl(chip, CDSP, chip->regCDSP);
  417. }
  418. /*
  419. * write an AKM codec data (24bit)
  420. */
  421. static void vx2_write_codec_reg(vx_core_t *chip, unsigned int data)
  422. {
  423. unsigned int i;
  424. vx_inl(chip, HIFREQ);
  425. /* We have to send 24 bits (3 x 8 bits). Start with most signif. Bit */
  426. for (i = 0; i < 24; i++, data <<= 1)
  427. vx_outl(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0));
  428. /* Terminate access to codec registers */
  429. vx_inl(chip, RUER);
  430. }
  431. #define AKM_CODEC_POWER_CONTROL_CMD 0xA007
  432. #define AKM_CODEC_RESET_ON_CMD 0xA100
  433. #define AKM_CODEC_RESET_OFF_CMD 0xA103
  434. #define AKM_CODEC_CLOCK_FORMAT_CMD 0xA240
  435. #define AKM_CODEC_MUTE_CMD 0xA38D
  436. #define AKM_CODEC_UNMUTE_CMD 0xA30D
  437. #define AKM_CODEC_LEFT_LEVEL_CMD 0xA400
  438. #define AKM_CODEC_RIGHT_LEVEL_CMD 0xA500
  439. static const u8 vx2_akm_gains_lut[VX2_AKM_LEVEL_MAX+1] = {
  440. 0x7f, // [000] = +0.000 dB -> AKM(0x7f) = +0.000 dB error(+0.000 dB)
  441. 0x7d, // [001] = -0.500 dB -> AKM(0x7d) = -0.572 dB error(-0.072 dB)
  442. 0x7c, // [002] = -1.000 dB -> AKM(0x7c) = -0.873 dB error(+0.127 dB)
  443. 0x7a, // [003] = -1.500 dB -> AKM(0x7a) = -1.508 dB error(-0.008 dB)
  444. 0x79, // [004] = -2.000 dB -> AKM(0x79) = -1.844 dB error(+0.156 dB)
  445. 0x77, // [005] = -2.500 dB -> AKM(0x77) = -2.557 dB error(-0.057 dB)
  446. 0x76, // [006] = -3.000 dB -> AKM(0x76) = -2.937 dB error(+0.063 dB)
  447. 0x75, // [007] = -3.500 dB -> AKM(0x75) = -3.334 dB error(+0.166 dB)
  448. 0x73, // [008] = -4.000 dB -> AKM(0x73) = -4.188 dB error(-0.188 dB)
  449. 0x72, // [009] = -4.500 dB -> AKM(0x72) = -4.648 dB error(-0.148 dB)
  450. 0x71, // [010] = -5.000 dB -> AKM(0x71) = -5.134 dB error(-0.134 dB)
  451. 0x70, // [011] = -5.500 dB -> AKM(0x70) = -5.649 dB error(-0.149 dB)
  452. 0x6f, // [012] = -6.000 dB -> AKM(0x6f) = -6.056 dB error(-0.056 dB)
  453. 0x6d, // [013] = -6.500 dB -> AKM(0x6d) = -6.631 dB error(-0.131 dB)
  454. 0x6c, // [014] = -7.000 dB -> AKM(0x6c) = -6.933 dB error(+0.067 dB)
  455. 0x6a, // [015] = -7.500 dB -> AKM(0x6a) = -7.571 dB error(-0.071 dB)
  456. 0x69, // [016] = -8.000 dB -> AKM(0x69) = -7.909 dB error(+0.091 dB)
  457. 0x67, // [017] = -8.500 dB -> AKM(0x67) = -8.626 dB error(-0.126 dB)
  458. 0x66, // [018] = -9.000 dB -> AKM(0x66) = -9.008 dB error(-0.008 dB)
  459. 0x65, // [019] = -9.500 dB -> AKM(0x65) = -9.407 dB error(+0.093 dB)
  460. 0x64, // [020] = -10.000 dB -> AKM(0x64) = -9.826 dB error(+0.174 dB)
  461. 0x62, // [021] = -10.500 dB -> AKM(0x62) = -10.730 dB error(-0.230 dB)
  462. 0x61, // [022] = -11.000 dB -> AKM(0x61) = -11.219 dB error(-0.219 dB)
  463. 0x60, // [023] = -11.500 dB -> AKM(0x60) = -11.738 dB error(-0.238 dB)
  464. 0x5f, // [024] = -12.000 dB -> AKM(0x5f) = -12.149 dB error(-0.149 dB)
  465. 0x5e, // [025] = -12.500 dB -> AKM(0x5e) = -12.434 dB error(+0.066 dB)
  466. 0x5c, // [026] = -13.000 dB -> AKM(0x5c) = -13.033 dB error(-0.033 dB)
  467. 0x5b, // [027] = -13.500 dB -> AKM(0x5b) = -13.350 dB error(+0.150 dB)
  468. 0x59, // [028] = -14.000 dB -> AKM(0x59) = -14.018 dB error(-0.018 dB)
  469. 0x58, // [029] = -14.500 dB -> AKM(0x58) = -14.373 dB error(+0.127 dB)
  470. 0x56, // [030] = -15.000 dB -> AKM(0x56) = -15.130 dB error(-0.130 dB)
  471. 0x55, // [031] = -15.500 dB -> AKM(0x55) = -15.534 dB error(-0.034 dB)
  472. 0x54, // [032] = -16.000 dB -> AKM(0x54) = -15.958 dB error(+0.042 dB)
  473. 0x53, // [033] = -16.500 dB -> AKM(0x53) = -16.404 dB error(+0.096 dB)
  474. 0x52, // [034] = -17.000 dB -> AKM(0x52) = -16.874 dB error(+0.126 dB)
  475. 0x51, // [035] = -17.500 dB -> AKM(0x51) = -17.371 dB error(+0.129 dB)
  476. 0x50, // [036] = -18.000 dB -> AKM(0x50) = -17.898 dB error(+0.102 dB)
  477. 0x4e, // [037] = -18.500 dB -> AKM(0x4e) = -18.605 dB error(-0.105 dB)
  478. 0x4d, // [038] = -19.000 dB -> AKM(0x4d) = -18.905 dB error(+0.095 dB)
  479. 0x4b, // [039] = -19.500 dB -> AKM(0x4b) = -19.538 dB error(-0.038 dB)
  480. 0x4a, // [040] = -20.000 dB -> AKM(0x4a) = -19.872 dB error(+0.128 dB)
  481. 0x48, // [041] = -20.500 dB -> AKM(0x48) = -20.583 dB error(-0.083 dB)
  482. 0x47, // [042] = -21.000 dB -> AKM(0x47) = -20.961 dB error(+0.039 dB)
  483. 0x46, // [043] = -21.500 dB -> AKM(0x46) = -21.356 dB error(+0.144 dB)
  484. 0x44, // [044] = -22.000 dB -> AKM(0x44) = -22.206 dB error(-0.206 dB)
  485. 0x43, // [045] = -22.500 dB -> AKM(0x43) = -22.664 dB error(-0.164 dB)
  486. 0x42, // [046] = -23.000 dB -> AKM(0x42) = -23.147 dB error(-0.147 dB)
  487. 0x41, // [047] = -23.500 dB -> AKM(0x41) = -23.659 dB error(-0.159 dB)
  488. 0x40, // [048] = -24.000 dB -> AKM(0x40) = -24.203 dB error(-0.203 dB)
  489. 0x3f, // [049] = -24.500 dB -> AKM(0x3f) = -24.635 dB error(-0.135 dB)
  490. 0x3e, // [050] = -25.000 dB -> AKM(0x3e) = -24.935 dB error(+0.065 dB)
  491. 0x3c, // [051] = -25.500 dB -> AKM(0x3c) = -25.569 dB error(-0.069 dB)
  492. 0x3b, // [052] = -26.000 dB -> AKM(0x3b) = -25.904 dB error(+0.096 dB)
  493. 0x39, // [053] = -26.500 dB -> AKM(0x39) = -26.615 dB error(-0.115 dB)
  494. 0x38, // [054] = -27.000 dB -> AKM(0x38) = -26.994 dB error(+0.006 dB)
  495. 0x37, // [055] = -27.500 dB -> AKM(0x37) = -27.390 dB error(+0.110 dB)
  496. 0x36, // [056] = -28.000 dB -> AKM(0x36) = -27.804 dB error(+0.196 dB)
  497. 0x34, // [057] = -28.500 dB -> AKM(0x34) = -28.699 dB error(-0.199 dB)
  498. 0x33, // [058] = -29.000 dB -> AKM(0x33) = -29.183 dB error(-0.183 dB)
  499. 0x32, // [059] = -29.500 dB -> AKM(0x32) = -29.696 dB error(-0.196 dB)
  500. 0x31, // [060] = -30.000 dB -> AKM(0x31) = -30.241 dB error(-0.241 dB)
  501. 0x31, // [061] = -30.500 dB -> AKM(0x31) = -30.241 dB error(+0.259 dB)
  502. 0x30, // [062] = -31.000 dB -> AKM(0x30) = -30.823 dB error(+0.177 dB)
  503. 0x2e, // [063] = -31.500 dB -> AKM(0x2e) = -31.610 dB error(-0.110 dB)
  504. 0x2d, // [064] = -32.000 dB -> AKM(0x2d) = -31.945 dB error(+0.055 dB)
  505. 0x2b, // [065] = -32.500 dB -> AKM(0x2b) = -32.659 dB error(-0.159 dB)
  506. 0x2a, // [066] = -33.000 dB -> AKM(0x2a) = -33.038 dB error(-0.038 dB)
  507. 0x29, // [067] = -33.500 dB -> AKM(0x29) = -33.435 dB error(+0.065 dB)
  508. 0x28, // [068] = -34.000 dB -> AKM(0x28) = -33.852 dB error(+0.148 dB)
  509. 0x27, // [069] = -34.500 dB -> AKM(0x27) = -34.289 dB error(+0.211 dB)
  510. 0x25, // [070] = -35.000 dB -> AKM(0x25) = -35.235 dB error(-0.235 dB)
  511. 0x24, // [071] = -35.500 dB -> AKM(0x24) = -35.750 dB error(-0.250 dB)
  512. 0x24, // [072] = -36.000 dB -> AKM(0x24) = -35.750 dB error(+0.250 dB)
  513. 0x23, // [073] = -36.500 dB -> AKM(0x23) = -36.297 dB error(+0.203 dB)
  514. 0x22, // [074] = -37.000 dB -> AKM(0x22) = -36.881 dB error(+0.119 dB)
  515. 0x21, // [075] = -37.500 dB -> AKM(0x21) = -37.508 dB error(-0.008 dB)
  516. 0x20, // [076] = -38.000 dB -> AKM(0x20) = -38.183 dB error(-0.183 dB)
  517. 0x1f, // [077] = -38.500 dB -> AKM(0x1f) = -38.726 dB error(-0.226 dB)
  518. 0x1e, // [078] = -39.000 dB -> AKM(0x1e) = -39.108 dB error(-0.108 dB)
  519. 0x1d, // [079] = -39.500 dB -> AKM(0x1d) = -39.507 dB error(-0.007 dB)
  520. 0x1c, // [080] = -40.000 dB -> AKM(0x1c) = -39.926 dB error(+0.074 dB)
  521. 0x1b, // [081] = -40.500 dB -> AKM(0x1b) = -40.366 dB error(+0.134 dB)
  522. 0x1a, // [082] = -41.000 dB -> AKM(0x1a) = -40.829 dB error(+0.171 dB)
  523. 0x19, // [083] = -41.500 dB -> AKM(0x19) = -41.318 dB error(+0.182 dB)
  524. 0x18, // [084] = -42.000 dB -> AKM(0x18) = -41.837 dB error(+0.163 dB)
  525. 0x17, // [085] = -42.500 dB -> AKM(0x17) = -42.389 dB error(+0.111 dB)
  526. 0x16, // [086] = -43.000 dB -> AKM(0x16) = -42.978 dB error(+0.022 dB)
  527. 0x15, // [087] = -43.500 dB -> AKM(0x15) = -43.610 dB error(-0.110 dB)
  528. 0x14, // [088] = -44.000 dB -> AKM(0x14) = -44.291 dB error(-0.291 dB)
  529. 0x14, // [089] = -44.500 dB -> AKM(0x14) = -44.291 dB error(+0.209 dB)
  530. 0x13, // [090] = -45.000 dB -> AKM(0x13) = -45.031 dB error(-0.031 dB)
  531. 0x12, // [091] = -45.500 dB -> AKM(0x12) = -45.840 dB error(-0.340 dB)
  532. 0x12, // [092] = -46.000 dB -> AKM(0x12) = -45.840 dB error(+0.160 dB)
  533. 0x11, // [093] = -46.500 dB -> AKM(0x11) = -46.731 dB error(-0.231 dB)
  534. 0x11, // [094] = -47.000 dB -> AKM(0x11) = -46.731 dB error(+0.269 dB)
  535. 0x10, // [095] = -47.500 dB -> AKM(0x10) = -47.725 dB error(-0.225 dB)
  536. 0x10, // [096] = -48.000 dB -> AKM(0x10) = -47.725 dB error(+0.275 dB)
  537. 0x0f, // [097] = -48.500 dB -> AKM(0x0f) = -48.553 dB error(-0.053 dB)
  538. 0x0e, // [098] = -49.000 dB -> AKM(0x0e) = -49.152 dB error(-0.152 dB)
  539. 0x0d, // [099] = -49.500 dB -> AKM(0x0d) = -49.796 dB error(-0.296 dB)
  540. 0x0d, // [100] = -50.000 dB -> AKM(0x0d) = -49.796 dB error(+0.204 dB)
  541. 0x0c, // [101] = -50.500 dB -> AKM(0x0c) = -50.491 dB error(+0.009 dB)
  542. 0x0b, // [102] = -51.000 dB -> AKM(0x0b) = -51.247 dB error(-0.247 dB)
  543. 0x0b, // [103] = -51.500 dB -> AKM(0x0b) = -51.247 dB error(+0.253 dB)
  544. 0x0a, // [104] = -52.000 dB -> AKM(0x0a) = -52.075 dB error(-0.075 dB)
  545. 0x0a, // [105] = -52.500 dB -> AKM(0x0a) = -52.075 dB error(+0.425 dB)
  546. 0x09, // [106] = -53.000 dB -> AKM(0x09) = -52.990 dB error(+0.010 dB)
  547. 0x09, // [107] = -53.500 dB -> AKM(0x09) = -52.990 dB error(+0.510 dB)
  548. 0x08, // [108] = -54.000 dB -> AKM(0x08) = -54.013 dB error(-0.013 dB)
  549. 0x08, // [109] = -54.500 dB -> AKM(0x08) = -54.013 dB error(+0.487 dB)
  550. 0x07, // [110] = -55.000 dB -> AKM(0x07) = -55.173 dB error(-0.173 dB)
  551. 0x07, // [111] = -55.500 dB -> AKM(0x07) = -55.173 dB error(+0.327 dB)
  552. 0x06, // [112] = -56.000 dB -> AKM(0x06) = -56.512 dB error(-0.512 dB)
  553. 0x06, // [113] = -56.500 dB -> AKM(0x06) = -56.512 dB error(-0.012 dB)
  554. 0x06, // [114] = -57.000 dB -> AKM(0x06) = -56.512 dB error(+0.488 dB)
  555. 0x05, // [115] = -57.500 dB -> AKM(0x05) = -58.095 dB error(-0.595 dB)
  556. 0x05, // [116] = -58.000 dB -> AKM(0x05) = -58.095 dB error(-0.095 dB)
  557. 0x05, // [117] = -58.500 dB -> AKM(0x05) = -58.095 dB error(+0.405 dB)
  558. 0x05, // [118] = -59.000 dB -> AKM(0x05) = -58.095 dB error(+0.905 dB)
  559. 0x04, // [119] = -59.500 dB -> AKM(0x04) = -60.034 dB error(-0.534 dB)
  560. 0x04, // [120] = -60.000 dB -> AKM(0x04) = -60.034 dB error(-0.034 dB)
  561. 0x04, // [121] = -60.500 dB -> AKM(0x04) = -60.034 dB error(+0.466 dB)
  562. 0x04, // [122] = -61.000 dB -> AKM(0x04) = -60.034 dB error(+0.966 dB)
  563. 0x03, // [123] = -61.500 dB -> AKM(0x03) = -62.532 dB error(-1.032 dB)
  564. 0x03, // [124] = -62.000 dB -> AKM(0x03) = -62.532 dB error(-0.532 dB)
  565. 0x03, // [125] = -62.500 dB -> AKM(0x03) = -62.532 dB error(-0.032 dB)
  566. 0x03, // [126] = -63.000 dB -> AKM(0x03) = -62.532 dB error(+0.468 dB)
  567. 0x03, // [127] = -63.500 dB -> AKM(0x03) = -62.532 dB error(+0.968 dB)
  568. 0x03, // [128] = -64.000 dB -> AKM(0x03) = -62.532 dB error(+1.468 dB)
  569. 0x02, // [129] = -64.500 dB -> AKM(0x02) = -66.054 dB error(-1.554 dB)
  570. 0x02, // [130] = -65.000 dB -> AKM(0x02) = -66.054 dB error(-1.054 dB)
  571. 0x02, // [131] = -65.500 dB -> AKM(0x02) = -66.054 dB error(-0.554 dB)
  572. 0x02, // [132] = -66.000 dB -> AKM(0x02) = -66.054 dB error(-0.054 dB)
  573. 0x02, // [133] = -66.500 dB -> AKM(0x02) = -66.054 dB error(+0.446 dB)
  574. 0x02, // [134] = -67.000 dB -> AKM(0x02) = -66.054 dB error(+0.946 dB)
  575. 0x02, // [135] = -67.500 dB -> AKM(0x02) = -66.054 dB error(+1.446 dB)
  576. 0x02, // [136] = -68.000 dB -> AKM(0x02) = -66.054 dB error(+1.946 dB)
  577. 0x02, // [137] = -68.500 dB -> AKM(0x02) = -66.054 dB error(+2.446 dB)
  578. 0x02, // [138] = -69.000 dB -> AKM(0x02) = -66.054 dB error(+2.946 dB)
  579. 0x01, // [139] = -69.500 dB -> AKM(0x01) = -72.075 dB error(-2.575 dB)
  580. 0x01, // [140] = -70.000 dB -> AKM(0x01) = -72.075 dB error(-2.075 dB)
  581. 0x01, // [141] = -70.500 dB -> AKM(0x01) = -72.075 dB error(-1.575 dB)
  582. 0x01, // [142] = -71.000 dB -> AKM(0x01) = -72.075 dB error(-1.075 dB)
  583. 0x01, // [143] = -71.500 dB -> AKM(0x01) = -72.075 dB error(-0.575 dB)
  584. 0x01, // [144] = -72.000 dB -> AKM(0x01) = -72.075 dB error(-0.075 dB)
  585. 0x01, // [145] = -72.500 dB -> AKM(0x01) = -72.075 dB error(+0.425 dB)
  586. 0x01, // [146] = -73.000 dB -> AKM(0x01) = -72.075 dB error(+0.925 dB)
  587. 0x00}; // [147] = -73.500 dB -> AKM(0x00) = mute error(+infini)
  588. /*
  589. * pseudo-codec write entry
  590. */
  591. static void vx2_write_akm(vx_core_t *chip, int reg, unsigned int data)
  592. {
  593. unsigned int val;
  594. if (reg == XX_CODEC_DAC_CONTROL_REGISTER) {
  595. vx2_write_codec_reg(chip, data ? AKM_CODEC_MUTE_CMD : AKM_CODEC_UNMUTE_CMD);
  596. return;
  597. }
  598. /* `data' is a value between 0x0 and VX2_AKM_LEVEL_MAX = 0x093, in the case of the AKM codecs, we need
  599. a look up table, as there is no linear matching between the driver codec values
  600. and the real dBu value
  601. */
  602. snd_assert(data < sizeof(vx2_akm_gains_lut), return);
  603. switch (reg) {
  604. case XX_CODEC_LEVEL_LEFT_REGISTER:
  605. val = AKM_CODEC_LEFT_LEVEL_CMD;
  606. break;
  607. case XX_CODEC_LEVEL_RIGHT_REGISTER:
  608. val = AKM_CODEC_RIGHT_LEVEL_CMD;
  609. break;
  610. default:
  611. snd_BUG();
  612. return;
  613. }
  614. val |= vx2_akm_gains_lut[data];
  615. vx2_write_codec_reg(chip, val);
  616. }
  617. /*
  618. * write codec bit for old VX222 board
  619. */
  620. static void vx2_old_write_codec_bit(vx_core_t *chip, int codec, unsigned int data)
  621. {
  622. int i;
  623. /* activate access to codec registers */
  624. vx_inl(chip, HIFREQ);
  625. for (i = 0; i < 24; i++, data <<= 1)
  626. vx_outl(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0));
  627. /* Terminate access to codec registers */
  628. vx_inl(chip, RUER);
  629. }
  630. /*
  631. * reset codec bit
  632. */
  633. static void vx2_reset_codec(vx_core_t *_chip)
  634. {
  635. struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
  636. /* Set the reset CODEC bit to 0. */
  637. vx_outl(chip, CDSP, chip->regCDSP &~ VX_CDSP_CODEC_RESET_MASK);
  638. vx_inl(chip, CDSP);
  639. snd_vx_delay(_chip, 10);
  640. /* Set the reset CODEC bit to 1. */
  641. chip->regCDSP |= VX_CDSP_CODEC_RESET_MASK;
  642. vx_outl(chip, CDSP, chip->regCDSP);
  643. vx_inl(chip, CDSP);
  644. if (_chip->type == VX_TYPE_BOARD) {
  645. snd_vx_delay(_chip, 1);
  646. return;
  647. }
  648. snd_vx_delay(_chip, 5); /* additionnel wait time for AKM's */
  649. vx2_write_codec_reg(_chip, AKM_CODEC_POWER_CONTROL_CMD); /* DAC power up, ADC power up, Vref power down */
  650. vx2_write_codec_reg(_chip, AKM_CODEC_CLOCK_FORMAT_CMD); /* default */
  651. vx2_write_codec_reg(_chip, AKM_CODEC_MUTE_CMD); /* Mute = ON ,Deemphasis = OFF */
  652. vx2_write_codec_reg(_chip, AKM_CODEC_RESET_OFF_CMD); /* DAC and ADC normal operation */
  653. if (_chip->type == VX_TYPE_MIC) {
  654. /* set up the micro input selector */
  655. chip->regSELMIC = MICRO_SELECT_INPUT_NORM |
  656. MICRO_SELECT_PREAMPLI_G_0 |
  657. MICRO_SELECT_NOISE_T_52DB;
  658. /* reset phantom power supply */
  659. chip->regSELMIC &= ~MICRO_SELECT_PHANTOM_ALIM;
  660. vx_outl(_chip, SELMIC, chip->regSELMIC);
  661. }
  662. }
  663. /*
  664. * change the audio source
  665. */
  666. static void vx2_change_audio_source(vx_core_t *_chip, int src)
  667. {
  668. struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
  669. switch (src) {
  670. case VX_AUDIO_SRC_DIGITAL:
  671. chip->regCFG |= VX_CFG_DATAIN_SEL_MASK;
  672. break;
  673. default:
  674. chip->regCFG &= ~VX_CFG_DATAIN_SEL_MASK;
  675. break;
  676. }
  677. vx_outl(chip, CFG, chip->regCFG);
  678. }
  679. /*
  680. * set the clock source
  681. */
  682. static void vx2_set_clock_source(vx_core_t *_chip, int source)
  683. {
  684. struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
  685. if (source == INTERNAL_QUARTZ)
  686. chip->regCFG &= ~VX_CFG_CLOCKIN_SEL_MASK;
  687. else
  688. chip->regCFG |= VX_CFG_CLOCKIN_SEL_MASK;
  689. vx_outl(chip, CFG, chip->regCFG);
  690. }
  691. /*
  692. * reset the board
  693. */
  694. static void vx2_reset_board(vx_core_t *_chip, int cold_reset)
  695. {
  696. struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
  697. /* initialize the register values */
  698. chip->regCDSP = VX_CDSP_CODEC_RESET_MASK | VX_CDSP_DSP_RESET_MASK ;
  699. chip->regCFG = 0;
  700. }
  701. /*
  702. * input level controls for VX222 Mic
  703. */
  704. /* Micro level is specified to be adjustable from -96dB to 63 dB (board coded 0x00 ... 318),
  705. * 318 = 210 + 36 + 36 + 36 (210 = +9dB variable) (3 * 36 = 3 steps of 18dB pre ampli)
  706. * as we will mute if less than -110dB, so let's simply use line input coded levels and add constant offset !
  707. */
  708. #define V2_MICRO_LEVEL_RANGE (318 - 255)
  709. static void vx2_set_input_level(struct snd_vx222 *chip)
  710. {
  711. int i, miclevel, preamp;
  712. unsigned int data;
  713. miclevel = chip->mic_level;
  714. miclevel += V2_MICRO_LEVEL_RANGE; /* add 318 - 0xff */
  715. preamp = 0;
  716. while (miclevel > 210) { /* limitation to +9dB of 3310 real gain */
  717. preamp++; /* raise pre ampli + 18dB */
  718. miclevel -= (18 * 2); /* lower level 18 dB (*2 because of 0.5 dB steps !) */
  719. }
  720. snd_assert(preamp < 4, return);
  721. /* set pre-amp level */
  722. chip->regSELMIC &= ~MICRO_SELECT_PREAMPLI_MASK;
  723. chip->regSELMIC |= (preamp << MICRO_SELECT_PREAMPLI_OFFSET) & MICRO_SELECT_PREAMPLI_MASK;
  724. vx_outl(chip, SELMIC, chip->regSELMIC);
  725. data = (unsigned int)miclevel << 16 |
  726. (unsigned int)chip->input_level[1] << 8 |
  727. (unsigned int)chip->input_level[0];
  728. vx_inl(chip, DATA); /* Activate input level programming */
  729. /* We have to send 32 bits (4 x 8 bits) */
  730. for (i = 0; i < 32; i++, data <<= 1)
  731. vx_outl(chip, DATA, ((data & 0x80000000) ? VX_DATA_CODEC_MASK : 0));
  732. vx_inl(chip, RUER); /* Terminate input level programming */
  733. }
  734. #define MIC_LEVEL_MAX 0xff
  735. /*
  736. * controls API for input levels
  737. */
  738. /* input levels */
  739. static int vx_input_level_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
  740. {
  741. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  742. uinfo->count = 2;
  743. uinfo->value.integer.min = 0;
  744. uinfo->value.integer.max = MIC_LEVEL_MAX;
  745. return 0;
  746. }
  747. static int vx_input_level_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
  748. {
  749. vx_core_t *_chip = snd_kcontrol_chip(kcontrol);
  750. struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
  751. down(&_chip->mixer_mutex);
  752. ucontrol->value.integer.value[0] = chip->input_level[0];
  753. ucontrol->value.integer.value[1] = chip->input_level[1];
  754. up(&_chip->mixer_mutex);
  755. return 0;
  756. }
  757. static int vx_input_level_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
  758. {
  759. vx_core_t *_chip = snd_kcontrol_chip(kcontrol);
  760. struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
  761. down(&_chip->mixer_mutex);
  762. if (chip->input_level[0] != ucontrol->value.integer.value[0] ||
  763. chip->input_level[1] != ucontrol->value.integer.value[1]) {
  764. chip->input_level[0] = ucontrol->value.integer.value[0];
  765. chip->input_level[1] = ucontrol->value.integer.value[1];
  766. vx2_set_input_level(chip);
  767. up(&_chip->mixer_mutex);
  768. return 1;
  769. }
  770. up(&_chip->mixer_mutex);
  771. return 0;
  772. }
  773. /* mic level */
  774. static int vx_mic_level_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
  775. {
  776. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  777. uinfo->count = 1;
  778. uinfo->value.integer.min = 0;
  779. uinfo->value.integer.max = MIC_LEVEL_MAX;
  780. return 0;
  781. }
  782. static int vx_mic_level_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
  783. {
  784. vx_core_t *_chip = snd_kcontrol_chip(kcontrol);
  785. struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
  786. ucontrol->value.integer.value[0] = chip->mic_level;
  787. return 0;
  788. }
  789. static int vx_mic_level_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
  790. {
  791. vx_core_t *_chip = snd_kcontrol_chip(kcontrol);
  792. struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
  793. down(&_chip->mixer_mutex);
  794. if (chip->mic_level != ucontrol->value.integer.value[0]) {
  795. chip->mic_level = ucontrol->value.integer.value[0];
  796. vx2_set_input_level(chip);
  797. up(&_chip->mixer_mutex);
  798. return 1;
  799. }
  800. up(&_chip->mixer_mutex);
  801. return 0;
  802. }
  803. static snd_kcontrol_new_t vx_control_input_level = {
  804. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  805. .name = "Capture Volume",
  806. .info = vx_input_level_info,
  807. .get = vx_input_level_get,
  808. .put = vx_input_level_put,
  809. };
  810. static snd_kcontrol_new_t vx_control_mic_level = {
  811. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  812. .name = "Mic Capture Volume",
  813. .info = vx_mic_level_info,
  814. .get = vx_mic_level_get,
  815. .put = vx_mic_level_put,
  816. };
  817. /*
  818. * FIXME: compressor/limiter implementation is missing yet...
  819. */
  820. static int vx2_add_mic_controls(vx_core_t *_chip)
  821. {
  822. struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
  823. int err;
  824. if (_chip->type != VX_TYPE_MIC)
  825. return 0;
  826. /* mute input levels */
  827. chip->input_level[0] = chip->input_level[1] = 0;
  828. chip->mic_level = 0;
  829. vx2_set_input_level(chip);
  830. /* controls */
  831. if ((err = snd_ctl_add(_chip->card, snd_ctl_new1(&vx_control_input_level, chip))) < 0)
  832. return err;
  833. if ((err = snd_ctl_add(_chip->card, snd_ctl_new1(&vx_control_mic_level, chip))) < 0)
  834. return err;
  835. return 0;
  836. }
  837. /*
  838. * callbacks
  839. */
  840. struct snd_vx_ops vx222_ops = {
  841. .in8 = vx2_inb,
  842. .in32 = vx2_inl,
  843. .out8 = vx2_outb,
  844. .out32 = vx2_outl,
  845. .test_and_ack = vx2_test_and_ack,
  846. .validate_irq = vx2_validate_irq,
  847. .akm_write = vx2_write_akm,
  848. .reset_codec = vx2_reset_codec,
  849. .change_audio_source = vx2_change_audio_source,
  850. .set_clock_source = vx2_set_clock_source,
  851. .load_dsp = vx2_load_dsp,
  852. .reset_dsp = vx2_reset_dsp,
  853. .reset_board = vx2_reset_board,
  854. .dma_write = vx2_dma_write,
  855. .dma_read = vx2_dma_read,
  856. .add_controls = vx2_add_mic_controls,
  857. };
  858. /* for old VX222 board */
  859. struct snd_vx_ops vx222_old_ops = {
  860. .in8 = vx2_inb,
  861. .in32 = vx2_inl,
  862. .out8 = vx2_outb,
  863. .out32 = vx2_outl,
  864. .test_and_ack = vx2_test_and_ack,
  865. .validate_irq = vx2_validate_irq,
  866. .write_codec = vx2_old_write_codec_bit,
  867. .reset_codec = vx2_reset_codec,
  868. .change_audio_source = vx2_change_audio_source,
  869. .set_clock_source = vx2_set_clock_source,
  870. .load_dsp = vx2_load_dsp,
  871. .reset_dsp = vx2_reset_dsp,
  872. .reset_board = vx2_reset_board,
  873. .dma_write = vx2_dma_write,
  874. .dma_read = vx2_dma_read,
  875. };