/drivers/ide/pci/piix.c

https://bitbucket.org/evzijst/gittest · C · 670 lines · 412 code · 59 blank · 199 comment · 54 complexity · 9e0ec2233526c3d12324abcb01068c28 MD5 · raw file

  1. /*
  2. * linux/drivers/ide/pci/piix.c Version 0.44 March 20, 2003
  3. *
  4. * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
  5. * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
  6. * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
  7. *
  8. * May be copied or modified under the terms of the GNU General Public License
  9. *
  10. * PIO mode setting function for Intel chipsets.
  11. * For use instead of BIOS settings.
  12. *
  13. * 40-41
  14. * 42-43
  15. *
  16. * 41
  17. * 43
  18. *
  19. * | PIO 0 | c0 | 80 | 0 | piix_tune_drive(drive, 0);
  20. * | PIO 2 | SW2 | d0 | 90 | 4 | piix_tune_drive(drive, 2);
  21. * | PIO 3 | MW1 | e1 | a1 | 9 | piix_tune_drive(drive, 3);
  22. * | PIO 4 | MW2 | e3 | a3 | b | piix_tune_drive(drive, 4);
  23. *
  24. * sitre = word40 & 0x4000; primary
  25. * sitre = word42 & 0x4000; secondary
  26. *
  27. * 44 8421|8421 hdd|hdb
  28. *
  29. * 48 8421 hdd|hdc|hdb|hda udma enabled
  30. *
  31. * 0001 hda
  32. * 0010 hdb
  33. * 0100 hdc
  34. * 1000 hdd
  35. *
  36. * 4a 84|21 hdb|hda
  37. * 4b 84|21 hdd|hdc
  38. *
  39. * ata-33/82371AB
  40. * ata-33/82371EB
  41. * ata-33/82801AB ata-66/82801AA
  42. * 00|00 udma 0 00|00 reserved
  43. * 01|01 udma 1 01|01 udma 3
  44. * 10|10 udma 2 10|10 udma 4
  45. * 11|11 reserved 11|11 reserved
  46. *
  47. * 54 8421|8421 ata66 drive|ata66 enable
  48. *
  49. * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, &reg40);
  50. * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, &reg42);
  51. * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, &reg44);
  52. * pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, &reg48);
  53. * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, &reg4a);
  54. * pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, &reg54);
  55. *
  56. * Documentation
  57. * Publically available from Intel web site. Errata documentation
  58. * is also publically available. As an aide to anyone hacking on this
  59. * driver the list of errata that are relevant is below.going back to
  60. * PIIX4. Older device documentation is now a bit tricky to find.
  61. *
  62. * Errata of note:
  63. *
  64. * Unfixable
  65. * PIIX4 errata #9 - Only on ultra obscure hw
  66. * ICH3 errata #13 - Not observed to affect real hw
  67. * by Intel
  68. *
  69. * Things we must deal with
  70. * PIIX4 errata #10 - BM IDE hang with non UDMA
  71. * (must stop/start dma to recover)
  72. * 440MX errata #15 - As PIIX4 errata #10
  73. * PIIX4 errata #15 - Must not read control registers
  74. * during a PIO transfer
  75. * 440MX errata #13 - As PIIX4 errata #15
  76. * ICH2 errata #21 - DMA mode 0 doesn't work right
  77. * ICH0/1 errata #55 - As ICH2 errata #21
  78. * ICH2 spec c #9 - Extra operations needed to handle
  79. * drive hotswap [NOT YET SUPPORTED]
  80. * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
  81. * and must be dword aligned
  82. * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
  83. *
  84. * Should have been BIOS fixed:
  85. * 450NX: errata #19 - DMA hangs on old 450NX
  86. * 450NX: errata #20 - DMA hangs on old 450NX
  87. * 450NX: errata #25 - Corruption with DMA on old 450NX
  88. * ICH3 errata #15 - IDE deadlock under high load
  89. * (BIOS must set dev 31 fn 0 bit 23)
  90. * ICH3 errata #18 - Don't use native mode
  91. */
  92. #include <linux/config.h>
  93. #include <linux/types.h>
  94. #include <linux/module.h>
  95. #include <linux/kernel.h>
  96. #include <linux/ioport.h>
  97. #include <linux/pci.h>
  98. #include <linux/hdreg.h>
  99. #include <linux/ide.h>
  100. #include <linux/delay.h>
  101. #include <linux/init.h>
  102. #include <asm/io.h>
  103. static int no_piix_dma;
  104. /**
  105. * piix_ratemask - compute rate mask for PIIX IDE
  106. * @drive: IDE drive to compute for
  107. *
  108. * Returns the available modes for the PIIX IDE controller.
  109. */
  110. static u8 piix_ratemask (ide_drive_t *drive)
  111. {
  112. struct pci_dev *dev = HWIF(drive)->pci_dev;
  113. u8 mode;
  114. switch(dev->device) {
  115. case PCI_DEVICE_ID_INTEL_82801EB_1:
  116. mode = 3;
  117. break;
  118. /* UDMA 100 capable */
  119. case PCI_DEVICE_ID_INTEL_82801BA_8:
  120. case PCI_DEVICE_ID_INTEL_82801BA_9:
  121. case PCI_DEVICE_ID_INTEL_82801CA_10:
  122. case PCI_DEVICE_ID_INTEL_82801CA_11:
  123. case PCI_DEVICE_ID_INTEL_82801E_11:
  124. case PCI_DEVICE_ID_INTEL_82801DB_1:
  125. case PCI_DEVICE_ID_INTEL_82801DB_10:
  126. case PCI_DEVICE_ID_INTEL_82801DB_11:
  127. case PCI_DEVICE_ID_INTEL_82801EB_11:
  128. case PCI_DEVICE_ID_INTEL_ESB_2:
  129. case PCI_DEVICE_ID_INTEL_ICH6_19:
  130. case PCI_DEVICE_ID_INTEL_ICH7_21:
  131. mode = 3;
  132. break;
  133. /* UDMA 66 capable */
  134. case PCI_DEVICE_ID_INTEL_82801AA_1:
  135. case PCI_DEVICE_ID_INTEL_82372FB_1:
  136. mode = 2;
  137. break;
  138. /* UDMA 33 capable */
  139. case PCI_DEVICE_ID_INTEL_82371AB:
  140. case PCI_DEVICE_ID_INTEL_82443MX_1:
  141. case PCI_DEVICE_ID_INTEL_82451NX:
  142. case PCI_DEVICE_ID_INTEL_82801AB_1:
  143. return 1;
  144. /* Non UDMA capable (MWDMA2) */
  145. case PCI_DEVICE_ID_INTEL_82371SB_1:
  146. case PCI_DEVICE_ID_INTEL_82371FB_1:
  147. case PCI_DEVICE_ID_INTEL_82371FB_0:
  148. case PCI_DEVICE_ID_INTEL_82371MX:
  149. default:
  150. return 0;
  151. }
  152. /*
  153. * If we are UDMA66 capable fall back to UDMA33
  154. * if the drive cannot see an 80pin cable.
  155. */
  156. if (!eighty_ninty_three(drive))
  157. mode = min(mode, (u8)1);
  158. return mode;
  159. }
  160. /**
  161. * piix_dma_2_pio - return the PIO mode matching DMA
  162. * @xfer_rate: transfer speed
  163. *
  164. * Returns the nearest equivalent PIO timing for the PIO or DMA
  165. * mode requested by the controller.
  166. */
  167. static u8 piix_dma_2_pio (u8 xfer_rate) {
  168. switch(xfer_rate) {
  169. case XFER_UDMA_6:
  170. case XFER_UDMA_5:
  171. case XFER_UDMA_4:
  172. case XFER_UDMA_3:
  173. case XFER_UDMA_2:
  174. case XFER_UDMA_1:
  175. case XFER_UDMA_0:
  176. case XFER_MW_DMA_2:
  177. case XFER_PIO_4:
  178. return 4;
  179. case XFER_MW_DMA_1:
  180. case XFER_PIO_3:
  181. return 3;
  182. case XFER_SW_DMA_2:
  183. case XFER_PIO_2:
  184. return 2;
  185. case XFER_MW_DMA_0:
  186. case XFER_SW_DMA_1:
  187. case XFER_SW_DMA_0:
  188. case XFER_PIO_1:
  189. case XFER_PIO_0:
  190. case XFER_PIO_SLOW:
  191. default:
  192. return 0;
  193. }
  194. }
  195. /**
  196. * piix_tune_drive - tune a drive attached to a PIIX
  197. * @drive: drive to tune
  198. * @pio: desired PIO mode
  199. *
  200. * Set the interface PIO mode based upon the settings done by AMI BIOS
  201. * (might be useful if drive is not registered in CMOS for any reason).
  202. */
  203. static void piix_tune_drive (ide_drive_t *drive, u8 pio)
  204. {
  205. ide_hwif_t *hwif = HWIF(drive);
  206. struct pci_dev *dev = hwif->pci_dev;
  207. int is_slave = (&hwif->drives[1] == drive);
  208. int master_port = hwif->channel ? 0x42 : 0x40;
  209. int slave_port = 0x44;
  210. unsigned long flags;
  211. u16 master_data;
  212. u8 slave_data;
  213. /* ISP RTC */
  214. u8 timings[][2] = { { 0, 0 },
  215. { 0, 0 },
  216. { 1, 0 },
  217. { 2, 1 },
  218. { 2, 3 }, };
  219. pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
  220. spin_lock_irqsave(&ide_lock, flags);
  221. pci_read_config_word(dev, master_port, &master_data);
  222. if (is_slave) {
  223. master_data = master_data | 0x4000;
  224. if (pio > 1)
  225. /* enable PPE, IE and TIME */
  226. master_data = master_data | 0x0070;
  227. pci_read_config_byte(dev, slave_port, &slave_data);
  228. slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0);
  229. slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0));
  230. } else {
  231. master_data = master_data & 0xccf8;
  232. if (pio > 1)
  233. /* enable PPE, IE and TIME */
  234. master_data = master_data | 0x0007;
  235. master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
  236. }
  237. pci_write_config_word(dev, master_port, master_data);
  238. if (is_slave)
  239. pci_write_config_byte(dev, slave_port, slave_data);
  240. spin_unlock_irqrestore(&ide_lock, flags);
  241. }
  242. /**
  243. * piix_tune_chipset - tune a PIIX interface
  244. * @drive: IDE drive to tune
  245. * @xferspeed: speed to configure
  246. *
  247. * Set a PIIX interface channel to the desired speeds. This involves
  248. * requires the right timing data into the PIIX configuration space
  249. * then setting the drive parameters appropriately
  250. */
  251. static int piix_tune_chipset (ide_drive_t *drive, u8 xferspeed)
  252. {
  253. ide_hwif_t *hwif = HWIF(drive);
  254. struct pci_dev *dev = hwif->pci_dev;
  255. u8 maslave = hwif->channel ? 0x42 : 0x40;
  256. u8 speed = ide_rate_filter(piix_ratemask(drive), xferspeed);
  257. int a_speed = 3 << (drive->dn * 4);
  258. int u_flag = 1 << drive->dn;
  259. int v_flag = 0x01 << drive->dn;
  260. int w_flag = 0x10 << drive->dn;
  261. int u_speed = 0;
  262. int sitre;
  263. u16 reg4042, reg4a;
  264. u8 reg48, reg54, reg55;
  265. pci_read_config_word(dev, maslave, &reg4042);
  266. sitre = (reg4042 & 0x4000) ? 1 : 0;
  267. pci_read_config_byte(dev, 0x48, &reg48);
  268. pci_read_config_word(dev, 0x4a, &reg4a);
  269. pci_read_config_byte(dev, 0x54, &reg54);
  270. pci_read_config_byte(dev, 0x55, &reg55);
  271. switch(speed) {
  272. case XFER_UDMA_4:
  273. case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break;
  274. case XFER_UDMA_5:
  275. case XFER_UDMA_3:
  276. case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break;
  277. case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
  278. case XFER_MW_DMA_2:
  279. case XFER_MW_DMA_1:
  280. case XFER_SW_DMA_2: break;
  281. case XFER_PIO_4:
  282. case XFER_PIO_3:
  283. case XFER_PIO_2:
  284. case XFER_PIO_0: break;
  285. default: return -1;
  286. }
  287. if (speed >= XFER_UDMA_0) {
  288. if (!(reg48 & u_flag))
  289. pci_write_config_byte(dev, 0x48, reg48 | u_flag);
  290. if (speed == XFER_UDMA_5) {
  291. pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
  292. } else {
  293. pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
  294. }
  295. if ((reg4a & a_speed) != u_speed)
  296. pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
  297. if (speed > XFER_UDMA_2) {
  298. if (!(reg54 & v_flag))
  299. pci_write_config_byte(dev, 0x54, reg54 | v_flag);
  300. } else
  301. pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
  302. } else {
  303. if (reg48 & u_flag)
  304. pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
  305. if (reg4a & a_speed)
  306. pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
  307. if (reg54 & v_flag)
  308. pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
  309. if (reg55 & w_flag)
  310. pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
  311. }
  312. piix_tune_drive(drive, piix_dma_2_pio(speed));
  313. return (ide_config_drive_speed(drive, speed));
  314. }
  315. /**
  316. * piix_faulty_dma0 - check for DMA0 errata
  317. * @hwif: IDE interface to check
  318. *
  319. * If an ICH/ICH0/ICH2 interface is is operating in multi-word
  320. * DMA mode with 600nS cycle time the IDE PIO prefetch buffer will
  321. * inadvertently provide an extra piece of secondary data to the primary
  322. * device resulting in data corruption.
  323. *
  324. * With such a device this test function returns true. This allows
  325. * our tuning code to follow Intel recommendations and use PIO on
  326. * such devices.
  327. */
  328. static int piix_faulty_dma0(ide_hwif_t *hwif)
  329. {
  330. switch(hwif->pci_dev->device)
  331. {
  332. case PCI_DEVICE_ID_INTEL_82801AA_1: /* ICH */
  333. case PCI_DEVICE_ID_INTEL_82801AB_1: /* ICH0 */
  334. case PCI_DEVICE_ID_INTEL_82801BA_8: /* ICH2 */
  335. case PCI_DEVICE_ID_INTEL_82801BA_9: /* ICH2 */
  336. return 1;
  337. }
  338. return 0;
  339. }
  340. /**
  341. * piix_config_drive_for_dma - configure drive for DMA
  342. * @drive: IDE drive to configure
  343. *
  344. * Set up a PIIX interface channel for the best available speed.
  345. * We prefer UDMA if it is available and then MWDMA. If DMA is
  346. * not available we switch to PIO and return 0.
  347. */
  348. static int piix_config_drive_for_dma (ide_drive_t *drive)
  349. {
  350. u8 speed = ide_dma_speed(drive, piix_ratemask(drive));
  351. /* Some ICH devices cannot support DMA mode 0 */
  352. if(speed == XFER_MW_DMA_0 && piix_faulty_dma0(HWIF(drive)))
  353. speed = 0;
  354. /* If no DMA speed was available or the chipset has DMA bugs
  355. then disable DMA and use PIO */
  356. if (!speed || no_piix_dma) {
  357. u8 tspeed = ide_get_best_pio_mode(drive, 255, 5, NULL);
  358. speed = piix_dma_2_pio(XFER_PIO_0 + tspeed);
  359. }
  360. (void) piix_tune_chipset(drive, speed);
  361. return ide_dma_enable(drive);
  362. }
  363. /**
  364. * piix_config_drive_xfer_rate - set up an IDE device
  365. * @drive: IDE drive to configure
  366. *
  367. * Set up the PIIX interface for the best available speed on this
  368. * interface, preferring DMA to PIO.
  369. */
  370. static int piix_config_drive_xfer_rate (ide_drive_t *drive)
  371. {
  372. ide_hwif_t *hwif = HWIF(drive);
  373. struct hd_driveid *id = drive->id;
  374. drive->init_speed = 0;
  375. if ((id->capability & 1) && drive->autodma) {
  376. if (ide_use_dma(drive)) {
  377. if (piix_config_drive_for_dma(drive))
  378. return hwif->ide_dma_on(drive);
  379. }
  380. goto fast_ata_pio;
  381. } else if ((id->capability & 8) || (id->field_valid & 2)) {
  382. fast_ata_pio:
  383. /* Find best PIO mode. */
  384. hwif->tuneproc(drive, 255);
  385. return hwif->ide_dma_off_quietly(drive);
  386. }
  387. /* IORDY not supported */
  388. return 0;
  389. }
  390. /**
  391. * init_chipset_piix - set up the PIIX chipset
  392. * @dev: PCI device to set up
  393. * @name: Name of the device
  394. *
  395. * Initialize the PCI device as required. For the PIIX this turns
  396. * out to be nice and simple
  397. */
  398. static unsigned int __devinit init_chipset_piix (struct pci_dev *dev, const char *name)
  399. {
  400. switch(dev->device) {
  401. case PCI_DEVICE_ID_INTEL_82801EB_1:
  402. case PCI_DEVICE_ID_INTEL_82801AA_1:
  403. case PCI_DEVICE_ID_INTEL_82801AB_1:
  404. case PCI_DEVICE_ID_INTEL_82801BA_8:
  405. case PCI_DEVICE_ID_INTEL_82801BA_9:
  406. case PCI_DEVICE_ID_INTEL_82801CA_10:
  407. case PCI_DEVICE_ID_INTEL_82801CA_11:
  408. case PCI_DEVICE_ID_INTEL_82801DB_1:
  409. case PCI_DEVICE_ID_INTEL_82801DB_10:
  410. case PCI_DEVICE_ID_INTEL_82801DB_11:
  411. case PCI_DEVICE_ID_INTEL_82801EB_11:
  412. case PCI_DEVICE_ID_INTEL_82801E_11:
  413. case PCI_DEVICE_ID_INTEL_ESB_2:
  414. case PCI_DEVICE_ID_INTEL_ICH6_19:
  415. case PCI_DEVICE_ID_INTEL_ICH7_21:
  416. {
  417. unsigned int extra = 0;
  418. pci_read_config_dword(dev, 0x54, &extra);
  419. pci_write_config_dword(dev, 0x54, extra|0x400);
  420. }
  421. default:
  422. break;
  423. }
  424. return 0;
  425. }
  426. /**
  427. * init_hwif_piix - fill in the hwif for the PIIX
  428. * @hwif: IDE interface
  429. *
  430. * Set up the ide_hwif_t for the PIIX interface according to the
  431. * capabilities of the hardware.
  432. */
  433. static void __devinit init_hwif_piix(ide_hwif_t *hwif)
  434. {
  435. u8 reg54h = 0, reg55h = 0, ata66 = 0;
  436. u8 mask = hwif->channel ? 0xc0 : 0x30;
  437. #ifndef CONFIG_IA64
  438. if (!hwif->irq)
  439. hwif->irq = hwif->channel ? 15 : 14;
  440. #endif /* CONFIG_IA64 */
  441. if (hwif->pci_dev->device == PCI_DEVICE_ID_INTEL_82371MX) {
  442. /* This is a painful system best to let it self tune for now */
  443. return;
  444. }
  445. hwif->autodma = 0;
  446. hwif->tuneproc = &piix_tune_drive;
  447. hwif->speedproc = &piix_tune_chipset;
  448. hwif->drives[0].autotune = 1;
  449. hwif->drives[1].autotune = 1;
  450. if (!hwif->dma_base)
  451. return;
  452. hwif->atapi_dma = 1;
  453. hwif->ultra_mask = 0x3f;
  454. hwif->mwdma_mask = 0x06;
  455. hwif->swdma_mask = 0x04;
  456. switch(hwif->pci_dev->device) {
  457. case PCI_DEVICE_ID_INTEL_82371MX:
  458. hwif->mwdma_mask = 0x80;
  459. hwif->swdma_mask = 0x80;
  460. case PCI_DEVICE_ID_INTEL_82371FB_0:
  461. case PCI_DEVICE_ID_INTEL_82371FB_1:
  462. case PCI_DEVICE_ID_INTEL_82371SB_1:
  463. hwif->ultra_mask = 0x80;
  464. break;
  465. case PCI_DEVICE_ID_INTEL_82371AB:
  466. case PCI_DEVICE_ID_INTEL_82443MX_1:
  467. case PCI_DEVICE_ID_INTEL_82451NX:
  468. case PCI_DEVICE_ID_INTEL_82801AB_1:
  469. hwif->ultra_mask = 0x07;
  470. break;
  471. default:
  472. pci_read_config_byte(hwif->pci_dev, 0x54, &reg54h);
  473. pci_read_config_byte(hwif->pci_dev, 0x55, &reg55h);
  474. ata66 = (reg54h & mask) ? 1 : 0;
  475. break;
  476. }
  477. if (!(hwif->udma_four))
  478. hwif->udma_four = ata66;
  479. hwif->ide_dma_check = &piix_config_drive_xfer_rate;
  480. if (!noautodma)
  481. hwif->autodma = 1;
  482. hwif->drives[1].autodma = hwif->autodma;
  483. hwif->drives[0].autodma = hwif->autodma;
  484. }
  485. #define DECLARE_PIIX_DEV(name_str) \
  486. { \
  487. .name = name_str, \
  488. .init_chipset = init_chipset_piix, \
  489. .init_hwif = init_hwif_piix, \
  490. .channels = 2, \
  491. .autodma = AUTODMA, \
  492. .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
  493. .bootable = ON_BOARD, \
  494. }
  495. static ide_pci_device_t piix_pci_info[] __devinitdata = {
  496. /* 0 */ DECLARE_PIIX_DEV("PIIXa"),
  497. /* 1 */ DECLARE_PIIX_DEV("PIIXb"),
  498. { /* 2 */
  499. .name = "MPIIX",
  500. .init_hwif = init_hwif_piix,
  501. .channels = 2,
  502. .autodma = NODMA,
  503. .enablebits = {{0x6D,0x80,0x80}, {0x6F,0x80,0x80}},
  504. .bootable = ON_BOARD,
  505. },
  506. /* 3 */ DECLARE_PIIX_DEV("PIIX3"),
  507. /* 4 */ DECLARE_PIIX_DEV("PIIX4"),
  508. /* 5 */ DECLARE_PIIX_DEV("ICH0"),
  509. /* 6 */ DECLARE_PIIX_DEV("PIIX4"),
  510. /* 7 */ DECLARE_PIIX_DEV("ICH"),
  511. /* 8 */ DECLARE_PIIX_DEV("PIIX4"),
  512. /* 9 */ DECLARE_PIIX_DEV("PIIX4"),
  513. /* 10 */ DECLARE_PIIX_DEV("ICH2"),
  514. /* 11 */ DECLARE_PIIX_DEV("ICH2M"),
  515. /* 12 */ DECLARE_PIIX_DEV("ICH3M"),
  516. /* 13 */ DECLARE_PIIX_DEV("ICH3"),
  517. /* 14 */ DECLARE_PIIX_DEV("ICH4"),
  518. /* 15 */ DECLARE_PIIX_DEV("ICH5"),
  519. /* 16 */ DECLARE_PIIX_DEV("C-ICH"),
  520. /* 17 */ DECLARE_PIIX_DEV("ICH4"),
  521. /* 18 */ DECLARE_PIIX_DEV("ICH5-SATA"),
  522. /* 19 */ DECLARE_PIIX_DEV("ICH5"),
  523. /* 20 */ DECLARE_PIIX_DEV("ICH6"),
  524. /* 21 */ DECLARE_PIIX_DEV("ICH7"),
  525. /* 22 */ DECLARE_PIIX_DEV("ICH4"),
  526. };
  527. /**
  528. * piix_init_one - called when a PIIX is found
  529. * @dev: the piix device
  530. * @id: the matching pci id
  531. *
  532. * Called when the PCI registration layer (or the IDE initialization)
  533. * finds a device matching our IDE device tables.
  534. */
  535. static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  536. {
  537. ide_pci_device_t *d = &piix_pci_info[id->driver_data];
  538. return ide_setup_pci_device(dev, d);
  539. }
  540. /**
  541. * piix_check_450nx - Check for problem 450NX setup
  542. *
  543. * Check for the present of 450NX errata #19 and errata #25. If
  544. * they are found, disable use of DMA IDE
  545. */
  546. static void __devinit piix_check_450nx(void)
  547. {
  548. struct pci_dev *pdev = NULL;
  549. u16 cfg;
  550. u8 rev;
  551. while((pdev=pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
  552. {
  553. /* Look for 450NX PXB. Check for problem configurations
  554. A PCI quirk checks bit 6 already */
  555. pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
  556. pci_read_config_word(pdev, 0x41, &cfg);
  557. /* Only on the original revision: IDE DMA can hang */
  558. if(rev == 0x00)
  559. no_piix_dma = 1;
  560. /* On all revisions below 5 PXB bus lock must be disabled for IDE */
  561. else if(cfg & (1<<14) && rev < 5)
  562. no_piix_dma = 2;
  563. }
  564. if(no_piix_dma)
  565. printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n");
  566. if(no_piix_dma == 2)
  567. printk(KERN_WARNING "piix: A BIOS update may resolve this.\n");
  568. }
  569. static struct pci_device_id piix_pci_tbl[] = {
  570. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  571. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
  572. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
  573. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
  574. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
  575. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
  576. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
  577. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7},
  578. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82372FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8},
  579. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9},
  580. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10},
  581. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11},
  582. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12},
  583. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13},
  584. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14},
  585. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 15},
  586. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_11, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 16},
  587. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 17},
  588. #ifdef CONFIG_BLK_DEV_IDE_SATA
  589. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 18},
  590. #endif
  591. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 19},
  592. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_19, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 20},
  593. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 21},
  594. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 22},
  595. { 0, },
  596. };
  597. MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
  598. static struct pci_driver driver = {
  599. .name = "PIIX_IDE",
  600. .id_table = piix_pci_tbl,
  601. .probe = piix_init_one,
  602. };
  603. static int __init piix_ide_init(void)
  604. {
  605. piix_check_450nx();
  606. return ide_pci_register_driver(&driver);
  607. }
  608. module_init(piix_ide_init);
  609. MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
  610. MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
  611. MODULE_LICENSE("GPL");