/drivers/ide/pci/piix.c
C | 670 lines | 412 code | 59 blank | 199 comment | 47 complexity | 9e0ec2233526c3d12324abcb01068c28 MD5 | raw file
1/* 2 * linux/drivers/ide/pci/piix.c Version 0.44 March 20, 2003 3 * 4 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer 5 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> 6 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> 7 * 8 * May be copied or modified under the terms of the GNU General Public License 9 * 10 * PIO mode setting function for Intel chipsets. 11 * For use instead of BIOS settings. 12 * 13 * 40-41 14 * 42-43 15 * 16 * 41 17 * 43 18 * 19 * | PIO 0 | c0 | 80 | 0 | piix_tune_drive(drive, 0); 20 * | PIO 2 | SW2 | d0 | 90 | 4 | piix_tune_drive(drive, 2); 21 * | PIO 3 | MW1 | e1 | a1 | 9 | piix_tune_drive(drive, 3); 22 * | PIO 4 | MW2 | e3 | a3 | b | piix_tune_drive(drive, 4); 23 * 24 * sitre = word40 & 0x4000; primary 25 * sitre = word42 & 0x4000; secondary 26 * 27 * 44 8421|8421 hdd|hdb 28 * 29 * 48 8421 hdd|hdc|hdb|hda udma enabled 30 * 31 * 0001 hda 32 * 0010 hdb 33 * 0100 hdc 34 * 1000 hdd 35 * 36 * 4a 84|21 hdb|hda 37 * 4b 84|21 hdd|hdc 38 * 39 * ata-33/82371AB 40 * ata-33/82371EB 41 * ata-33/82801AB ata-66/82801AA 42 * 00|00 udma 0 00|00 reserved 43 * 01|01 udma 1 01|01 udma 3 44 * 10|10 udma 2 10|10 udma 4 45 * 11|11 reserved 11|11 reserved 46 * 47 * 54 8421|8421 ata66 drive|ata66 enable 48 * 49 * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, ®40); 50 * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, ®42); 51 * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, ®44); 52 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, ®48); 53 * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, ®4a); 54 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, ®54); 55 * 56 * Documentation 57 * Publically available from Intel web site. Errata documentation 58 * is also publically available. As an aide to anyone hacking on this 59 * driver the list of errata that are relevant is below.going back to 60 * PIIX4. Older device documentation is now a bit tricky to find. 61 * 62 * Errata of note: 63 * 64 * Unfixable 65 * PIIX4 errata #9 - Only on ultra obscure hw 66 * ICH3 errata #13 - Not observed to affect real hw 67 * by Intel 68 * 69 * Things we must deal with 70 * PIIX4 errata #10 - BM IDE hang with non UDMA 71 * (must stop/start dma to recover) 72 * 440MX errata #15 - As PIIX4 errata #10 73 * PIIX4 errata #15 - Must not read control registers 74 * during a PIO transfer 75 * 440MX errata #13 - As PIIX4 errata #15 76 * ICH2 errata #21 - DMA mode 0 doesn't work right 77 * ICH0/1 errata #55 - As ICH2 errata #21 78 * ICH2 spec c #9 - Extra operations needed to handle 79 * drive hotswap [NOT YET SUPPORTED] 80 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary 81 * and must be dword aligned 82 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 83 * 84 * Should have been BIOS fixed: 85 * 450NX: errata #19 - DMA hangs on old 450NX 86 * 450NX: errata #20 - DMA hangs on old 450NX 87 * 450NX: errata #25 - Corruption with DMA on old 450NX 88 * ICH3 errata #15 - IDE deadlock under high load 89 * (BIOS must set dev 31 fn 0 bit 23) 90 * ICH3 errata #18 - Don't use native mode 91 */ 92 93#include <linux/config.h> 94#include <linux/types.h> 95#include <linux/module.h> 96#include <linux/kernel.h> 97#include <linux/ioport.h> 98#include <linux/pci.h> 99#include <linux/hdreg.h> 100#include <linux/ide.h> 101#include <linux/delay.h> 102#include <linux/init.h> 103 104#include <asm/io.h> 105 106static int no_piix_dma; 107 108/** 109 * piix_ratemask - compute rate mask for PIIX IDE 110 * @drive: IDE drive to compute for 111 * 112 * Returns the available modes for the PIIX IDE controller. 113 */ 114 115static u8 piix_ratemask (ide_drive_t *drive) 116{ 117 struct pci_dev *dev = HWIF(drive)->pci_dev; 118 u8 mode; 119 120 switch(dev->device) { 121 case PCI_DEVICE_ID_INTEL_82801EB_1: 122 mode = 3; 123 break; 124 /* UDMA 100 capable */ 125 case PCI_DEVICE_ID_INTEL_82801BA_8: 126 case PCI_DEVICE_ID_INTEL_82801BA_9: 127 case PCI_DEVICE_ID_INTEL_82801CA_10: 128 case PCI_DEVICE_ID_INTEL_82801CA_11: 129 case PCI_DEVICE_ID_INTEL_82801E_11: 130 case PCI_DEVICE_ID_INTEL_82801DB_1: 131 case PCI_DEVICE_ID_INTEL_82801DB_10: 132 case PCI_DEVICE_ID_INTEL_82801DB_11: 133 case PCI_DEVICE_ID_INTEL_82801EB_11: 134 case PCI_DEVICE_ID_INTEL_ESB_2: 135 case PCI_DEVICE_ID_INTEL_ICH6_19: 136 case PCI_DEVICE_ID_INTEL_ICH7_21: 137 mode = 3; 138 break; 139 /* UDMA 66 capable */ 140 case PCI_DEVICE_ID_INTEL_82801AA_1: 141 case PCI_DEVICE_ID_INTEL_82372FB_1: 142 mode = 2; 143 break; 144 /* UDMA 33 capable */ 145 case PCI_DEVICE_ID_INTEL_82371AB: 146 case PCI_DEVICE_ID_INTEL_82443MX_1: 147 case PCI_DEVICE_ID_INTEL_82451NX: 148 case PCI_DEVICE_ID_INTEL_82801AB_1: 149 return 1; 150 /* Non UDMA capable (MWDMA2) */ 151 case PCI_DEVICE_ID_INTEL_82371SB_1: 152 case PCI_DEVICE_ID_INTEL_82371FB_1: 153 case PCI_DEVICE_ID_INTEL_82371FB_0: 154 case PCI_DEVICE_ID_INTEL_82371MX: 155 default: 156 return 0; 157 } 158 159 /* 160 * If we are UDMA66 capable fall back to UDMA33 161 * if the drive cannot see an 80pin cable. 162 */ 163 if (!eighty_ninty_three(drive)) 164 mode = min(mode, (u8)1); 165 return mode; 166} 167 168/** 169 * piix_dma_2_pio - return the PIO mode matching DMA 170 * @xfer_rate: transfer speed 171 * 172 * Returns the nearest equivalent PIO timing for the PIO or DMA 173 * mode requested by the controller. 174 */ 175 176static u8 piix_dma_2_pio (u8 xfer_rate) { 177 switch(xfer_rate) { 178 case XFER_UDMA_6: 179 case XFER_UDMA_5: 180 case XFER_UDMA_4: 181 case XFER_UDMA_3: 182 case XFER_UDMA_2: 183 case XFER_UDMA_1: 184 case XFER_UDMA_0: 185 case XFER_MW_DMA_2: 186 case XFER_PIO_4: 187 return 4; 188 case XFER_MW_DMA_1: 189 case XFER_PIO_3: 190 return 3; 191 case XFER_SW_DMA_2: 192 case XFER_PIO_2: 193 return 2; 194 case XFER_MW_DMA_0: 195 case XFER_SW_DMA_1: 196 case XFER_SW_DMA_0: 197 case XFER_PIO_1: 198 case XFER_PIO_0: 199 case XFER_PIO_SLOW: 200 default: 201 return 0; 202 } 203} 204 205/** 206 * piix_tune_drive - tune a drive attached to a PIIX 207 * @drive: drive to tune 208 * @pio: desired PIO mode 209 * 210 * Set the interface PIO mode based upon the settings done by AMI BIOS 211 * (might be useful if drive is not registered in CMOS for any reason). 212 */ 213static void piix_tune_drive (ide_drive_t *drive, u8 pio) 214{ 215 ide_hwif_t *hwif = HWIF(drive); 216 struct pci_dev *dev = hwif->pci_dev; 217 int is_slave = (&hwif->drives[1] == drive); 218 int master_port = hwif->channel ? 0x42 : 0x40; 219 int slave_port = 0x44; 220 unsigned long flags; 221 u16 master_data; 222 u8 slave_data; 223 /* ISP RTC */ 224 u8 timings[][2] = { { 0, 0 }, 225 { 0, 0 }, 226 { 1, 0 }, 227 { 2, 1 }, 228 { 2, 3 }, }; 229 230 pio = ide_get_best_pio_mode(drive, pio, 5, NULL); 231 spin_lock_irqsave(&ide_lock, flags); 232 pci_read_config_word(dev, master_port, &master_data); 233 if (is_slave) { 234 master_data = master_data | 0x4000; 235 if (pio > 1) 236 /* enable PPE, IE and TIME */ 237 master_data = master_data | 0x0070; 238 pci_read_config_byte(dev, slave_port, &slave_data); 239 slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0); 240 slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0)); 241 } else { 242 master_data = master_data & 0xccf8; 243 if (pio > 1) 244 /* enable PPE, IE and TIME */ 245 master_data = master_data | 0x0007; 246 master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8); 247 } 248 pci_write_config_word(dev, master_port, master_data); 249 if (is_slave) 250 pci_write_config_byte(dev, slave_port, slave_data); 251 spin_unlock_irqrestore(&ide_lock, flags); 252} 253 254/** 255 * piix_tune_chipset - tune a PIIX interface 256 * @drive: IDE drive to tune 257 * @xferspeed: speed to configure 258 * 259 * Set a PIIX interface channel to the desired speeds. This involves 260 * requires the right timing data into the PIIX configuration space 261 * then setting the drive parameters appropriately 262 */ 263 264static int piix_tune_chipset (ide_drive_t *drive, u8 xferspeed) 265{ 266 ide_hwif_t *hwif = HWIF(drive); 267 struct pci_dev *dev = hwif->pci_dev; 268 u8 maslave = hwif->channel ? 0x42 : 0x40; 269 u8 speed = ide_rate_filter(piix_ratemask(drive), xferspeed); 270 int a_speed = 3 << (drive->dn * 4); 271 int u_flag = 1 << drive->dn; 272 int v_flag = 0x01 << drive->dn; 273 int w_flag = 0x10 << drive->dn; 274 int u_speed = 0; 275 int sitre; 276 u16 reg4042, reg4a; 277 u8 reg48, reg54, reg55; 278 279 pci_read_config_word(dev, maslave, ®4042); 280 sitre = (reg4042 & 0x4000) ? 1 : 0; 281 pci_read_config_byte(dev, 0x48, ®48); 282 pci_read_config_word(dev, 0x4a, ®4a); 283 pci_read_config_byte(dev, 0x54, ®54); 284 pci_read_config_byte(dev, 0x55, ®55); 285 286 switch(speed) { 287 case XFER_UDMA_4: 288 case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break; 289 case XFER_UDMA_5: 290 case XFER_UDMA_3: 291 case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break; 292 case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break; 293 case XFER_MW_DMA_2: 294 case XFER_MW_DMA_1: 295 case XFER_SW_DMA_2: break; 296 case XFER_PIO_4: 297 case XFER_PIO_3: 298 case XFER_PIO_2: 299 case XFER_PIO_0: break; 300 default: return -1; 301 } 302 303 if (speed >= XFER_UDMA_0) { 304 if (!(reg48 & u_flag)) 305 pci_write_config_byte(dev, 0x48, reg48 | u_flag); 306 if (speed == XFER_UDMA_5) { 307 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag); 308 } else { 309 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); 310 } 311 if ((reg4a & a_speed) != u_speed) 312 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed); 313 if (speed > XFER_UDMA_2) { 314 if (!(reg54 & v_flag)) 315 pci_write_config_byte(dev, 0x54, reg54 | v_flag); 316 } else 317 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); 318 } else { 319 if (reg48 & u_flag) 320 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag); 321 if (reg4a & a_speed) 322 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed); 323 if (reg54 & v_flag) 324 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); 325 if (reg55 & w_flag) 326 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); 327 } 328 329 piix_tune_drive(drive, piix_dma_2_pio(speed)); 330 return (ide_config_drive_speed(drive, speed)); 331} 332 333/** 334 * piix_faulty_dma0 - check for DMA0 errata 335 * @hwif: IDE interface to check 336 * 337 * If an ICH/ICH0/ICH2 interface is is operating in multi-word 338 * DMA mode with 600nS cycle time the IDE PIO prefetch buffer will 339 * inadvertently provide an extra piece of secondary data to the primary 340 * device resulting in data corruption. 341 * 342 * With such a device this test function returns true. This allows 343 * our tuning code to follow Intel recommendations and use PIO on 344 * such devices. 345 */ 346 347static int piix_faulty_dma0(ide_hwif_t *hwif) 348{ 349 switch(hwif->pci_dev->device) 350 { 351 case PCI_DEVICE_ID_INTEL_82801AA_1: /* ICH */ 352 case PCI_DEVICE_ID_INTEL_82801AB_1: /* ICH0 */ 353 case PCI_DEVICE_ID_INTEL_82801BA_8: /* ICH2 */ 354 case PCI_DEVICE_ID_INTEL_82801BA_9: /* ICH2 */ 355 return 1; 356 } 357 return 0; 358} 359 360/** 361 * piix_config_drive_for_dma - configure drive for DMA 362 * @drive: IDE drive to configure 363 * 364 * Set up a PIIX interface channel for the best available speed. 365 * We prefer UDMA if it is available and then MWDMA. If DMA is 366 * not available we switch to PIO and return 0. 367 */ 368 369static int piix_config_drive_for_dma (ide_drive_t *drive) 370{ 371 u8 speed = ide_dma_speed(drive, piix_ratemask(drive)); 372 373 /* Some ICH devices cannot support DMA mode 0 */ 374 if(speed == XFER_MW_DMA_0 && piix_faulty_dma0(HWIF(drive))) 375 speed = 0; 376 377 /* If no DMA speed was available or the chipset has DMA bugs 378 then disable DMA and use PIO */ 379 380 if (!speed || no_piix_dma) { 381 u8 tspeed = ide_get_best_pio_mode(drive, 255, 5, NULL); 382 speed = piix_dma_2_pio(XFER_PIO_0 + tspeed); 383 } 384 385 (void) piix_tune_chipset(drive, speed); 386 return ide_dma_enable(drive); 387} 388 389/** 390 * piix_config_drive_xfer_rate - set up an IDE device 391 * @drive: IDE drive to configure 392 * 393 * Set up the PIIX interface for the best available speed on this 394 * interface, preferring DMA to PIO. 395 */ 396 397static int piix_config_drive_xfer_rate (ide_drive_t *drive) 398{ 399 ide_hwif_t *hwif = HWIF(drive); 400 struct hd_driveid *id = drive->id; 401 402 drive->init_speed = 0; 403 404 if ((id->capability & 1) && drive->autodma) { 405 406 if (ide_use_dma(drive)) { 407 if (piix_config_drive_for_dma(drive)) 408 return hwif->ide_dma_on(drive); 409 } 410 411 goto fast_ata_pio; 412 413 } else if ((id->capability & 8) || (id->field_valid & 2)) { 414fast_ata_pio: 415 /* Find best PIO mode. */ 416 hwif->tuneproc(drive, 255); 417 return hwif->ide_dma_off_quietly(drive); 418 } 419 /* IORDY not supported */ 420 return 0; 421} 422 423/** 424 * init_chipset_piix - set up the PIIX chipset 425 * @dev: PCI device to set up 426 * @name: Name of the device 427 * 428 * Initialize the PCI device as required. For the PIIX this turns 429 * out to be nice and simple 430 */ 431 432static unsigned int __devinit init_chipset_piix (struct pci_dev *dev, const char *name) 433{ 434 switch(dev->device) { 435 case PCI_DEVICE_ID_INTEL_82801EB_1: 436 case PCI_DEVICE_ID_INTEL_82801AA_1: 437 case PCI_DEVICE_ID_INTEL_82801AB_1: 438 case PCI_DEVICE_ID_INTEL_82801BA_8: 439 case PCI_DEVICE_ID_INTEL_82801BA_9: 440 case PCI_DEVICE_ID_INTEL_82801CA_10: 441 case PCI_DEVICE_ID_INTEL_82801CA_11: 442 case PCI_DEVICE_ID_INTEL_82801DB_1: 443 case PCI_DEVICE_ID_INTEL_82801DB_10: 444 case PCI_DEVICE_ID_INTEL_82801DB_11: 445 case PCI_DEVICE_ID_INTEL_82801EB_11: 446 case PCI_DEVICE_ID_INTEL_82801E_11: 447 case PCI_DEVICE_ID_INTEL_ESB_2: 448 case PCI_DEVICE_ID_INTEL_ICH6_19: 449 case PCI_DEVICE_ID_INTEL_ICH7_21: 450 { 451 unsigned int extra = 0; 452 pci_read_config_dword(dev, 0x54, &extra); 453 pci_write_config_dword(dev, 0x54, extra|0x400); 454 } 455 default: 456 break; 457 } 458 459 return 0; 460} 461 462/** 463 * init_hwif_piix - fill in the hwif for the PIIX 464 * @hwif: IDE interface 465 * 466 * Set up the ide_hwif_t for the PIIX interface according to the 467 * capabilities of the hardware. 468 */ 469 470static void __devinit init_hwif_piix(ide_hwif_t *hwif) 471{ 472 u8 reg54h = 0, reg55h = 0, ata66 = 0; 473 u8 mask = hwif->channel ? 0xc0 : 0x30; 474 475#ifndef CONFIG_IA64 476 if (!hwif->irq) 477 hwif->irq = hwif->channel ? 15 : 14; 478#endif /* CONFIG_IA64 */ 479 480 if (hwif->pci_dev->device == PCI_DEVICE_ID_INTEL_82371MX) { 481 /* This is a painful system best to let it self tune for now */ 482 return; 483 } 484 485 hwif->autodma = 0; 486 hwif->tuneproc = &piix_tune_drive; 487 hwif->speedproc = &piix_tune_chipset; 488 hwif->drives[0].autotune = 1; 489 hwif->drives[1].autotune = 1; 490 491 if (!hwif->dma_base) 492 return; 493 494 hwif->atapi_dma = 1; 495 hwif->ultra_mask = 0x3f; 496 hwif->mwdma_mask = 0x06; 497 hwif->swdma_mask = 0x04; 498 499 switch(hwif->pci_dev->device) { 500 case PCI_DEVICE_ID_INTEL_82371MX: 501 hwif->mwdma_mask = 0x80; 502 hwif->swdma_mask = 0x80; 503 case PCI_DEVICE_ID_INTEL_82371FB_0: 504 case PCI_DEVICE_ID_INTEL_82371FB_1: 505 case PCI_DEVICE_ID_INTEL_82371SB_1: 506 hwif->ultra_mask = 0x80; 507 break; 508 case PCI_DEVICE_ID_INTEL_82371AB: 509 case PCI_DEVICE_ID_INTEL_82443MX_1: 510 case PCI_DEVICE_ID_INTEL_82451NX: 511 case PCI_DEVICE_ID_INTEL_82801AB_1: 512 hwif->ultra_mask = 0x07; 513 break; 514 default: 515 pci_read_config_byte(hwif->pci_dev, 0x54, ®54h); 516 pci_read_config_byte(hwif->pci_dev, 0x55, ®55h); 517 ata66 = (reg54h & mask) ? 1 : 0; 518 break; 519 } 520 521 if (!(hwif->udma_four)) 522 hwif->udma_four = ata66; 523 hwif->ide_dma_check = &piix_config_drive_xfer_rate; 524 if (!noautodma) 525 hwif->autodma = 1; 526 527 hwif->drives[1].autodma = hwif->autodma; 528 hwif->drives[0].autodma = hwif->autodma; 529} 530 531#define DECLARE_PIIX_DEV(name_str) \ 532 { \ 533 .name = name_str, \ 534 .init_chipset = init_chipset_piix, \ 535 .init_hwif = init_hwif_piix, \ 536 .channels = 2, \ 537 .autodma = AUTODMA, \ 538 .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \ 539 .bootable = ON_BOARD, \ 540 } 541 542static ide_pci_device_t piix_pci_info[] __devinitdata = { 543 /* 0 */ DECLARE_PIIX_DEV("PIIXa"), 544 /* 1 */ DECLARE_PIIX_DEV("PIIXb"), 545 546 { /* 2 */ 547 .name = "MPIIX", 548 .init_hwif = init_hwif_piix, 549 .channels = 2, 550 .autodma = NODMA, 551 .enablebits = {{0x6D,0x80,0x80}, {0x6F,0x80,0x80}}, 552 .bootable = ON_BOARD, 553 }, 554 555 /* 3 */ DECLARE_PIIX_DEV("PIIX3"), 556 /* 4 */ DECLARE_PIIX_DEV("PIIX4"), 557 /* 5 */ DECLARE_PIIX_DEV("ICH0"), 558 /* 6 */ DECLARE_PIIX_DEV("PIIX4"), 559 /* 7 */ DECLARE_PIIX_DEV("ICH"), 560 /* 8 */ DECLARE_PIIX_DEV("PIIX4"), 561 /* 9 */ DECLARE_PIIX_DEV("PIIX4"), 562 /* 10 */ DECLARE_PIIX_DEV("ICH2"), 563 /* 11 */ DECLARE_PIIX_DEV("ICH2M"), 564 /* 12 */ DECLARE_PIIX_DEV("ICH3M"), 565 /* 13 */ DECLARE_PIIX_DEV("ICH3"), 566 /* 14 */ DECLARE_PIIX_DEV("ICH4"), 567 /* 15 */ DECLARE_PIIX_DEV("ICH5"), 568 /* 16 */ DECLARE_PIIX_DEV("C-ICH"), 569 /* 17 */ DECLARE_PIIX_DEV("ICH4"), 570 /* 18 */ DECLARE_PIIX_DEV("ICH5-SATA"), 571 /* 19 */ DECLARE_PIIX_DEV("ICH5"), 572 /* 20 */ DECLARE_PIIX_DEV("ICH6"), 573 /* 21 */ DECLARE_PIIX_DEV("ICH7"), 574 /* 22 */ DECLARE_PIIX_DEV("ICH4"), 575}; 576 577/** 578 * piix_init_one - called when a PIIX is found 579 * @dev: the piix device 580 * @id: the matching pci id 581 * 582 * Called when the PCI registration layer (or the IDE initialization) 583 * finds a device matching our IDE device tables. 584 */ 585 586static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id) 587{ 588 ide_pci_device_t *d = &piix_pci_info[id->driver_data]; 589 590 return ide_setup_pci_device(dev, d); 591} 592 593/** 594 * piix_check_450nx - Check for problem 450NX setup 595 * 596 * Check for the present of 450NX errata #19 and errata #25. If 597 * they are found, disable use of DMA IDE 598 */ 599 600static void __devinit piix_check_450nx(void) 601{ 602 struct pci_dev *pdev = NULL; 603 u16 cfg; 604 u8 rev; 605 while((pdev=pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL) 606 { 607 /* Look for 450NX PXB. Check for problem configurations 608 A PCI quirk checks bit 6 already */ 609 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); 610 pci_read_config_word(pdev, 0x41, &cfg); 611 /* Only on the original revision: IDE DMA can hang */ 612 if(rev == 0x00) 613 no_piix_dma = 1; 614 /* On all revisions below 5 PXB bus lock must be disabled for IDE */ 615 else if(cfg & (1<<14) && rev < 5) 616 no_piix_dma = 2; 617 } 618 if(no_piix_dma) 619 printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n"); 620 if(no_piix_dma == 2) 621 printk(KERN_WARNING "piix: A BIOS update may resolve this.\n"); 622} 623 624static struct pci_device_id piix_pci_tbl[] = { 625 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 626 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, 627 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2}, 628 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3}, 629 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4}, 630 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5}, 631 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6}, 632 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7}, 633 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82372FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8}, 634 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9}, 635 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10}, 636 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11}, 637 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12}, 638 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13}, 639 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14}, 640 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 15}, 641 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_11, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 16}, 642 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 17}, 643#ifdef CONFIG_BLK_DEV_IDE_SATA 644 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 18}, 645#endif 646 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 19}, 647 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_19, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 20}, 648 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 21}, 649 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 22}, 650 { 0, }, 651}; 652MODULE_DEVICE_TABLE(pci, piix_pci_tbl); 653 654static struct pci_driver driver = { 655 .name = "PIIX_IDE", 656 .id_table = piix_pci_tbl, 657 .probe = piix_init_one, 658}; 659 660static int __init piix_ide_init(void) 661{ 662 piix_check_450nx(); 663 return ide_pci_register_driver(&driver); 664} 665 666module_init(piix_ide_init); 667 668MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz"); 669MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE"); 670MODULE_LICENSE("GPL");