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/drivers/ide/pci/cs5530.c

https://bitbucket.org/evzijst/gittest
C | 384 lines | 209 code | 47 blank | 128 comment | 44 complexity | 19f8a1f7246339b1155d92a026717dbe MD5 | raw file
  1/*
  2 * linux/drivers/ide/pci/cs5530.c		Version 0.7	Sept 10, 2002
  3 *
  4 * Copyright (C) 2000			Andre Hedrick <andre@linux-ide.org>
  5 * Ditto of GNU General Public License.
  6 *
  7 * Copyright (C) 2000			Mark Lord <mlord@pobox.com>
  8 * May be copied or modified under the terms of the GNU General Public License
  9 *
 10 * Development of this chipset driver was funded
 11 * by the nice folks at National Semiconductor.
 12 *
 13 * Documentation:
 14 *	CS5530 documentation available from National Semiconductor.
 15 */
 16
 17#include <linux/config.h>
 18#include <linux/module.h>
 19#include <linux/types.h>
 20#include <linux/kernel.h>
 21#include <linux/delay.h>
 22#include <linux/timer.h>
 23#include <linux/mm.h>
 24#include <linux/ioport.h>
 25#include <linux/blkdev.h>
 26#include <linux/hdreg.h>
 27#include <linux/interrupt.h>
 28#include <linux/pci.h>
 29#include <linux/init.h>
 30#include <linux/ide.h>
 31#include <asm/io.h>
 32#include <asm/irq.h>
 33
 34/**
 35 *	cs5530_xfer_set_mode	-	set a new transfer mode at the drive
 36 *	@drive: drive to tune
 37 *	@mode: new mode
 38 *
 39 *	Logging wrapper to the IDE driver speed configuration. This can
 40 *	probably go away now.
 41 */
 42 
 43static int cs5530_set_xfer_mode (ide_drive_t *drive, u8 mode)
 44{
 45	printk(KERN_DEBUG "%s: cs5530_set_xfer_mode(%s)\n",
 46		drive->name, ide_xfer_verbose(mode));
 47	return (ide_config_drive_speed(drive, mode));
 48}
 49
 50/*
 51 * Here are the standard PIO mode 0-4 timings for each "format".
 52 * Format-0 uses fast data reg timings, with slower command reg timings.
 53 * Format-1 uses fast timings for all registers, but won't work with all drives.
 54 */
 55static unsigned int cs5530_pio_timings[2][5] = {
 56	{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
 57	{0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
 58};
 59
 60/*
 61 * After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
 62 */
 63#define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
 64#define CS5530_BASEREG(hwif)	(((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))
 65
 66/**
 67 *	cs5530_tuneproc		-	select/set PIO modes
 68 *
 69 *	cs5530_tuneproc() handles selection/setting of PIO modes
 70 *	for both the chipset and drive.
 71 *
 72 *	The ide_init_cs5530() routine guarantees that all drives
 73 *	will have valid default PIO timings set up before we get here.
 74 */
 75
 76static void cs5530_tuneproc (ide_drive_t *drive, u8 pio)	/* pio=255 means "autotune" */
 77{
 78	ide_hwif_t	*hwif = HWIF(drive);
 79	unsigned int	format;
 80	unsigned long basereg = CS5530_BASEREG(hwif);
 81	static u8	modes[5] = { XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3, XFER_PIO_4};
 82
 83	pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
 84	if (!cs5530_set_xfer_mode(drive, modes[pio])) {
 85		format = (hwif->INL(basereg+4) >> 31) & 1;
 86		hwif->OUTL(cs5530_pio_timings[format][pio],
 87			basereg+(drive->select.b.unit<<3));
 88	}
 89}
 90
 91/**
 92 *	cs5530_config_dma	-	select/set DMA and UDMA modes
 93 *	@drive: drive to tune
 94 *
 95 *	cs5530_config_dma() handles selection/setting of DMA/UDMA modes
 96 *	for both the chipset and drive. The CS5530 has limitations about
 97 *	mixing DMA/UDMA on the same cable.
 98 */
 99 
100static int cs5530_config_dma (ide_drive_t *drive)
101{
102	int			udma_ok = 1, mode = 0;
103	ide_hwif_t		*hwif = HWIF(drive);
104	int			unit = drive->select.b.unit;
105	ide_drive_t		*mate = &hwif->drives[unit^1];
106	struct hd_driveid	*id = drive->id;
107	unsigned int		reg, timings;
108	unsigned long		basereg;
109
110	/*
111	 * Default to DMA-off in case we run into trouble here.
112	 */
113	hwif->ide_dma_off_quietly(drive);
114	/* turn off DMA while we fiddle */
115	hwif->ide_dma_host_off(drive);
116	/* clear DMA_capable bit */
117
118	/*
119	 * The CS5530 specifies that two drives sharing a cable cannot
120	 * mix UDMA/MDMA.  It has to be one or the other, for the pair,
121	 * though different timings can still be chosen for each drive.
122	 * We could set the appropriate timing bits on the fly,
123	 * but that might be a bit confusing.  So, for now we statically
124	 * handle this requirement by looking at our mate drive to see
125	 * what it is capable of, before choosing a mode for our own drive.
126	 *
127	 * Note: This relies on the fact we never fail from UDMA to MWDMA_2
128	 * but instead drop to PIO
129	 */
130	if (mate->present) {
131		struct hd_driveid *mateid = mate->id;
132		if (mateid && (mateid->capability & 1) &&
133		    !__ide_dma_bad_drive(mate)) {
134			if ((mateid->field_valid & 4) &&
135			    (mateid->dma_ultra & 7))
136				udma_ok = 1;
137			else if ((mateid->field_valid & 2) &&
138				 (mateid->dma_mword & 7))
139				udma_ok = 0;
140			else
141				udma_ok = 1;
142		}
143	}
144
145	/*
146	 * Now see what the current drive is capable of,
147	 * selecting UDMA only if the mate said it was ok.
148	 */
149	if (id && (id->capability & 1) && drive->autodma &&
150	    !__ide_dma_bad_drive(drive)) {
151		if (udma_ok && (id->field_valid & 4) && (id->dma_ultra & 7)) {
152			if      (id->dma_ultra & 4)
153				mode = XFER_UDMA_2;
154			else if (id->dma_ultra & 2)
155				mode = XFER_UDMA_1;
156			else if (id->dma_ultra & 1)
157				mode = XFER_UDMA_0;
158		}
159		if (!mode && (id->field_valid & 2) && (id->dma_mword & 7)) {
160			if      (id->dma_mword & 4)
161				mode = XFER_MW_DMA_2;
162			else if (id->dma_mword & 2)
163				mode = XFER_MW_DMA_1;
164			else if (id->dma_mword & 1)
165				mode = XFER_MW_DMA_0;
166		}
167	}
168
169	/*
170	 * Tell the drive to switch to the new mode; abort on failure.
171	 */
172	if (!mode || cs5530_set_xfer_mode(drive, mode))
173		return 1;	/* failure */
174
175	/*
176	 * Now tune the chipset to match the drive:
177	 */
178	switch (mode) {
179		case XFER_UDMA_0:	timings = 0x00921250; break;
180		case XFER_UDMA_1:	timings = 0x00911140; break;
181		case XFER_UDMA_2:	timings = 0x00911030; break;
182		case XFER_MW_DMA_0:	timings = 0x00077771; break;
183		case XFER_MW_DMA_1:	timings = 0x00012121; break;
184		case XFER_MW_DMA_2:	timings = 0x00002020; break;
185		default:
186			printk(KERN_ERR "%s: cs5530_config_dma: huh? mode=%02x\n",
187				drive->name, mode);
188			return 1;	/* failure */
189	}
190	basereg = CS5530_BASEREG(hwif);
191	reg = hwif->INL(basereg+4);		/* get drive0 config register */
192	timings |= reg & 0x80000000;		/* preserve PIO format bit */
193	if (unit == 0) {			/* are we configuring drive0? */
194		hwif->OUTL(timings, basereg+4);	/* write drive0 config register */
195	} else {
196		if (timings & 0x00100000)
197			reg |=  0x00100000;	/* enable UDMA timings for both drives */
198		else
199			reg &= ~0x00100000;	/* disable UDMA timings for both drives */
200		hwif->OUTL(reg,     basereg+4);	/* write drive0 config register */
201		hwif->OUTL(timings, basereg+12);	/* write drive1 config register */
202	}
203	(void) hwif->ide_dma_host_on(drive);
204	/* set DMA_capable bit */
205
206	/*
207	 * Finally, turn DMA on in software, and exit.
208	 */
209	return hwif->ide_dma_on(drive);	/* success */
210}
211
212/**
213 *	init_chipset_5530	-	set up 5530 bridge
214 *	@dev: PCI device
215 *	@name: device name
216 *
217 *	Initialize the cs5530 bridge for reliable IDE DMA operation.
218 */
219
220static unsigned int __init init_chipset_cs5530 (struct pci_dev *dev, const char *name)
221{
222	struct pci_dev *master_0 = NULL, *cs5530_0 = NULL;
223	unsigned long flags;
224
225	dev = NULL;
226	while ((dev = pci_find_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
227		switch (dev->device) {
228			case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
229				master_0 = dev;
230				break;
231			case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
232				cs5530_0 = dev;
233				break;
234		}
235	}
236	if (!master_0) {
237		printk(KERN_ERR "%s: unable to locate PCI MASTER function\n", name);
238		return 0;
239	}
240	if (!cs5530_0) {
241		printk(KERN_ERR "%s: unable to locate CS5530 LEGACY function\n", name);
242		return 0;
243	}
244
245	spin_lock_irqsave(&ide_lock, flags);
246		/* all CPUs (there should only be one CPU with this chipset) */
247
248	/*
249	 * Enable BusMaster and MemoryWriteAndInvalidate for the cs5530:
250	 * -->  OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530
251	 */
252
253	pci_set_master(cs5530_0);
254	pci_set_mwi(cs5530_0);
255
256	/*
257	 * Set PCI CacheLineSize to 16-bytes:
258	 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
259	 */
260
261	pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
262
263	/*
264	 * Disable trapping of UDMA register accesses (Win98 hack):
265	 * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
266	 */
267
268	pci_write_config_word(cs5530_0, 0xd0, 0x5006);
269
270	/*
271	 * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
272	 * The other settings are what is necessary to get the register
273	 * into a sane state for IDE DMA operation.
274	 */
275
276	pci_write_config_byte(master_0, 0x40, 0x1e);
277
278	/* 
279	 * Set max PCI burst size (16-bytes seems to work best):
280	 *	   16bytes: set bit-1 at 0x41 (reg value of 0x16)
281	 *	all others: clear bit-1 at 0x41, and do:
282	 *	  128bytes: OR 0x00 at 0x41
283	 *	  256bytes: OR 0x04 at 0x41
284	 *	  512bytes: OR 0x08 at 0x41
285	 *	 1024bytes: OR 0x0c at 0x41
286	 */
287
288	pci_write_config_byte(master_0, 0x41, 0x14);
289
290	/*
291	 * These settings are necessary to get the chip
292	 * into a sane state for IDE DMA operation.
293	 */
294
295	pci_write_config_byte(master_0, 0x42, 0x00);
296	pci_write_config_byte(master_0, 0x43, 0xc1);
297
298	spin_unlock_irqrestore(&ide_lock, flags);
299
300	return 0;
301}
302
303/**
304 *	init_hwif_cs5530	-	initialise an IDE channel
305 *	@hwif: IDE to initialize
306 *
307 *	This gets invoked by the IDE driver once for each channel. It
308 *	performs channel-specific pre-initialization before drive probing.
309 */
310
311static void __init init_hwif_cs5530 (ide_hwif_t *hwif)
312{
313	unsigned long basereg;
314	u32 d0_timings;
315	hwif->autodma = 0;
316
317	if (hwif->mate)
318		hwif->serialized = hwif->mate->serialized = 1;
319
320	hwif->tuneproc = &cs5530_tuneproc;
321	basereg = CS5530_BASEREG(hwif);
322	d0_timings = hwif->INL(basereg+0);
323	if (CS5530_BAD_PIO(d0_timings)) {
324		/* PIO timings not initialized? */
325		hwif->OUTL(cs5530_pio_timings[(d0_timings>>31)&1][0], basereg+0);
326		if (!hwif->drives[0].autotune)
327			hwif->drives[0].autotune = 1;
328			/* needs autotuning later */
329	}
330	if (CS5530_BAD_PIO(hwif->INL(basereg+8))) {
331	/* PIO timings not initialized? */
332		hwif->OUTL(cs5530_pio_timings[(d0_timings>>31)&1][0], basereg+8);
333		if (!hwif->drives[1].autotune)
334			hwif->drives[1].autotune = 1;
335			/* needs autotuning later */
336	}
337
338	hwif->atapi_dma = 1;
339	hwif->ultra_mask = 0x07;
340	hwif->mwdma_mask = 0x07;
341
342	hwif->ide_dma_check = &cs5530_config_dma;
343	if (!noautodma)
344		hwif->autodma = 1;
345	hwif->drives[0].autodma = hwif->autodma;
346	hwif->drives[1].autodma = hwif->autodma;
347}
348
349static ide_pci_device_t cs5530_chipset __devinitdata = {
350	.name		= "CS5530",
351	.init_chipset	= init_chipset_cs5530,
352	.init_hwif	= init_hwif_cs5530,
353	.channels	= 2,
354	.autodma	= AUTODMA,
355	.bootable	= ON_BOARD,
356};
357
358static int __devinit cs5530_init_one(struct pci_dev *dev, const struct pci_device_id *id)
359{
360	return ide_setup_pci_device(dev, &cs5530_chipset);
361}
362
363static struct pci_device_id cs5530_pci_tbl[] = {
364	{ PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
365	{ 0, },
366};
367MODULE_DEVICE_TABLE(pci, cs5530_pci_tbl);
368
369static struct pci_driver driver = {
370	.name		= "CS5530 IDE",
371	.id_table	= cs5530_pci_tbl,
372	.probe		= cs5530_init_one,
373};
374
375static int cs5530_ide_init(void)
376{
377	return ide_pci_register_driver(&driver);
378}
379
380module_init(cs5530_ide_init);
381
382MODULE_AUTHOR("Mark Lord");
383MODULE_DESCRIPTION("PCI driver module for Cyrix/NS 5530 IDE");
384MODULE_LICENSE("GPL");