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/drivers/char/synclink.c

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   1/*
   2 * linux/drivers/char/synclink.c
   3 *
   4 * $Id: synclink.c,v 4.28 2004/08/11 19:30:01 paulkf Exp $
   5 *
   6 * Device driver for Microgate SyncLink ISA and PCI
   7 * high speed multiprotocol serial adapters.
   8 *
   9 * written by Paul Fulghum for Microgate Corporation
  10 * paulkf@microgate.com
  11 *
  12 * Microgate and SyncLink are trademarks of Microgate Corporation
  13 *
  14 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  15 *
  16 * Original release 01/11/99
  17 *
  18 * This code is released under the GNU General Public License (GPL)
  19 *
  20 * This driver is primarily intended for use in synchronous
  21 * HDLC mode. Asynchronous mode is also provided.
  22 *
  23 * When operating in synchronous mode, each call to mgsl_write()
  24 * contains exactly one complete HDLC frame. Calling mgsl_put_char
  25 * will start assembling an HDLC frame that will not be sent until
  26 * mgsl_flush_chars or mgsl_write is called.
  27 * 
  28 * Synchronous receive data is reported as complete frames. To accomplish
  29 * this, the TTY flip buffer is bypassed (too small to hold largest
  30 * frame and may fragment frames) and the line discipline
  31 * receive entry point is called directly.
  32 *
  33 * This driver has been tested with a slightly modified ppp.c driver
  34 * for synchronous PPP.
  35 *
  36 * 2000/02/16
  37 * Added interface for syncppp.c driver (an alternate synchronous PPP
  38 * implementation that also supports Cisco HDLC). Each device instance
  39 * registers as a tty device AND a network device (if dosyncppp option
  40 * is set for the device). The functionality is determined by which
  41 * device interface is opened.
  42 *
  43 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  45 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  46 * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  51 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  53 * OF THE POSSIBILITY OF SUCH DAMAGE.
  54 */
  55
  56#if defined(__i386__)
  57#  define BREAKPOINT() asm("   int $3");
  58#else
  59#  define BREAKPOINT() { }
  60#endif
  61
  62#define MAX_ISA_DEVICES 10
  63#define MAX_PCI_DEVICES 10
  64#define MAX_TOTAL_DEVICES 20
  65
  66#include <linux/config.h>	
  67#include <linux/module.h>
  68#include <linux/errno.h>
  69#include <linux/signal.h>
  70#include <linux/sched.h>
  71#include <linux/timer.h>
  72#include <linux/interrupt.h>
  73#include <linux/pci.h>
  74#include <linux/tty.h>
  75#include <linux/tty_flip.h>
  76#include <linux/serial.h>
  77#include <linux/major.h>
  78#include <linux/string.h>
  79#include <linux/fcntl.h>
  80#include <linux/ptrace.h>
  81#include <linux/ioport.h>
  82#include <linux/mm.h>
  83#include <linux/slab.h>
  84#include <linux/delay.h>
  85
  86#include <linux/netdevice.h>
  87
  88#include <linux/vmalloc.h>
  89#include <linux/init.h>
  90#include <asm/serial.h>
  91
  92#include <linux/delay.h>
  93#include <linux/ioctl.h>
  94
  95#include <asm/system.h>
  96#include <asm/io.h>
  97#include <asm/irq.h>
  98#include <asm/dma.h>
  99#include <linux/bitops.h>
 100#include <asm/types.h>
 101#include <linux/termios.h>
 102#include <linux/workqueue.h>
 103#include <linux/hdlc.h>
 104
 105#ifdef CONFIG_HDLC_MODULE
 106#define CONFIG_HDLC 1
 107#endif
 108
 109#define GET_USER(error,value,addr) error = get_user(value,addr)
 110#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
 111#define PUT_USER(error,value,addr) error = put_user(value,addr)
 112#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
 113
 114#include <asm/uaccess.h>
 115
 116#include "linux/synclink.h"
 117
 118#define RCLRVALUE 0xffff
 119
 120static MGSL_PARAMS default_params = {
 121	MGSL_MODE_HDLC,			/* unsigned long mode */
 122	0,				/* unsigned char loopback; */
 123	HDLC_FLAG_UNDERRUN_ABORT15,	/* unsigned short flags; */
 124	HDLC_ENCODING_NRZI_SPACE,	/* unsigned char encoding; */
 125	0,				/* unsigned long clock_speed; */
 126	0xff,				/* unsigned char addr_filter; */
 127	HDLC_CRC_16_CCITT,		/* unsigned short crc_type; */
 128	HDLC_PREAMBLE_LENGTH_8BITS,	/* unsigned char preamble_length; */
 129	HDLC_PREAMBLE_PATTERN_NONE,	/* unsigned char preamble; */
 130	9600,				/* unsigned long data_rate; */
 131	8,				/* unsigned char data_bits; */
 132	1,				/* unsigned char stop_bits; */
 133	ASYNC_PARITY_NONE		/* unsigned char parity; */
 134};
 135
 136#define SHARED_MEM_ADDRESS_SIZE 0x40000
 137#define BUFFERLISTSIZE (PAGE_SIZE)
 138#define DMABUFFERSIZE (PAGE_SIZE)
 139#define MAXRXFRAMES 7
 140
 141typedef struct _DMABUFFERENTRY
 142{
 143	u32 phys_addr;	/* 32-bit flat physical address of data buffer */
 144	u16 count;	/* buffer size/data count */
 145	u16 status;	/* Control/status field */
 146	u16 rcc;	/* character count field */
 147	u16 reserved;	/* padding required by 16C32 */
 148	u32 link;	/* 32-bit flat link to next buffer entry */
 149	char *virt_addr;	/* virtual address of data buffer */
 150	u32 phys_entry;	/* physical address of this buffer entry */
 151} DMABUFFERENTRY, *DMAPBUFFERENTRY;
 152
 153/* The queue of BH actions to be performed */
 154
 155#define BH_RECEIVE  1
 156#define BH_TRANSMIT 2
 157#define BH_STATUS   4
 158
 159#define IO_PIN_SHUTDOWN_LIMIT 100
 160
 161#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
 162
 163struct	_input_signal_events {
 164	int	ri_up;	
 165	int	ri_down;
 166	int	dsr_up;
 167	int	dsr_down;
 168	int	dcd_up;
 169	int	dcd_down;
 170	int	cts_up;
 171	int	cts_down;
 172};
 173
 174/* transmit holding buffer definitions*/
 175#define MAX_TX_HOLDING_BUFFERS 5
 176struct tx_holding_buffer {
 177	int	buffer_size;
 178	unsigned char *	buffer;
 179};
 180
 181
 182/*
 183 * Device instance data structure
 184 */
 185 
 186struct mgsl_struct {
 187	int			magic;
 188	int			flags;
 189	int			count;		/* count of opens */
 190	int			line;
 191	int                     hw_version;
 192	unsigned short		close_delay;
 193	unsigned short		closing_wait;	/* time to wait before closing */
 194	
 195	struct mgsl_icount	icount;
 196	
 197	struct tty_struct 	*tty;
 198	int			timeout;
 199	int			x_char;		/* xon/xoff character */
 200	int			blocked_open;	/* # of blocked opens */
 201	u16			read_status_mask;
 202	u16			ignore_status_mask;	
 203	unsigned char 		*xmit_buf;
 204	int			xmit_head;
 205	int			xmit_tail;
 206	int			xmit_cnt;
 207	
 208	wait_queue_head_t	open_wait;
 209	wait_queue_head_t	close_wait;
 210	
 211	wait_queue_head_t	status_event_wait_q;
 212	wait_queue_head_t	event_wait_q;
 213	struct timer_list	tx_timer;	/* HDLC transmit timeout timer */
 214	struct mgsl_struct	*next_device;	/* device list link */
 215	
 216	spinlock_t irq_spinlock;		/* spinlock for synchronizing with ISR */
 217	struct work_struct task;		/* task structure for scheduling bh */
 218
 219	u32 EventMask;			/* event trigger mask */
 220	u32 RecordedEvents;		/* pending events */
 221
 222	u32 max_frame_size;		/* as set by device config */
 223
 224	u32 pending_bh;
 225
 226	int bh_running;		/* Protection from multiple */
 227	int isr_overflow;
 228	int bh_requested;
 229	
 230	int dcd_chkcount;		/* check counts to prevent */
 231	int cts_chkcount;		/* too many IRQs if a signal */
 232	int dsr_chkcount;		/* is floating */
 233	int ri_chkcount;
 234
 235	char *buffer_list;		/* virtual address of Rx & Tx buffer lists */
 236	unsigned long buffer_list_phys;
 237
 238	unsigned int rx_buffer_count;	/* count of total allocated Rx buffers */
 239	DMABUFFERENTRY *rx_buffer_list;	/* list of receive buffer entries */
 240	unsigned int current_rx_buffer;
 241
 242	int num_tx_dma_buffers;		/* number of tx dma frames required */
 243 	int tx_dma_buffers_used;
 244	unsigned int tx_buffer_count;	/* count of total allocated Tx buffers */
 245	DMABUFFERENTRY *tx_buffer_list;	/* list of transmit buffer entries */
 246	int start_tx_dma_buffer;	/* tx dma buffer to start tx dma operation */
 247	int current_tx_buffer;          /* next tx dma buffer to be loaded */
 248	
 249	unsigned char *intermediate_rxbuffer;
 250
 251	int num_tx_holding_buffers;	/* number of tx holding buffer allocated */
 252	int get_tx_holding_index;  	/* next tx holding buffer for adapter to load */
 253	int put_tx_holding_index;  	/* next tx holding buffer to store user request */
 254	int tx_holding_count;		/* number of tx holding buffers waiting */
 255	struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
 256
 257	int rx_enabled;
 258	int rx_overflow;
 259	int rx_rcc_underrun;
 260
 261	int tx_enabled;
 262	int tx_active;
 263	u32 idle_mode;
 264
 265	u16 cmr_value;
 266	u16 tcsr_value;
 267
 268	char device_name[25];		/* device instance name */
 269
 270	unsigned int bus_type;	/* expansion bus type (ISA,EISA,PCI) */
 271	unsigned char bus;		/* expansion bus number (zero based) */
 272	unsigned char function;		/* PCI device number */
 273
 274	unsigned int io_base;		/* base I/O address of adapter */
 275	unsigned int io_addr_size;	/* size of the I/O address range */
 276	int io_addr_requested;		/* nonzero if I/O address requested */
 277	
 278	unsigned int irq_level;		/* interrupt level */
 279	unsigned long irq_flags;
 280	int irq_requested;		/* nonzero if IRQ requested */
 281	
 282	unsigned int dma_level;		/* DMA channel */
 283	int dma_requested;		/* nonzero if dma channel requested */
 284
 285	u16 mbre_bit;
 286	u16 loopback_bits;
 287	u16 usc_idle_mode;
 288
 289	MGSL_PARAMS params;		/* communications parameters */
 290
 291	unsigned char serial_signals;	/* current serial signal states */
 292
 293	int irq_occurred;		/* for diagnostics use */
 294	unsigned int init_error;	/* Initialization startup error 		(DIAGS)	*/
 295	int	fDiagnosticsmode;	/* Driver in Diagnostic mode?			(DIAGS)	*/
 296
 297	u32 last_mem_alloc;
 298	unsigned char* memory_base;	/* shared memory address (PCI only) */
 299	u32 phys_memory_base;
 300	int shared_mem_requested;
 301
 302	unsigned char* lcr_base;	/* local config registers (PCI only) */
 303	u32 phys_lcr_base;
 304	u32 lcr_offset;
 305	int lcr_mem_requested;
 306
 307	u32 misc_ctrl_value;
 308	char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 309	char char_buf[MAX_ASYNC_BUFFER_SIZE];	
 310	BOOLEAN drop_rts_on_tx_done;
 311
 312	BOOLEAN loopmode_insert_requested;
 313	BOOLEAN	loopmode_send_done_requested;
 314	
 315	struct	_input_signal_events	input_signal_events;
 316
 317	/* generic HDLC device parts */
 318	int netcount;
 319	int dosyncppp;
 320	spinlock_t netlock;
 321
 322#ifdef CONFIG_HDLC
 323	struct net_device *netdev;
 324#endif
 325};
 326
 327#define MGSL_MAGIC 0x5401
 328
 329/*
 330 * The size of the serial xmit buffer is 1 page, or 4096 bytes
 331 */
 332#ifndef SERIAL_XMIT_SIZE
 333#define SERIAL_XMIT_SIZE 4096
 334#endif
 335
 336/*
 337 * These macros define the offsets used in calculating the
 338 * I/O address of the specified USC registers.
 339 */
 340
 341
 342#define DCPIN 2		/* Bit 1 of I/O address */
 343#define SDPIN 4		/* Bit 2 of I/O address */
 344
 345#define DCAR 0		/* DMA command/address register */
 346#define CCAR SDPIN		/* channel command/address register */
 347#define DATAREG DCPIN + SDPIN	/* serial data register */
 348#define MSBONLY 0x41
 349#define LSBONLY 0x40
 350
 351/*
 352 * These macros define the register address (ordinal number)
 353 * used for writing address/value pairs to the USC.
 354 */
 355
 356#define CMR	0x02	/* Channel mode Register */
 357#define CCSR	0x04	/* Channel Command/status Register */
 358#define CCR	0x06	/* Channel Control Register */
 359#define PSR	0x08	/* Port status Register */
 360#define PCR	0x0a	/* Port Control Register */
 361#define TMDR	0x0c	/* Test mode Data Register */
 362#define TMCR	0x0e	/* Test mode Control Register */
 363#define CMCR	0x10	/* Clock mode Control Register */
 364#define HCR	0x12	/* Hardware Configuration Register */
 365#define IVR	0x14	/* Interrupt Vector Register */
 366#define IOCR	0x16	/* Input/Output Control Register */
 367#define ICR	0x18	/* Interrupt Control Register */
 368#define DCCR	0x1a	/* Daisy Chain Control Register */
 369#define MISR	0x1c	/* Misc Interrupt status Register */
 370#define SICR	0x1e	/* status Interrupt Control Register */
 371#define RDR	0x20	/* Receive Data Register */
 372#define RMR	0x22	/* Receive mode Register */
 373#define RCSR	0x24	/* Receive Command/status Register */
 374#define RICR	0x26	/* Receive Interrupt Control Register */
 375#define RSR	0x28	/* Receive Sync Register */
 376#define RCLR	0x2a	/* Receive count Limit Register */
 377#define RCCR	0x2c	/* Receive Character count Register */
 378#define TC0R	0x2e	/* Time Constant 0 Register */
 379#define TDR	0x30	/* Transmit Data Register */
 380#define TMR	0x32	/* Transmit mode Register */
 381#define TCSR	0x34	/* Transmit Command/status Register */
 382#define TICR	0x36	/* Transmit Interrupt Control Register */
 383#define TSR	0x38	/* Transmit Sync Register */
 384#define TCLR	0x3a	/* Transmit count Limit Register */
 385#define TCCR	0x3c	/* Transmit Character count Register */
 386#define TC1R	0x3e	/* Time Constant 1 Register */
 387
 388
 389/*
 390 * MACRO DEFINITIONS FOR DMA REGISTERS
 391 */
 392
 393#define DCR	0x06	/* DMA Control Register (shared) */
 394#define DACR	0x08	/* DMA Array count Register (shared) */
 395#define BDCR	0x12	/* Burst/Dwell Control Register (shared) */
 396#define DIVR	0x14	/* DMA Interrupt Vector Register (shared) */	
 397#define DICR	0x18	/* DMA Interrupt Control Register (shared) */
 398#define CDIR	0x1a	/* Clear DMA Interrupt Register (shared) */
 399#define SDIR	0x1c	/* Set DMA Interrupt Register (shared) */
 400
 401#define TDMR	0x02	/* Transmit DMA mode Register */
 402#define TDIAR	0x1e	/* Transmit DMA Interrupt Arm Register */
 403#define TBCR	0x2a	/* Transmit Byte count Register */
 404#define TARL	0x2c	/* Transmit Address Register (low) */
 405#define TARU	0x2e	/* Transmit Address Register (high) */
 406#define NTBCR	0x3a	/* Next Transmit Byte count Register */
 407#define NTARL	0x3c	/* Next Transmit Address Register (low) */
 408#define NTARU	0x3e	/* Next Transmit Address Register (high) */
 409
 410#define RDMR	0x82	/* Receive DMA mode Register (non-shared) */
 411#define RDIAR	0x9e	/* Receive DMA Interrupt Arm Register */
 412#define RBCR	0xaa	/* Receive Byte count Register */
 413#define RARL	0xac	/* Receive Address Register (low) */
 414#define RARU	0xae	/* Receive Address Register (high) */
 415#define NRBCR	0xba	/* Next Receive Byte count Register */
 416#define NRARL	0xbc	/* Next Receive Address Register (low) */
 417#define NRARU	0xbe	/* Next Receive Address Register (high) */
 418
 419
 420/*
 421 * MACRO DEFINITIONS FOR MODEM STATUS BITS
 422 */
 423
 424#define MODEMSTATUS_DTR 0x80
 425#define MODEMSTATUS_DSR 0x40
 426#define MODEMSTATUS_RTS 0x20
 427#define MODEMSTATUS_CTS 0x10
 428#define MODEMSTATUS_RI  0x04
 429#define MODEMSTATUS_DCD 0x01
 430
 431
 432/*
 433 * Channel Command/Address Register (CCAR) Command Codes
 434 */
 435
 436#define RTCmd_Null			0x0000
 437#define RTCmd_ResetHighestIus		0x1000
 438#define RTCmd_TriggerChannelLoadDma	0x2000
 439#define RTCmd_TriggerRxDma		0x2800
 440#define RTCmd_TriggerTxDma		0x3000
 441#define RTCmd_TriggerRxAndTxDma		0x3800
 442#define RTCmd_PurgeRxFifo		0x4800
 443#define RTCmd_PurgeTxFifo		0x5000
 444#define RTCmd_PurgeRxAndTxFifo		0x5800
 445#define RTCmd_LoadRcc			0x6800
 446#define RTCmd_LoadTcc			0x7000
 447#define RTCmd_LoadRccAndTcc		0x7800
 448#define RTCmd_LoadTC0			0x8800
 449#define RTCmd_LoadTC1			0x9000
 450#define RTCmd_LoadTC0AndTC1		0x9800
 451#define RTCmd_SerialDataLSBFirst	0xa000
 452#define RTCmd_SerialDataMSBFirst	0xa800
 453#define RTCmd_SelectBigEndian		0xb000
 454#define RTCmd_SelectLittleEndian	0xb800
 455
 456
 457/*
 458 * DMA Command/Address Register (DCAR) Command Codes
 459 */
 460
 461#define DmaCmd_Null			0x0000
 462#define DmaCmd_ResetTxChannel		0x1000
 463#define DmaCmd_ResetRxChannel		0x1200
 464#define DmaCmd_StartTxChannel		0x2000
 465#define DmaCmd_StartRxChannel		0x2200
 466#define DmaCmd_ContinueTxChannel	0x3000
 467#define DmaCmd_ContinueRxChannel	0x3200
 468#define DmaCmd_PauseTxChannel		0x4000
 469#define DmaCmd_PauseRxChannel		0x4200
 470#define DmaCmd_AbortTxChannel		0x5000
 471#define DmaCmd_AbortRxChannel		0x5200
 472#define DmaCmd_InitTxChannel		0x7000
 473#define DmaCmd_InitRxChannel		0x7200
 474#define DmaCmd_ResetHighestDmaIus	0x8000
 475#define DmaCmd_ResetAllChannels		0x9000
 476#define DmaCmd_StartAllChannels		0xa000
 477#define DmaCmd_ContinueAllChannels	0xb000
 478#define DmaCmd_PauseAllChannels		0xc000
 479#define DmaCmd_AbortAllChannels		0xd000
 480#define DmaCmd_InitAllChannels		0xf000
 481
 482#define TCmd_Null			0x0000
 483#define TCmd_ClearTxCRC			0x2000
 484#define TCmd_SelectTicrTtsaData		0x4000
 485#define TCmd_SelectTicrTxFifostatus	0x5000
 486#define TCmd_SelectTicrIntLevel		0x6000
 487#define TCmd_SelectTicrdma_level		0x7000
 488#define TCmd_SendFrame			0x8000
 489#define TCmd_SendAbort			0x9000
 490#define TCmd_EnableDleInsertion		0xc000
 491#define TCmd_DisableDleInsertion	0xd000
 492#define TCmd_ClearEofEom		0xe000
 493#define TCmd_SetEofEom			0xf000
 494
 495#define RCmd_Null			0x0000
 496#define RCmd_ClearRxCRC			0x2000
 497#define RCmd_EnterHuntmode		0x3000
 498#define RCmd_SelectRicrRtsaData		0x4000
 499#define RCmd_SelectRicrRxFifostatus	0x5000
 500#define RCmd_SelectRicrIntLevel		0x6000
 501#define RCmd_SelectRicrdma_level		0x7000
 502
 503/*
 504 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
 505 */
 506 
 507#define RECEIVE_STATUS		BIT5
 508#define RECEIVE_DATA		BIT4
 509#define TRANSMIT_STATUS		BIT3
 510#define TRANSMIT_DATA		BIT2
 511#define IO_PIN			BIT1
 512#define MISC			BIT0
 513
 514
 515/*
 516 * Receive status Bits in Receive Command/status Register RCSR
 517 */
 518
 519#define RXSTATUS_SHORT_FRAME		BIT8
 520#define RXSTATUS_CODE_VIOLATION		BIT8
 521#define RXSTATUS_EXITED_HUNT		BIT7
 522#define RXSTATUS_IDLE_RECEIVED		BIT6
 523#define RXSTATUS_BREAK_RECEIVED		BIT5
 524#define RXSTATUS_ABORT_RECEIVED		BIT5
 525#define RXSTATUS_RXBOUND		BIT4
 526#define RXSTATUS_CRC_ERROR		BIT3
 527#define RXSTATUS_FRAMING_ERROR		BIT3
 528#define RXSTATUS_ABORT			BIT2
 529#define RXSTATUS_PARITY_ERROR		BIT2
 530#define RXSTATUS_OVERRUN		BIT1
 531#define RXSTATUS_DATA_AVAILABLE		BIT0
 532#define RXSTATUS_ALL			0x01f6
 533#define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
 534
 535/*
 536 * Values for setting transmit idle mode in 
 537 * Transmit Control/status Register (TCSR)
 538 */
 539#define IDLEMODE_FLAGS			0x0000
 540#define IDLEMODE_ALT_ONE_ZERO		0x0100
 541#define IDLEMODE_ZERO			0x0200
 542#define IDLEMODE_ONE			0x0300
 543#define IDLEMODE_ALT_MARK_SPACE		0x0500
 544#define IDLEMODE_SPACE			0x0600
 545#define IDLEMODE_MARK			0x0700
 546#define IDLEMODE_MASK			0x0700
 547
 548/*
 549 * IUSC revision identifiers
 550 */
 551#define	IUSC_SL1660			0x4d44
 552#define IUSC_PRE_SL1660			0x4553
 553
 554/*
 555 * Transmit status Bits in Transmit Command/status Register (TCSR)
 556 */
 557
 558#define TCSR_PRESERVE			0x0F00
 559
 560#define TCSR_UNDERWAIT			BIT11
 561#define TXSTATUS_PREAMBLE_SENT		BIT7
 562#define TXSTATUS_IDLE_SENT		BIT6
 563#define TXSTATUS_ABORT_SENT		BIT5
 564#define TXSTATUS_EOF_SENT		BIT4
 565#define TXSTATUS_EOM_SENT		BIT4
 566#define TXSTATUS_CRC_SENT		BIT3
 567#define TXSTATUS_ALL_SENT		BIT2
 568#define TXSTATUS_UNDERRUN		BIT1
 569#define TXSTATUS_FIFO_EMPTY		BIT0
 570#define TXSTATUS_ALL			0x00fa
 571#define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
 572				
 573
 574#define MISCSTATUS_RXC_LATCHED		BIT15
 575#define MISCSTATUS_RXC			BIT14
 576#define MISCSTATUS_TXC_LATCHED		BIT13
 577#define MISCSTATUS_TXC			BIT12
 578#define MISCSTATUS_RI_LATCHED		BIT11
 579#define MISCSTATUS_RI			BIT10
 580#define MISCSTATUS_DSR_LATCHED		BIT9
 581#define MISCSTATUS_DSR			BIT8
 582#define MISCSTATUS_DCD_LATCHED		BIT7
 583#define MISCSTATUS_DCD			BIT6
 584#define MISCSTATUS_CTS_LATCHED		BIT5
 585#define MISCSTATUS_CTS			BIT4
 586#define MISCSTATUS_RCC_UNDERRUN		BIT3
 587#define MISCSTATUS_DPLL_NO_SYNC		BIT2
 588#define MISCSTATUS_BRG1_ZERO		BIT1
 589#define MISCSTATUS_BRG0_ZERO		BIT0
 590
 591#define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
 592#define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
 593
 594#define SICR_RXC_ACTIVE			BIT15
 595#define SICR_RXC_INACTIVE		BIT14
 596#define SICR_RXC			(BIT15+BIT14)
 597#define SICR_TXC_ACTIVE			BIT13
 598#define SICR_TXC_INACTIVE		BIT12
 599#define SICR_TXC			(BIT13+BIT12)
 600#define SICR_RI_ACTIVE			BIT11
 601#define SICR_RI_INACTIVE		BIT10
 602#define SICR_RI				(BIT11+BIT10)
 603#define SICR_DSR_ACTIVE			BIT9
 604#define SICR_DSR_INACTIVE		BIT8
 605#define SICR_DSR			(BIT9+BIT8)
 606#define SICR_DCD_ACTIVE			BIT7
 607#define SICR_DCD_INACTIVE		BIT6
 608#define SICR_DCD			(BIT7+BIT6)
 609#define SICR_CTS_ACTIVE			BIT5
 610#define SICR_CTS_INACTIVE		BIT4
 611#define SICR_CTS			(BIT5+BIT4)
 612#define SICR_RCC_UNDERFLOW		BIT3
 613#define SICR_DPLL_NO_SYNC		BIT2
 614#define SICR_BRG1_ZERO			BIT1
 615#define SICR_BRG0_ZERO			BIT0
 616
 617void usc_DisableMasterIrqBit( struct mgsl_struct *info );
 618void usc_EnableMasterIrqBit( struct mgsl_struct *info );
 619void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
 620void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
 621void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
 622
 623#define usc_EnableInterrupts( a, b ) \
 624	usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
 625
 626#define usc_DisableInterrupts( a, b ) \
 627	usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
 628
 629#define usc_EnableMasterIrqBit(a) \
 630	usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
 631
 632#define usc_DisableMasterIrqBit(a) \
 633	usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
 634
 635#define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
 636
 637/*
 638 * Transmit status Bits in Transmit Control status Register (TCSR)
 639 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
 640 */
 641
 642#define TXSTATUS_PREAMBLE_SENT	BIT7
 643#define TXSTATUS_IDLE_SENT	BIT6
 644#define TXSTATUS_ABORT_SENT	BIT5
 645#define TXSTATUS_EOF		BIT4
 646#define TXSTATUS_CRC_SENT	BIT3
 647#define TXSTATUS_ALL_SENT	BIT2
 648#define TXSTATUS_UNDERRUN	BIT1
 649#define TXSTATUS_FIFO_EMPTY	BIT0
 650
 651#define DICR_MASTER		BIT15
 652#define DICR_TRANSMIT		BIT0
 653#define DICR_RECEIVE		BIT1
 654
 655#define usc_EnableDmaInterrupts(a,b) \
 656	usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
 657
 658#define usc_DisableDmaInterrupts(a,b) \
 659	usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
 660
 661#define usc_EnableStatusIrqs(a,b) \
 662	usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
 663
 664#define usc_DisablestatusIrqs(a,b) \
 665	usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
 666
 667/* Transmit status Bits in Transmit Control status Register (TCSR) */
 668/* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
 669
 670
 671#define DISABLE_UNCONDITIONAL    0
 672#define DISABLE_END_OF_FRAME     1
 673#define ENABLE_UNCONDITIONAL     2
 674#define ENABLE_AUTO_CTS          3
 675#define ENABLE_AUTO_DCD          3
 676#define usc_EnableTransmitter(a,b) \
 677	usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
 678#define usc_EnableReceiver(a,b) \
 679	usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
 680
 681static u16  usc_InDmaReg( struct mgsl_struct *info, u16 Port );
 682static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
 683static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
 684
 685static u16  usc_InReg( struct mgsl_struct *info, u16 Port );
 686static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
 687static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
 688void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
 689void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
 690
 691#define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
 692#define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
 693
 694#define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
 695
 696static void usc_process_rxoverrun_sync( struct mgsl_struct *info );
 697static void usc_start_receiver( struct mgsl_struct *info );
 698static void usc_stop_receiver( struct mgsl_struct *info );
 699
 700static void usc_start_transmitter( struct mgsl_struct *info );
 701static void usc_stop_transmitter( struct mgsl_struct *info );
 702static void usc_set_txidle( struct mgsl_struct *info );
 703static void usc_load_txfifo( struct mgsl_struct *info );
 704
 705static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
 706static void usc_enable_loopback( struct mgsl_struct *info, int enable );
 707
 708static void usc_get_serial_signals( struct mgsl_struct *info );
 709static void usc_set_serial_signals( struct mgsl_struct *info );
 710
 711static void usc_reset( struct mgsl_struct *info );
 712
 713static void usc_set_sync_mode( struct mgsl_struct *info );
 714static void usc_set_sdlc_mode( struct mgsl_struct *info );
 715static void usc_set_async_mode( struct mgsl_struct *info );
 716static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
 717
 718static void usc_loopback_frame( struct mgsl_struct *info );
 719
 720static void mgsl_tx_timeout(unsigned long context);
 721
 722
 723static void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
 724static void usc_loopmode_insert_request( struct mgsl_struct * info );
 725static int usc_loopmode_active( struct mgsl_struct * info);
 726static void usc_loopmode_send_done( struct mgsl_struct * info );
 727
 728static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
 729
 730#ifdef CONFIG_HDLC
 731#define dev_to_port(D) (dev_to_hdlc(D)->priv)
 732static void hdlcdev_tx_done(struct mgsl_struct *info);
 733static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size);
 734static int  hdlcdev_init(struct mgsl_struct *info);
 735static void hdlcdev_exit(struct mgsl_struct *info);
 736#endif
 737
 738/*
 739 * Defines a BUS descriptor value for the PCI adapter
 740 * local bus address ranges.
 741 */
 742
 743#define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
 744(0x00400020 + \
 745((WrHold) << 30) + \
 746((WrDly)  << 28) + \
 747((RdDly)  << 26) + \
 748((Nwdd)   << 20) + \
 749((Nwad)   << 15) + \
 750((Nxda)   << 13) + \
 751((Nrdd)   << 11) + \
 752((Nrad)   <<  6) )
 753
 754static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
 755
 756/*
 757 * Adapter diagnostic routines
 758 */
 759static BOOLEAN mgsl_register_test( struct mgsl_struct *info );
 760static BOOLEAN mgsl_irq_test( struct mgsl_struct *info );
 761static BOOLEAN mgsl_dma_test( struct mgsl_struct *info );
 762static BOOLEAN mgsl_memory_test( struct mgsl_struct *info );
 763static int mgsl_adapter_test( struct mgsl_struct *info );
 764
 765/*
 766 * device and resource management routines
 767 */
 768static int mgsl_claim_resources(struct mgsl_struct *info);
 769static void mgsl_release_resources(struct mgsl_struct *info);
 770static void mgsl_add_device(struct mgsl_struct *info);
 771static struct mgsl_struct* mgsl_allocate_device(void);
 772
 773/*
 774 * DMA buffer manupulation functions.
 775 */
 776static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
 777static int  mgsl_get_rx_frame( struct mgsl_struct *info );
 778static int  mgsl_get_raw_rx_frame( struct mgsl_struct *info );
 779static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
 780static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
 781static int num_free_tx_dma_buffers(struct mgsl_struct *info);
 782static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
 783static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
 784
 785/*
 786 * DMA and Shared Memory buffer allocation and formatting
 787 */
 788static int  mgsl_allocate_dma_buffers(struct mgsl_struct *info);
 789static void mgsl_free_dma_buffers(struct mgsl_struct *info);
 790static int  mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
 791static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
 792static int  mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
 793static void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
 794static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
 795static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
 796static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
 797static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
 798static int load_next_tx_holding_buffer(struct mgsl_struct *info);
 799static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
 800
 801/*
 802 * Bottom half interrupt handlers
 803 */
 804static void mgsl_bh_handler(void* Context);
 805static void mgsl_bh_receive(struct mgsl_struct *info);
 806static void mgsl_bh_transmit(struct mgsl_struct *info);
 807static void mgsl_bh_status(struct mgsl_struct *info);
 808
 809/*
 810 * Interrupt handler routines and dispatch table.
 811 */
 812static void mgsl_isr_null( struct mgsl_struct *info );
 813static void mgsl_isr_transmit_data( struct mgsl_struct *info );
 814static void mgsl_isr_receive_data( struct mgsl_struct *info );
 815static void mgsl_isr_receive_status( struct mgsl_struct *info );
 816static void mgsl_isr_transmit_status( struct mgsl_struct *info );
 817static void mgsl_isr_io_pin( struct mgsl_struct *info );
 818static void mgsl_isr_misc( struct mgsl_struct *info );
 819static void mgsl_isr_receive_dma( struct mgsl_struct *info );
 820static void mgsl_isr_transmit_dma( struct mgsl_struct *info );
 821
 822typedef void (*isr_dispatch_func)(struct mgsl_struct *);
 823
 824static isr_dispatch_func UscIsrTable[7] =
 825{
 826	mgsl_isr_null,
 827	mgsl_isr_misc,
 828	mgsl_isr_io_pin,
 829	mgsl_isr_transmit_data,
 830	mgsl_isr_transmit_status,
 831	mgsl_isr_receive_data,
 832	mgsl_isr_receive_status
 833};
 834
 835/*
 836 * ioctl call handlers
 837 */
 838static int tiocmget(struct tty_struct *tty, struct file *file);
 839static int tiocmset(struct tty_struct *tty, struct file *file,
 840		    unsigned int set, unsigned int clear);
 841static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
 842	__user *user_icount);
 843static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS  __user *user_params);
 844static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS  __user *new_params);
 845static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode);
 846static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
 847static int mgsl_txenable(struct mgsl_struct * info, int enable);
 848static int mgsl_txabort(struct mgsl_struct * info);
 849static int mgsl_rxenable(struct mgsl_struct * info, int enable);
 850static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask);
 851static int mgsl_loopmode_send_done( struct mgsl_struct * info );
 852
 853/* set non-zero on successful registration with PCI subsystem */
 854static int pci_registered;
 855
 856/*
 857 * Global linked list of SyncLink devices
 858 */
 859static struct mgsl_struct *mgsl_device_list;
 860static int mgsl_device_count;
 861
 862/*
 863 * Set this param to non-zero to load eax with the
 864 * .text section address and breakpoint on module load.
 865 * This is useful for use with gdb and add-symbol-file command.
 866 */
 867static int break_on_load;
 868
 869/*
 870 * Driver major number, defaults to zero to get auto
 871 * assigned major number. May be forced as module parameter.
 872 */
 873static int ttymajor;
 874
 875/*
 876 * Array of user specified options for ISA adapters.
 877 */
 878static int io[MAX_ISA_DEVICES];
 879static int irq[MAX_ISA_DEVICES];
 880static int dma[MAX_ISA_DEVICES];
 881static int debug_level;
 882static int maxframe[MAX_TOTAL_DEVICES];
 883static int dosyncppp[MAX_TOTAL_DEVICES];
 884static int txdmabufs[MAX_TOTAL_DEVICES];
 885static int txholdbufs[MAX_TOTAL_DEVICES];
 886	
 887module_param(break_on_load, bool, 0);
 888module_param(ttymajor, int, 0);
 889module_param_array(io, int, NULL, 0);
 890module_param_array(irq, int, NULL, 0);
 891module_param_array(dma, int, NULL, 0);
 892module_param(debug_level, int, 0);
 893module_param_array(maxframe, int, NULL, 0);
 894module_param_array(dosyncppp, int, NULL, 0);
 895module_param_array(txdmabufs, int, NULL, 0);
 896module_param_array(txholdbufs, int, NULL, 0);
 897
 898static char *driver_name = "SyncLink serial driver";
 899static char *driver_version = "$Revision: 4.28 $";
 900
 901static int synclink_init_one (struct pci_dev *dev,
 902				     const struct pci_device_id *ent);
 903static void synclink_remove_one (struct pci_dev *dev);
 904
 905static struct pci_device_id synclink_pci_tbl[] = {
 906	{ PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
 907	{ PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
 908	{ 0, }, /* terminate list */
 909};
 910MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
 911
 912MODULE_LICENSE("GPL");
 913
 914static struct pci_driver synclink_pci_driver = {
 915	.name		= "synclink",
 916	.id_table	= synclink_pci_tbl,
 917	.probe		= synclink_init_one,
 918	.remove		= __devexit_p(synclink_remove_one),
 919};
 920
 921static struct tty_driver *serial_driver;
 922
 923/* number of characters left in xmit buffer before we ask for more */
 924#define WAKEUP_CHARS 256
 925
 926
 927static void mgsl_change_params(struct mgsl_struct *info);
 928static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
 929
 930/*
 931 * 1st function defined in .text section. Calling this function in
 932 * init_module() followed by a breakpoint allows a remote debugger
 933 * (gdb) to get the .text address for the add-symbol-file command.
 934 * This allows remote debugging of dynamically loadable modules.
 935 */
 936static void* mgsl_get_text_ptr(void)
 937{
 938	return mgsl_get_text_ptr;
 939}
 940
 941/*
 942 * tmp_buf is used as a temporary buffer by mgsl_write.  We need to
 943 * lock it in case the COPY_FROM_USER blocks while swapping in a page,
 944 * and some other program tries to do a serial write at the same time.
 945 * Since the lock will only come under contention when the system is
 946 * swapping and available memory is low, it makes sense to share one
 947 * buffer across all the serial ioports, since it significantly saves
 948 * memory if large numbers of serial ports are open.
 949 */
 950static unsigned char *tmp_buf;
 951static DECLARE_MUTEX(tmp_buf_sem);
 952
 953static inline int mgsl_paranoia_check(struct mgsl_struct *info,
 954					char *name, const char *routine)
 955{
 956#ifdef MGSL_PARANOIA_CHECK
 957	static const char *badmagic =
 958		"Warning: bad magic number for mgsl struct (%s) in %s\n";
 959	static const char *badinfo =
 960		"Warning: null mgsl_struct for (%s) in %s\n";
 961
 962	if (!info) {
 963		printk(badinfo, name, routine);
 964		return 1;
 965	}
 966	if (info->magic != MGSL_MAGIC) {
 967		printk(badmagic, name, routine);
 968		return 1;
 969	}
 970#else
 971	if (!info)
 972		return 1;
 973#endif
 974	return 0;
 975}
 976
 977/**
 978 * line discipline callback wrappers
 979 *
 980 * The wrappers maintain line discipline references
 981 * while calling into the line discipline.
 982 *
 983 * ldisc_receive_buf  - pass receive data to line discipline
 984 */
 985
 986static void ldisc_receive_buf(struct tty_struct *tty,
 987			      const __u8 *data, char *flags, int count)
 988{
 989	struct tty_ldisc *ld;
 990	if (!tty)
 991		return;
 992	ld = tty_ldisc_ref(tty);
 993	if (ld) {
 994		if (ld->receive_buf)
 995			ld->receive_buf(tty, data, flags, count);
 996		tty_ldisc_deref(ld);
 997	}
 998}
 999
1000/* mgsl_stop()		throttle (stop) transmitter
1001 * 	
1002 * Arguments:		tty	pointer to tty info structure
1003 * Return Value:	None
1004 */
1005static void mgsl_stop(struct tty_struct *tty)
1006{
1007	struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
1008	unsigned long flags;
1009	
1010	if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
1011		return;
1012	
1013	if ( debug_level >= DEBUG_LEVEL_INFO )
1014		printk("mgsl_stop(%s)\n",info->device_name);	
1015		
1016	spin_lock_irqsave(&info->irq_spinlock,flags);
1017	if (info->tx_enabled)
1018	 	usc_stop_transmitter(info);
1019	spin_unlock_irqrestore(&info->irq_spinlock,flags);
1020	
1021}	/* end of mgsl_stop() */
1022
1023/* mgsl_start()		release (start) transmitter
1024 * 	
1025 * Arguments:		tty	pointer to tty info structure
1026 * Return Value:	None
1027 */
1028static void mgsl_start(struct tty_struct *tty)
1029{
1030	struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
1031	unsigned long flags;
1032	
1033	if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
1034		return;
1035	
1036	if ( debug_level >= DEBUG_LEVEL_INFO )
1037		printk("mgsl_start(%s)\n",info->device_name);	
1038		
1039	spin_lock_irqsave(&info->irq_spinlock,flags);
1040	if (!info->tx_enabled)
1041	 	usc_start_transmitter(info);
1042	spin_unlock_irqrestore(&info->irq_spinlock,flags);
1043	
1044}	/* end of mgsl_start() */
1045
1046/*
1047 * Bottom half work queue access functions
1048 */
1049
1050/* mgsl_bh_action()	Return next bottom half action to perform.
1051 * Return Value:	BH action code or 0 if nothing to do.
1052 */
1053static int mgsl_bh_action(struct mgsl_struct *info)
1054{
1055	unsigned long flags;
1056	int rc = 0;
1057	
1058	spin_lock_irqsave(&info->irq_spinlock,flags);
1059
1060	if (info->pending_bh & BH_RECEIVE) {
1061		info->pending_bh &= ~BH_RECEIVE;
1062		rc = BH_RECEIVE;
1063	} else if (info->pending_bh & BH_TRANSMIT) {
1064		info->pending_bh &= ~BH_TRANSMIT;
1065		rc = BH_TRANSMIT;
1066	} else if (info->pending_bh & BH_STATUS) {
1067		info->pending_bh &= ~BH_STATUS;
1068		rc = BH_STATUS;
1069	}
1070
1071	if (!rc) {
1072		/* Mark BH routine as complete */
1073		info->bh_running   = 0;
1074		info->bh_requested = 0;
1075	}
1076	
1077	spin_unlock_irqrestore(&info->irq_spinlock,flags);
1078	
1079	return rc;
1080}
1081
1082/*
1083 * 	Perform bottom half processing of work items queued by ISR.
1084 */
1085static void mgsl_bh_handler(void* Context)
1086{
1087	struct mgsl_struct *info = (struct mgsl_struct*)Context;
1088	int action;
1089
1090	if (!info)
1091		return;
1092		
1093	if ( debug_level >= DEBUG_LEVEL_BH )
1094		printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1095			__FILE__,__LINE__,info->device_name);
1096	
1097	info->bh_running = 1;
1098
1099	while((action = mgsl_bh_action(info)) != 0) {
1100	
1101		/* Process work item */
1102		if ( debug_level >= DEBUG_LEVEL_BH )
1103			printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1104				__FILE__,__LINE__,action);
1105
1106		switch (action) {
1107		
1108		case BH_RECEIVE:
1109			mgsl_bh_receive(info);
1110			break;
1111		case BH_TRANSMIT:
1112			mgsl_bh_transmit(info);
1113			break;
1114		case BH_STATUS:
1115			mgsl_bh_status(info);
1116			break;
1117		default:
1118			/* unknown work item ID */
1119			printk("Unknown work item ID=%08X!\n", action);
1120			break;
1121		}
1122	}
1123
1124	if ( debug_level >= DEBUG_LEVEL_BH )
1125		printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1126			__FILE__,__LINE__,info->device_name);
1127}
1128
1129static void mgsl_bh_receive(struct mgsl_struct *info)
1130{
1131	int (*get_rx_frame)(struct mgsl_struct *info) =
1132		(info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
1133
1134	if ( debug_level >= DEBUG_LEVEL_BH )
1135		printk( "%s(%d):mgsl_bh_receive(%s)\n",
1136			__FILE__,__LINE__,info->device_name);
1137	
1138	do
1139	{
1140		if (info->rx_rcc_underrun) {
1141			unsigned long flags;
1142			spin_lock_irqsave(&info->irq_spinlock,flags);
1143			usc_start_receiver(info);
1144			spin_unlock_irqrestore(&info->irq_spinlock,flags);
1145			return;
1146		}
1147	} while(get_rx_frame(info));
1148}
1149
1150static void mgsl_bh_transmit(struct mgsl_struct *info)
1151{
1152	struct tty_struct *tty = info->tty;
1153	unsigned long flags;
1154	
1155	if ( debug_level >= DEBUG_LEVEL_BH )
1156		printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1157			__FILE__,__LINE__,info->device_name);
1158
1159	if (tty) {
1160		tty_wakeup(tty);
1161		wake_up_interruptible(&tty->write_wait);
1162	}
1163
1164	/* if transmitter idle and loopmode_send_done_requested
1165	 * then start echoing RxD to TxD
1166	 */
1167	spin_lock_irqsave(&info->irq_spinlock,flags);
1168 	if ( !info->tx_active && info->loopmode_send_done_requested )
1169 		usc_loopmode_send_done( info );
1170	spin_unlock_irqrestore(&info->irq_spinlock,flags);
1171}
1172
1173static void mgsl_bh_status(struct mgsl_struct *info)
1174{
1175	if ( debug_level >= DEBUG_LEVEL_BH )
1176		printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1177			__FILE__,__LINE__,info->device_name);
1178
1179	info->ri_chkcount = 0;
1180	info->dsr_chkcount = 0;
1181	info->dcd_chkcount = 0;
1182	info->cts_chkcount = 0;
1183}
1184
1185/* mgsl_isr_receive_status()
1186 * 
1187 *	Service a receive status interrupt. The type of status
1188 *	interrupt is indicated by the state of the RCSR.
1189 *	This is only used for HDLC mode.
1190 *
1191 * Arguments:		info	pointer to device instance data
1192 * Return Value:	None
1193 */
1194static void mgsl_isr_receive_status( struct mgsl_struct *info )
1195{
1196	u16 status = usc_InReg( info, RCSR );
1197
1198	if ( debug_level >= DEBUG_LEVEL_ISR )	
1199		printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1200			__FILE__,__LINE__,status);
1201			
1202 	if ( (status & RXSTATUS_ABORT_RECEIVED) && 
1203		info->loopmode_insert_requested &&
1204 		usc_loopmode_active(info) )
1205 	{
1206		++info->icount.rxabort;
1207	 	info->loopmode_insert_requested = FALSE;
1208 
1209 		/* clear CMR:13 to start echoing RxD to TxD */
1210		info->cmr_value &= ~BIT13;
1211 		usc_OutReg(info, CMR, info->cmr_value);
1212 
1213		/* disable received abort irq (no longer required) */
1214	 	usc_OutReg(info, RICR,
1215 			(usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
1216 	}
1217
1218	if (status & (RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED)) {
1219		if (status & RXSTATUS_EXITED_HUNT)
1220			info->icount.exithunt++;
1221		if (status & RXSTATUS_IDLE_RECEIVED)
1222			info->icount.rxidle++;
1223		wake_up_interruptible(&info->event_wait_q);
1224	}
1225
1226	if (status & RXSTATUS_OVERRUN){
1227		info->icount.rxover++;
1228		usc_process_rxoverrun_sync( info );
1229	}
1230
1231	usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
1232	usc_UnlatchRxstatusBits( info, status );
1233
1234}	/* end of mgsl_isr_receive_status() */
1235
1236/* mgsl_isr_transmit_status()
1237 * 
1238 * 	Service a transmit status interrupt
1239 *	HDLC mode :end of transmit frame
1240 *	Async mode:all data is sent
1241 * 	transmit status is indicated by bits in the TCSR.
1242 * 
1243 * Arguments:		info	       pointer to device instance data
1244 * Return Value:	None
1245 */
1246static void mgsl_isr_transmit_status( struct mgsl_struct *info )
1247{
1248	u16 status = usc_InReg( info, TCSR );
1249
1250	if ( debug_level >= DEBUG_LEVEL_ISR )	
1251		printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1252			__FILE__,__LINE__,status);
1253	
1254	usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
1255	usc_UnlatchTxstatusBits( info, status );
1256	
1257	if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
1258	{
1259		/* finished sending HDLC abort. This may leave	*/
1260		/* the TxFifo with data from the aborted frame	*/
1261		/* so purge the TxFifo. Also shutdown the DMA	*/
1262		/* channel in case there is data remaining in 	*/
1263		/* the DMA buffer				*/
1264 		usc_DmaCmd( info, DmaCmd_ResetTxChannel );
1265 		usc_RTCmd( info, RTCmd_PurgeTxFifo );
1266	}
1267 
1268	if ( status & TXSTATUS_EOF_SENT )
1269		info->icount.txok++;
1270	else if ( status & TXSTATUS_UNDERRUN )
1271		info->icount.txunder++;
1272	else if ( status & TXSTATUS_ABORT_SENT )
1273		info->icount.txabort++;
1274	else
1275		info->icount.txunder++;
1276			
1277	info->tx_active = 0;
1278	info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1279	del_timer(&info->tx_timer);	
1280	
1281	if ( info->drop_rts_on_tx_done ) {
1282		usc_get_serial_signals( info );
1283		if ( info->serial_signals & SerialSignal_RTS ) {
1284			info->serial_signals &= ~SerialSignal_RTS;
1285			usc_set_serial_signals( info );
1286		}
1287		info->drop_rts_on_tx_done = 0;
1288	}
1289
1290#ifdef CONFIG_HDLC
1291	if (info->netcount)
1292		hdlcdev_tx_done(info);
1293	else 
1294#endif
1295	{
1296		if (info->tty->stopped || info->tty->hw_stopped) {
1297			usc_stop_transmitter(info);
1298			return;
1299		}
1300		info->pending_bh |= BH_TRANSMIT;
1301	}
1302
1303}	/* end of mgsl_isr_transmit_status() */
1304
1305/* mgsl_isr_io_pin()
1306 * 
1307 * 	Service an Input/Output pin interrupt. The type of
1308 * 	interrupt is indicated by bits in the MISR
1309 * 	
1310 * Arguments:		info	       pointer to device instance data
1311 * Return Value:	None
1312 */
1313static void mgsl_isr_io_pin( struct mgsl_struct *info )
1314{
1315 	struct	mgsl_icount *icount;
1316	u16 status = usc_InReg( info, MISR );
1317
1318	if ( debug_level >= DEBUG_LEVEL_ISR )	
1319		printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1320			__FILE__,__LINE__,status);
1321			
1322	usc_ClearIrqPendingBits( info, IO_PIN );
1323	usc_UnlatchIostatusBits( info, status );
1324
1325	if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
1326	              MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
1327		icount = &info->icount;
1328		/* update input line counters */
1329		if (status & MISCSTATUS_RI_LATCHED) {
1330			if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1331				usc_DisablestatusIrqs(info,SICR_RI);
1332			icount->rng++;
1333			if ( status & MISCSTATUS_RI )
1334				info->input_signal_events.ri_up++;	
1335			else
1336				info->input_signal_events.ri_down++;	
1337		}
1338		if (status & MISCSTATUS_DSR_LATCHED) {
1339			if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1340				usc_DisablestatusIrqs(info,SICR_DSR);
1341			icount->dsr++;
1342			if ( status & MISCSTATUS_DSR )
1343				info->input_signal_events.dsr_up++;
1344			else
1345				info->input_signal_events.dsr_down++;
1346		}
1347		if (status & MISCSTATUS_DCD_LATCHED) {
1348			if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1349				usc_DisablestatusIrqs(info,SICR_DCD);
1350			icount->dcd++;
1351			if (status & MISCSTATUS_DCD) {
1352				info->input_signal_events.dcd_up++;
1353			} else
1354				info->input_signal_events.dcd_down++;
1355#ifdef CONFIG_HDLC
1356			if (info->netcount)
1357				hdlc_set_carrier(status & MISCSTATUS_DCD, info->netdev);
1358#endif
1359		}
1360		if (status & MISCSTATUS_CTS_LATCHED)
1361		{
1362			if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1363				usc_DisablestatusIrqs(info,SICR_CTS);
1364			icount->cts++;
1365			if ( status & MISCSTATUS_CTS )
1366				info->input_signal_events.cts_up++;
1367			else
1368				info->input_signal_events.cts_down++;
1369		}
1370		wake_up_interruptible(&info->status_event_wait_q);
1371		wake_up_interruptible(&info->event_wait_q);
1372
1373		if ( (info->flags & ASYNC_CHECK_CD) && 
1374		     (status & MISCSTATUS_DCD_LATCHED) ) {
1375			if ( debug_level >= DEBUG_LEVEL_ISR )
1376				printk("%s CD now %s...", info->device_name,
1377				       (status & MISCSTATUS_DCD) ? "on" : "off");
1378			if (status & MISCSTATUS_DCD)
1379				wake_up_interruptible(&info->open_wait);
1380			else {
1381				if ( debug_level >= DEBUG_LEVEL_ISR )
1382					printk("doing serial hangup...");
1383				if (info->tty)
1384					tty_hangup(info->tty);
1385			}
1386		}
1387	
1388		if ( (info->flags & ASYNC_CTS_FLOW) && 
1389		     (status & MISCSTATUS_CTS_LATCHED) ) {
1390			if (info->tty->hw_stopped) {
1391				if (status & MISCSTATUS_CTS) {
1392					if ( debug_level >= DEBUG_LEVEL_ISR )
1393						printk("CTS tx start...");
1394					if (info->tty)
1395						info->tty->hw_stopped = 0;
1396					usc_start_transmitter(info);
1397					info->pending_bh |= BH_TRANSMIT;
1398					return;
1399				}
1400			} else {
1401				if (!(status & MISCSTATUS_CTS)) {
1402					if ( debug_level >= DEBUG_LEVEL_ISR )
1403						printk("CTS tx stop...");
1404					if (info->tty)
1405						info->tty->hw_stopped = 1;
1406					usc_stop_transmitter(info);
1407				}
1408			}
1409		}
1410	}
1411
1412	info->pending_bh |= BH_STATUS;
1413	
1414	/* for diagnostics set IRQ flag */
1415	if ( status & MISCSTATUS_TXC_LATCHED ){
1416		usc_OutReg( info, SICR,
1417			(unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
1418		usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
1419		info->irq_occurred = 1;
1420	}
1421
1422}	/* end of mgsl_isr_io_pin() */
1423
1424/* mgsl_isr_transmit_data()
1425 * 
1426 * 	Service a transmit data interrupt (async mode only).
1427 * 
1428 * Arguments:		info	pointer to device instance data
1429 * Return Value:	None
1430 */
1431static void mgsl_isr_transmit_data( struct mgsl_struct *info )
1432{
1433	if ( debug_level >= DEBUG_LEVEL_ISR )	
1434		printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1435			__FILE__,__LINE__,info->xmit_cnt);
1436			
1437	usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
1438	
1439	if (info->tty->stopped || info->tty->hw_stopped) {
1440		usc_stop_transmitter(info);
1441		return;
1442	}
1443	
1444	if ( info->xmit_cnt )
1445		usc_load_txfifo( info );
1446	else
1447		info->tx_active = 0;
1448		
1449	if (info->xmit_cnt < WAKEUP_CHARS)
1450		info->pending_bh |= BH_TRANSMIT;
1451
1452}	/* end of mgsl_isr_transmit_data() */
1453
1454/* mgsl_isr_receive_data()
1455 * 
1456 * 	Service a receive data interrupt. This occurs
1457 * 	when operating in asynchronous interrupt transfer mode.
1458 *	The receive data FIFO is flushed to the receive data buffers. 
1459 * 
1460 * Arguments:		info		pointer to device instance data
1461 * Return Value:	None
1462 */
1463static void mgsl_isr_receive_data( struct mgsl_struct *info )
1464{
1465	int Fifocount;
1466	u16 status;
1467	unsigned char DataByte;
1468 	struct tty_struct *tty = info->tty;
1469 	struct	mgsl_icount *icount = &info->icount;
1470	
1471	if ( debug_level >= DEBUG_LEVEL_ISR )	
1472		printk("%s(%d):mgsl_isr_receive_data\n",
1473			__FILE__,__LINE__);
1474
1475	usc_ClearIrqPendingBits( info, RECEIVE_DATA );
1476	
1477	/* select FIFO status for RICR readback */
1478	usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
1479
1480	/* clear the Wordstatus bit so that status readback */
1481	/* only reflects the status of this byte */
1482	usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
1483
1484	/* flush the receive FIFO */
1485
1486	while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
1487		/* read one byte from RxFIFO */
1488		outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
1489		      info->io_base + CCAR );
1490		DataByte = inb( info->io_base + CCAR );
1491
1492		/* get the status of the received byte */
1493		status = usc_InReg(info, RCSR);
1494		if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1495				RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) )
1496			usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
1497		
1498		if (tty->flip.count >= TTY_FLIPBUF_SIZE)
1499			continue;
1500			
1501		*tty->flip.char_buf_ptr = DataByte;
1502		icount->rx++;
1503		
1504		*tty->flip.flag_buf_ptr = 0;
1505		if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1506				RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) ) {
1507			printk("rxerr=%04X\n",status);					
1508			/* update error statistics */
1509			if ( status & RXSTATUS_BREAK_RECEIVED ) {
1510				status &= ~(RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR);
1511				icount->brk++;
1512			} else if (status & RXSTATUS_PARITY_ERROR) 
1513				icount->parity++;
1514			else if (status & RXSTATUS_FRAMING_ERROR)
1515				icount->frame++;
1516			else if (status & RXSTATUS_OVERRUN) {
1517				/* must issue purge fifo cmd before */
1518				/* 16C32 accepts more receive chars */
1519				usc_RTCmd(info,RTCmd_PurgeRxFifo);
1520				icount->overrun++;
1521			}
1522
1523			/* discard char if tty control flags say so */					
1524			if (status & info->ignore_status_mask)
1525				continue;
1526				
1527			status &= info->read_status_mask;
1528		
1529			if (status & RXSTATUS_BREAK_RECEIVED) {
1530				*tty->flip.flag_buf_ptr = TTY_BREAK;
1531				if (info->flags & ASYNC_SAK)
1532					do_SAK(tty);
1533			} else if (status & RXSTATUS_PARITY_ERROR)
1534				*tty->flip.flag_buf_ptr = TTY_PARITY;
1535			else if (status & RXSTATUS_FRAMING_ERROR)
1536				*tty->flip.flag_buf_ptr = TTY_FRAME;
1537			if (status & RXSTATUS_OVERRUN) {
1538				/* Overrun is special, since it's
1539				 * reported immediately, and doesn't
1540				 * affect the current character
1541				 */
1542				if (tty->flip.count < TTY_FLIPBUF_SIZE) {
1543					tty->flip.count++;
1544					tty->flip.flag_buf_ptr++;
1545					tty->flip.char_buf_ptr++;
1546					*tty->flip.flag_buf_ptr = TTY_OVERRUN;
1547				}
1548			}
1549		}	/* end of if (error) */
1550		
1551		tty->flip.flag_buf_ptr++;
1552		tty->flip.char_buf_ptr++;
1553		tty->flip.count++;
1554	}
1555
1556	if ( debug_level >= DEBUG_LEVEL_ISR ) {
1557		printk("%s(%d):mgsl_isr_receive_data flip count=%d\n",
1558			__FILE__,__LINE__,tty->flip.count);
1559		printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1560			__FILE__,__LINE__,icount->rx,icount->brk,
1561			icount->parity,icount->frame,icount->overrun);
1562	}
1563			
1564	if ( tty->flip.count )
1565		tty_flip_buffer_push(tty);
1566}
1567
1568/* mgsl_isr_misc()
1569 * 
1570 * 	Service a miscellaneos interrupt source.
1571 * 	
1572 * Arguments:		info		pointer to device extension (instance data)
1573 * Return Value:	None
1574 */
1575static void mgsl_isr_misc( struct mgsl_struct *info )
1576{
1577	u16 status = usc_InReg( info, MISR );
1578
1579	if ( debug_level >= DEBUG_LEVEL_ISR )	
1580		printk("%s(%d):mgsl_isr_misc status=%04X\n",
1581			__FILE__,__LINE__,status);
1582			
1583	if ((status & MISCSTATUS_RCC_UNDERRUN) &&
1584	    (info->params.mode == MGSL_MODE_HDLC)) {
1585
1586		/* turn off receiver and rx DMA */
1587		usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
1588		usc_DmaCmd(info, DmaCmd_ResetRxChannel);
1589		usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
1590		usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
1591		usc_DisableInterrupts(info, RECEIVE_DATA + RECEIVE_STATUS);
1592
1593		/* schedule BH handler to restart receiver */
1594		info->pending_bh |= BH_RECEIVE;
1595		info->rx_rcc_underrun = 1;
1596	}
1597
1598	usc_ClearIrqPendingBits( info, MISC );
1599	usc_UnlatchMiscstatusBits( info, status );
1600
1601}	/* end of mgsl_isr_misc() */
1602
1603/* mgsl_isr_null()
1604 *
1605 * 	Services undefined interrupt vectors from the
1606 * 	USC. (hence this function SHOULD never be called)
1607 * 
1608 * Arguments:		info		pointer to device extension (instance data)
1609 * Return Value:	None
1610 */
1611static void mgsl_isr_null( struct mgsl_struct *info )
1612{
1613
1614}	/* end of mgsl_isr_null() */
1615
1616/* mgsl_isr_receive_dma()
1617 * 
1618 * 	Service a rec…

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