/drivers/char/ipmi/ipmi_smic_sm.c

https://bitbucket.org/evzijst/gittest · C · 599 lines · 455 code · 54 blank · 90 comment · 70 complexity · 7b9054923c2c507b8b867d6a60ef0cb3 MD5 · raw file 

    

  1. /*
    2. 

  2.  * ipmi_smic_sm.c
    3. 

  3.  *
    4. 

  4.  * The state-machine driver for an IPMI SMIC driver
    5. 

  5.  *
    6. 

  6.  * It started as a copy of Corey Minyard's driver for the KSC interface
    7. 

  7.  * and the kernel patch "mmcdev-patch-245" by HP
    8. 

  8.  *
    9. 

  9.  * modified by:	Hannes Schulz <schulz@schwaar.com>
    10. 

  10.  *		ipmi@schwaar.com
    11. 

  11.  *
    12. 

  12.  *
    13. 

  13.  * Corey Minyard's driver for the KSC interface has the following
    14. 

  14.  * copyright notice:
    15. 

  15.  *   Copyright 2002 MontaVista Software Inc.
    16. 

  16.  *
    17. 

  17.  * the kernel patch "mmcdev-patch-245" by HP has the following
    18. 

  18.  * copyright notice:
    19. 

  19.  * (c) Copyright 2001 Grant Grundler (c) Copyright
    20. 

  20.  * 2001 Hewlett-Packard Company
    21. 

  21.  *
    22. 

  22.  *
    23. 

  23.  *  This program is free software; you can redistribute it and/or modify it
    24. 

  24.  *  under the terms of the GNU General Public License as published by the
    25. 

  25.  *  Free Software Foundation; either version 2 of the License, or (at your
    26. 

  26.  *  option) any later version.
    27. 

  27.  *
    28. 

  28.  *
    29. 

  29.  *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
    30. 

  30.  *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
    31. 

  31.  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
    32. 

  32.  *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
    33. 

  33.  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
    34. 

  34.  *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
    35. 

  35.  *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
    36. 

  36.  *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
    37. 

  37.  *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
    38. 

  38.  *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    39. 

  39.  *
    40. 

  40.  *  You should have received a copy of the GNU General Public License along
    41. 

  41.  *  with this program; if not, write to the Free Software Foundation, Inc.,
    42. 

  42.  *  675 Mass Ave, Cambridge, MA 02139, USA.  */
    43. 

  43. 

  44. #include <linux/kernel.h> /* For printk. */
    45. 

  45. #include <linux/string.h>
    46. 

  46. #include <linux/ipmi_msgdefs.h>		/* for completion codes */
    47. 

  47. #include "ipmi_si_sm.h"
    48. 

  48. 

  49. #define IPMI_SMIC_VERSION "v33"
    50. 

  50. 

  51. /* smic_debug is a bit-field
    52. 

  52.  *	SMIC_DEBUG_ENABLE -	turned on for now
    53. 

  53.  *	SMIC_DEBUG_MSG -	commands and their responses
    54. 

  54.  *	SMIC_DEBUG_STATES -	state machine
    55. 

  55. */
    56. 

  56. #define SMIC_DEBUG_STATES	4
    57. 

  57. #define SMIC_DEBUG_MSG		2
    58. 

  58. #define	SMIC_DEBUG_ENABLE	1
    59. 

  59. 

  60. static int smic_debug = 1;
    61. 

  61. 

  62. enum smic_states {
    63. 

  63. 	SMIC_IDLE,
    64. 

  64. 	SMIC_START_OP,
    65. 

  65. 	SMIC_OP_OK,
    66. 

  66. 	SMIC_WRITE_START,
    67. 

  67. 	SMIC_WRITE_NEXT,
    68. 

  68. 	SMIC_WRITE_END,
    69. 

  69. 	SMIC_WRITE2READ,
    70. 

  70. 	SMIC_READ_START,
    71. 

  71. 	SMIC_READ_NEXT,
    72. 

  72. 	SMIC_READ_END,
    73. 

  73. 	SMIC_HOSED
    74. 

  74. };
    75. 

  75. 

  76. #define MAX_SMIC_READ_SIZE 80
    77. 

  77. #define MAX_SMIC_WRITE_SIZE 80
    78. 

  78. #define SMIC_MAX_ERROR_RETRIES 3
    79. 

  79. 

  80. /* Timeouts in microseconds. */
    81. 

  81. #define SMIC_RETRY_TIMEOUT 100000
    82. 

  82. 

  83. /* SMIC Flags Register Bits */
    84. 

  84. #define SMIC_RX_DATA_READY	0x80
    85. 

  85. #define SMIC_TX_DATA_READY	0x40
    86. 

  86. #define SMIC_SMI		0x10
    87. 

  87. #define SMIC_EVM_DATA_AVAIL	0x08
    88. 

  88. #define SMIC_SMS_DATA_AVAIL	0x04
    89. 

  89. #define SMIC_FLAG_BSY		0x01
    90. 

  90. 

  91. /* SMIC Error Codes */
    92. 

  92. #define	EC_NO_ERROR		0x00
    93. 

  93. #define	EC_ABORTED		0x01
    94. 

  94. #define	EC_ILLEGAL_CONTROL	0x02
    95. 

  95. #define	EC_NO_RESPONSE		0x03
    96. 

  96. #define	EC_ILLEGAL_COMMAND	0x04
    97. 

  97. #define	EC_BUFFER_FULL		0x05
    98. 

  98. 

  99. struct si_sm_data
    100. 

  100. {
    101. 

  101. 	enum smic_states state;
    102. 

  102. 	struct si_sm_io *io;
    103. 

  103.         unsigned char	 write_data[MAX_SMIC_WRITE_SIZE];
    104. 

  104.         int		 write_pos;
    105. 

  105.         int		 write_count;
    106. 

  106.         int		 orig_write_count;
    107. 

  107.         unsigned char	 read_data[MAX_SMIC_READ_SIZE];
    108. 

  108.         int		 read_pos;
    109. 

  109.         int		 truncated;
    110. 

  110.         unsigned int	 error_retries;
    111. 

  111.         long		 smic_timeout;
    112. 

  112. };
    113. 

  113. 

  114. static unsigned int init_smic_data (struct si_sm_data *smic,
    115. 

  115. 				    struct si_sm_io *io)
    116. 

  116. {
    117. 

  117. 	smic->state = SMIC_IDLE;
    118. 

  118. 	smic->io = io;
    119. 

  119. 	smic->write_pos = 0;
    120. 

  120. 	smic->write_count = 0;
    121. 

  121. 	smic->orig_write_count = 0;
    122. 

  122. 	smic->read_pos = 0;
    123. 

  123. 	smic->error_retries = 0;
    124. 

  124. 	smic->truncated = 0;
    125. 

  125. 	smic->smic_timeout = SMIC_RETRY_TIMEOUT;
    126. 

  126. 

  127. 	/* We use 3 bytes of I/O. */
    128. 

  128. 	return 3;
    129. 

  129. }
    130. 

  130. 

  131. static int start_smic_transaction(struct si_sm_data *smic,
    132. 

  132. 				  unsigned char *data, unsigned int size)
    133. 

  133. {
    134. 

  134. 	unsigned int i;
    135. 

  135. 

  136. 	if ((size < 2) || (size > MAX_SMIC_WRITE_SIZE)) {
    137. 

  137. 		return -1;
    138. 

  138. 	}
    139. 

  139. 	if ((smic->state != SMIC_IDLE) && (smic->state != SMIC_HOSED)) {
    140. 

  140. 		return -2;
    141. 

  141. 	}
    142. 

  142. 	if (smic_debug & SMIC_DEBUG_MSG) {
    143. 

  143. 		printk(KERN_INFO "start_smic_transaction -");
    144. 

  144. 		for (i = 0; i < size; i ++) {
    145. 

  145. 			printk (" %02x", (unsigned char) (data [i]));
    146. 

  146. 		}
    147. 

  147. 		printk ("\n");
    148. 

  148. 	}
    149. 

  149. 	smic->error_retries = 0;
    150. 

  150. 	memcpy(smic->write_data, data, size);
    151. 

  151. 	smic->write_count = size;
    152. 

  152. 	smic->orig_write_count = size;
    153. 

  153. 	smic->write_pos = 0;
    154. 

  154. 	smic->read_pos = 0;
    155. 

  155. 	smic->state = SMIC_START_OP;
    156. 

  156. 	smic->smic_timeout = SMIC_RETRY_TIMEOUT;
    157. 

  157. 	return 0;
    158. 

  158. }
    159. 

  159. 

  160. static int smic_get_result(struct si_sm_data *smic,
    161. 

  161. 			   unsigned char *data, unsigned int length)
    162. 

  162. {
    163. 

  163. 	int i;
    164. 

  164. 

  165. 	if (smic_debug & SMIC_DEBUG_MSG) {
    166. 

  166. 		printk (KERN_INFO "smic_get result -");
    167. 

  167. 		for (i = 0; i < smic->read_pos; i ++) {
    168. 

  168. 			printk (" %02x", (smic->read_data [i]));
    169. 

  169. 		}
    170. 

  170. 		printk ("\n");
    171. 

  171. 	}
    172. 

  172. 	if (length < smic->read_pos) {
    173. 

  173. 		smic->read_pos = length;
    174. 

  174. 		smic->truncated = 1;
    175. 

  175. 	}
    176. 

  176. 	memcpy(data, smic->read_data, smic->read_pos);
    177. 

  177. 

  178. 	if ((length >= 3) && (smic->read_pos < 3)) {
    179. 

  179. 		data[2] = IPMI_ERR_UNSPECIFIED;
    180. 

  180. 		smic->read_pos = 3;
    181. 

  181. 	}
    182. 

  182. 	if (smic->truncated) {
    183. 

  183. 		data[2] = IPMI_ERR_MSG_TRUNCATED;
    184. 

  184. 		smic->truncated = 0;
    185. 

  185. 	}
    186. 

  186. 	return smic->read_pos;
    187. 

  187. }
    188. 

  188. 

  189. static inline unsigned char read_smic_flags(struct si_sm_data *smic)
    190. 

  190. {
    191. 

  191. 	return smic->io->inputb(smic->io, 2);
    192. 

  192. }
    193. 

  193. 

  194. static inline unsigned char read_smic_status(struct si_sm_data *smic)
    195. 

  195. {
    196. 

  196. 	return smic->io->inputb(smic->io, 1);
    197. 

  197. }
    198. 

  198. 

  199. static inline unsigned char read_smic_data(struct si_sm_data *smic)
    200. 

  200. {
    201. 

  201. 	return smic->io->inputb(smic->io, 0);
    202. 

  202. }
    203. 

  203. 

  204. static inline void write_smic_flags(struct si_sm_data *smic,
    205. 

  205. 				    unsigned char   flags)
    206. 

  206. {
    207. 

  207. 	smic->io->outputb(smic->io, 2, flags);
    208. 

  208. }
    209. 

  209. 

  210. static inline void write_smic_control(struct si_sm_data *smic,
    211. 

  211. 				      unsigned char   control)
    212. 

  212. {
    213. 

  213. 	smic->io->outputb(smic->io, 1, control);
    214. 

  214. }
    215. 

  215. 

  216. static inline void write_si_sm_data (struct si_sm_data *smic,
    217. 

  217. 				   unsigned char   data)
    218. 

  218. {
    219. 

  219. 	smic->io->outputb(smic->io, 0, data);
    220. 

  220. }
    221. 

  221. 

  222. static inline void start_error_recovery(struct si_sm_data *smic, char *reason)
    223. 

  223. {
    224. 

  224. 	(smic->error_retries)++;
    225. 

  225. 	if (smic->error_retries > SMIC_MAX_ERROR_RETRIES) {
    226. 

  226. 		if (smic_debug & SMIC_DEBUG_ENABLE) {
    227. 

  227. 			printk(KERN_WARNING
    228. 

  228. 			       "ipmi_smic_drv: smic hosed: %s\n", reason);
    229. 

  229. 		}
    230. 

  230. 		smic->state = SMIC_HOSED;
    231. 

  231. 	} else {
    232. 

  232. 		smic->write_count = smic->orig_write_count;
    233. 

  233. 		smic->write_pos = 0;
    234. 

  234. 		smic->read_pos = 0;
    235. 

  235. 		smic->state = SMIC_START_OP;
    236. 

  236. 		smic->smic_timeout = SMIC_RETRY_TIMEOUT;
    237. 

  237. 	}
    238. 

  238. }
    239. 

  239. 

  240. static inline void write_next_byte(struct si_sm_data *smic)
    241. 

  241. {
    242. 

  242. 	write_si_sm_data(smic, smic->write_data[smic->write_pos]);
    243. 

  243. 	(smic->write_pos)++;
    244. 

  244. 	(smic->write_count)--;
    245. 

  245. }
    246. 

  246. 

  247. static inline void read_next_byte (struct si_sm_data *smic)
    248. 

  248. {
    249. 

  249. 	if (smic->read_pos >= MAX_SMIC_READ_SIZE) {
    250. 

  250. 		read_smic_data (smic);
    251. 

  251. 		smic->truncated = 1;
    252. 

  252. 	} else {
    253. 

  253. 		smic->read_data[smic->read_pos] = read_smic_data(smic);
    254. 

  254. 		(smic->read_pos)++;
    255. 

  255. 	}
    256. 

  256. }
    257. 

  257. 

  258. /*  SMIC Control/Status Code Components */
    259. 

  259. #define	SMIC_GET_STATUS		0x00	/* Control form's name */
    260. 

  260. #define	SMIC_READY		0x00	/* Status  form's name */
    261. 

  261. #define	SMIC_WR_START		0x01	/* Unified Control/Status names... */
    262. 

  262. #define	SMIC_WR_NEXT		0x02
    263. 

  263. #define	SMIC_WR_END		0x03
    264. 

  264. #define	SMIC_RD_START		0x04
    265. 

  265. #define	SMIC_RD_NEXT		0x05
    266. 

  266. #define	SMIC_RD_END		0x06
    267. 

  267. #define	SMIC_CODE_MASK		0x0f
    268. 

  268. 

  269. #define	SMIC_CONTROL		0x00
    270. 

  270. #define	SMIC_STATUS		0x80
    271. 

  271. #define	SMIC_CS_MASK		0x80
    272. 

  272. 

  273. #define	SMIC_SMS		0x40
    274. 

  274. #define	SMIC_SMM		0x60
    275. 

  275. #define	SMIC_STREAM_MASK	0x60
    276. 

  276. 

  277. /*  SMIC Control Codes */
    278. 

  278. #define	SMIC_CC_SMS_GET_STATUS	(SMIC_CONTROL|SMIC_SMS|SMIC_GET_STATUS)
    279. 

  279. #define	SMIC_CC_SMS_WR_START	(SMIC_CONTROL|SMIC_SMS|SMIC_WR_START)
    280. 

  280. #define	SMIC_CC_SMS_WR_NEXT	(SMIC_CONTROL|SMIC_SMS|SMIC_WR_NEXT)
    281. 

  281. #define	SMIC_CC_SMS_WR_END	(SMIC_CONTROL|SMIC_SMS|SMIC_WR_END)
    282. 

  282. #define	SMIC_CC_SMS_RD_START	(SMIC_CONTROL|SMIC_SMS|SMIC_RD_START)
    283. 

  283. #define	SMIC_CC_SMS_RD_NEXT	(SMIC_CONTROL|SMIC_SMS|SMIC_RD_NEXT)
    284. 

  284. #define	SMIC_CC_SMS_RD_END	(SMIC_CONTROL|SMIC_SMS|SMIC_RD_END)
    285. 

  285. 

  286. #define	SMIC_CC_SMM_GET_STATUS	(SMIC_CONTROL|SMIC_SMM|SMIC_GET_STATUS)
    287. 

  287. #define	SMIC_CC_SMM_WR_START	(SMIC_CONTROL|SMIC_SMM|SMIC_WR_START)
    288. 

  288. #define	SMIC_CC_SMM_WR_NEXT	(SMIC_CONTROL|SMIC_SMM|SMIC_WR_NEXT)
    289. 

  289. #define	SMIC_CC_SMM_WR_END	(SMIC_CONTROL|SMIC_SMM|SMIC_WR_END)
    290. 

  290. #define	SMIC_CC_SMM_RD_START	(SMIC_CONTROL|SMIC_SMM|SMIC_RD_START)
    291. 

  291. #define	SMIC_CC_SMM_RD_NEXT	(SMIC_CONTROL|SMIC_SMM|SMIC_RD_NEXT)
    292. 

  292. #define	SMIC_CC_SMM_RD_END	(SMIC_CONTROL|SMIC_SMM|SMIC_RD_END)
    293. 

  293. 

  294. /*  SMIC Status Codes */
    295. 

  295. #define	SMIC_SC_SMS_READY	(SMIC_STATUS|SMIC_SMS|SMIC_READY)
    296. 

  296. #define	SMIC_SC_SMS_WR_START	(SMIC_STATUS|SMIC_SMS|SMIC_WR_START)
    297. 

  297. #define	SMIC_SC_SMS_WR_NEXT	(SMIC_STATUS|SMIC_SMS|SMIC_WR_NEXT)
    298. 

  298. #define	SMIC_SC_SMS_WR_END	(SMIC_STATUS|SMIC_SMS|SMIC_WR_END)
    299. 

  299. #define	SMIC_SC_SMS_RD_START	(SMIC_STATUS|SMIC_SMS|SMIC_RD_START)
    300. 

  300. #define	SMIC_SC_SMS_RD_NEXT	(SMIC_STATUS|SMIC_SMS|SMIC_RD_NEXT)
    301. 

  301. #define	SMIC_SC_SMS_RD_END	(SMIC_STATUS|SMIC_SMS|SMIC_RD_END)
    302. 

  302. 

  303. #define	SMIC_SC_SMM_READY	(SMIC_STATUS|SMIC_SMM|SMIC_READY)
    304. 

  304. #define	SMIC_SC_SMM_WR_START	(SMIC_STATUS|SMIC_SMM|SMIC_WR_START)
    305. 

  305. #define	SMIC_SC_SMM_WR_NEXT	(SMIC_STATUS|SMIC_SMM|SMIC_WR_NEXT)
    306. 

  306. #define	SMIC_SC_SMM_WR_END	(SMIC_STATUS|SMIC_SMM|SMIC_WR_END)
    307. 

  307. #define	SMIC_SC_SMM_RD_START	(SMIC_STATUS|SMIC_SMM|SMIC_RD_START)
    308. 

  308. #define	SMIC_SC_SMM_RD_NEXT	(SMIC_STATUS|SMIC_SMM|SMIC_RD_NEXT)
    309. 

  309. #define	SMIC_SC_SMM_RD_END	(SMIC_STATUS|SMIC_SMM|SMIC_RD_END)
    310. 

  310. 

  311. /* these are the control/status codes we actually use
    312. 

  312. 	SMIC_CC_SMS_GET_STATUS	0x40
    313. 

  313. 	SMIC_CC_SMS_WR_START	0x41
    314. 

  314. 	SMIC_CC_SMS_WR_NEXT	0x42
    315. 

  315. 	SMIC_CC_SMS_WR_END	0x43
    316. 

  316. 	SMIC_CC_SMS_RD_START	0x44
    317. 

  317. 	SMIC_CC_SMS_RD_NEXT	0x45
    318. 

  318. 	SMIC_CC_SMS_RD_END	0x46
    319. 

    320. 

  320. 	SMIC_SC_SMS_READY	0xC0
    321. 

  321. 	SMIC_SC_SMS_WR_START	0xC1
    322. 

  322. 	SMIC_SC_SMS_WR_NEXT	0xC2
    323. 

  323. 	SMIC_SC_SMS_WR_END	0xC3
    324. 

  324. 	SMIC_SC_SMS_RD_START	0xC4
    325. 

  325. 	SMIC_SC_SMS_RD_NEXT	0xC5
    326. 

  326. 	SMIC_SC_SMS_RD_END	0xC6
    327. 

  327. */
    328. 

  328. 

  329. static enum si_sm_result smic_event (struct si_sm_data *smic, long time)
    330. 

  330. {
    331. 

  331. 	unsigned char status;
    332. 

  332. 	unsigned char flags;
    333. 

  333. 	unsigned char data;
    334. 

  334. 

  335. 	if (smic->state == SMIC_HOSED) {
    336. 

  336. 		init_smic_data(smic, smic->io);
    337. 

  337. 		return SI_SM_HOSED;
    338. 

  338. 	}
    339. 

  339. 	if (smic->state != SMIC_IDLE) {
    340. 

  340. 		if (smic_debug & SMIC_DEBUG_STATES) {
    341. 

  341. 			printk(KERN_INFO
    342. 

  342. 			       "smic_event - smic->smic_timeout = %ld,"
    343. 

  343. 			       " time = %ld\n",
    344. 

  344. 			       smic->smic_timeout, time);
    345. 

  345. 		}
    346. 

  346. /* FIXME: smic_event is sometimes called with time > SMIC_RETRY_TIMEOUT */
    347. 

  347. 		if (time < SMIC_RETRY_TIMEOUT) {
    348. 

  348. 			smic->smic_timeout -= time;
    349. 

  349. 			if (smic->smic_timeout < 0) {
    350. 

  350. 				start_error_recovery(smic, "smic timed out.");
    351. 

  351. 				return SI_SM_CALL_WITH_DELAY;
    352. 

  352. 			}
    353. 

  353. 		}
    354. 

  354. 	}
    355. 

  355. 	flags = read_smic_flags(smic);
    356. 

  356. 	if (flags & SMIC_FLAG_BSY)
    357. 

  357. 		return SI_SM_CALL_WITH_DELAY;
    358. 

  358. 

  359. 	status = read_smic_status (smic);
    360. 

  360. 	if (smic_debug & SMIC_DEBUG_STATES)
    361. 

  361. 		printk(KERN_INFO
    362. 

  362. 		       "smic_event - state = %d, flags = 0x%02x,"
    363. 

  363. 		       " status = 0x%02x\n",
    364. 

  364. 		       smic->state, flags, status);
    365. 

  365. 

  366. 	switch (smic->state) {
    367. 

  367. 	case SMIC_IDLE:
    368. 

  368. 		/* in IDLE we check for available messages */
    369. 

  369. 		if (flags & (SMIC_SMI |
    370. 

  370. 			     SMIC_EVM_DATA_AVAIL | SMIC_SMS_DATA_AVAIL))
    371. 

  371. 		{
    372. 

  372. 			return SI_SM_ATTN;
    373. 

  373. 		}
    374. 

  374. 		return SI_SM_IDLE;
    375. 

  375. 

  376. 	case SMIC_START_OP:
    377. 

  377. 		/* sanity check whether smic is really idle */
    378. 

  378. 		write_smic_control(smic, SMIC_CC_SMS_GET_STATUS);
    379. 

  379. 		write_smic_flags(smic, flags | SMIC_FLAG_BSY);
    380. 

  380. 		smic->state = SMIC_OP_OK;
    381. 

  381. 		break;
    382. 

  382. 

  383. 	case SMIC_OP_OK:
    384. 

  384. 		if (status != SMIC_SC_SMS_READY) {
    385. 

  385. 				/* this should not happen */
    386. 

  386. 			start_error_recovery(smic,
    387. 

  387. 					     "state = SMIC_OP_OK,"
    388. 

  388. 					     " status != SMIC_SC_SMS_READY");
    389. 

  389. 			return SI_SM_CALL_WITH_DELAY;
    390. 

  390. 		}
    391. 

  391. 		/* OK so far; smic is idle let us start ... */
    392. 

  392. 		write_smic_control(smic, SMIC_CC_SMS_WR_START);
    393. 

  393. 		write_next_byte(smic);
    394. 

  394. 		write_smic_flags(smic, flags | SMIC_FLAG_BSY);
    395. 

  395. 		smic->state = SMIC_WRITE_START;
    396. 

  396. 		break;
    397. 

  397. 

  398. 	case SMIC_WRITE_START:
    399. 

  399. 		if (status != SMIC_SC_SMS_WR_START) {
    400. 

  400. 			start_error_recovery(smic,
    401. 

  401. 					     "state = SMIC_WRITE_START, "
    402. 

  402. 					     "status != SMIC_SC_SMS_WR_START");
    403. 

  403. 			return SI_SM_CALL_WITH_DELAY;
    404. 

  404. 		}
    405. 

  405. 		/* we must not issue WR_(NEXT|END) unless
    406. 

  406.                    TX_DATA_READY is set */
    407. 

  407. 		if (flags & SMIC_TX_DATA_READY) {
    408. 

  408. 			if (smic->write_count == 1) {
    409. 

  409. 				/* last byte */
    410. 

  410. 				write_smic_control(smic, SMIC_CC_SMS_WR_END);
    411. 

  411. 				smic->state = SMIC_WRITE_END;
    412. 

  412. 			} else {
    413. 

  413. 				write_smic_control(smic, SMIC_CC_SMS_WR_NEXT);
    414. 

  414. 				smic->state = SMIC_WRITE_NEXT;
    415. 

  415. 			}
    416. 

  416. 			write_next_byte(smic);
    417. 

  417. 			write_smic_flags(smic, flags | SMIC_FLAG_BSY);
    418. 

  418. 		}
    419. 

  419. 		else {
    420. 

  420. 			return SI_SM_CALL_WITH_DELAY;
    421. 

  421. 		}
    422. 

  422. 		break;
    423. 

  423. 

  424. 	case SMIC_WRITE_NEXT:
    425. 

  425. 		if (status != SMIC_SC_SMS_WR_NEXT) {
    426. 

  426. 			start_error_recovery(smic,
    427. 

  427. 					     "state = SMIC_WRITE_NEXT, "
    428. 

  428. 					     "status != SMIC_SC_SMS_WR_NEXT");
    429. 

  429. 			return SI_SM_CALL_WITH_DELAY;
    430. 

  430. 		}
    431. 

  431. 		/* this is the same code as in SMIC_WRITE_START */
    432. 

  432. 		if (flags & SMIC_TX_DATA_READY) {
    433. 

  433. 			if (smic->write_count == 1) {
    434. 

  434. 				write_smic_control(smic, SMIC_CC_SMS_WR_END);
    435. 

  435. 				smic->state = SMIC_WRITE_END;
    436. 

  436. 			}
    437. 

  437. 			else {
    438. 

  438. 				write_smic_control(smic, SMIC_CC_SMS_WR_NEXT);
    439. 

  439. 				smic->state = SMIC_WRITE_NEXT;
    440. 

  440. 			}
    441. 

  441. 			write_next_byte(smic);
    442. 

  442. 			write_smic_flags(smic, flags | SMIC_FLAG_BSY);
    443. 

  443. 		}
    444. 

  444. 		else {
    445. 

  445. 			return SI_SM_CALL_WITH_DELAY;
    446. 

  446. 		}
    447. 

  447. 		break;
    448. 

  448. 

  449. 	case SMIC_WRITE_END:
    450. 

  450. 		if (status != SMIC_SC_SMS_WR_END) {
    451. 

  451. 			start_error_recovery (smic,
    452. 

  452. 					      "state = SMIC_WRITE_END, "
    453. 

  453. 					      "status != SMIC_SC_SMS_WR_END");
    454. 

  454. 			return SI_SM_CALL_WITH_DELAY;
    455. 

  455. 		}
    456. 

  456. 		/* data register holds an error code */
    457. 

  457. 		data = read_smic_data(smic);
    458. 

  458. 		if (data != 0) {
    459. 

  459. 			if (smic_debug & SMIC_DEBUG_ENABLE) {
    460. 

  460. 				printk(KERN_INFO
    461. 

  461. 				       "SMIC_WRITE_END: data = %02x\n", data);
    462. 

  462. 			}
    463. 

  463. 			start_error_recovery(smic,
    464. 

  464. 					     "state = SMIC_WRITE_END, "
    465. 

  465. 					     "data != SUCCESS");
    466. 

  466. 			return SI_SM_CALL_WITH_DELAY;
    467. 

  467. 		} else {
    468. 

  468. 			smic->state = SMIC_WRITE2READ;
    469. 

  469. 		}
    470. 

  470. 		break;
    471. 

  471. 

  472. 	case SMIC_WRITE2READ:
    473. 

  473. 		/* we must wait for RX_DATA_READY to be set before we
    474. 

  474.                    can continue */
    475. 

  475. 		if (flags & SMIC_RX_DATA_READY) {
    476. 

  476. 			write_smic_control(smic, SMIC_CC_SMS_RD_START);
    477. 

  477. 			write_smic_flags(smic, flags | SMIC_FLAG_BSY);
    478. 

  478. 			smic->state = SMIC_READ_START;
    479. 

  479. 		} else {
    480. 

  480. 			return SI_SM_CALL_WITH_DELAY;
    481. 

  481. 		}
    482. 

  482. 		break;
    483. 

  483. 

  484. 	case SMIC_READ_START:
    485. 

  485. 		if (status != SMIC_SC_SMS_RD_START) {
    486. 

  486. 			start_error_recovery(smic,
    487. 

  487. 					     "state = SMIC_READ_START, "
    488. 

  488. 					     "status != SMIC_SC_SMS_RD_START");
    489. 

  489. 			return SI_SM_CALL_WITH_DELAY;
    490. 

  490. 		}
    491. 

  491. 		if (flags & SMIC_RX_DATA_READY) {
    492. 

  492. 			read_next_byte(smic);
    493. 

  493. 			write_smic_control(smic, SMIC_CC_SMS_RD_NEXT);
    494. 

  494. 			write_smic_flags(smic, flags | SMIC_FLAG_BSY);
    495. 

  495. 			smic->state = SMIC_READ_NEXT;
    496. 

  496. 		} else {
    497. 

  497. 			return SI_SM_CALL_WITH_DELAY;
    498. 

  498. 		}
    499. 

  499. 		break;
    500. 

  500. 

  501. 	case SMIC_READ_NEXT:
    502. 

  502. 		switch (status) {
    503. 

  503. 		/* smic tells us that this is the last byte to be read
    504. 

  504.                    --> clean up */
    505. 

  505. 		case SMIC_SC_SMS_RD_END:
    506. 

  506. 			read_next_byte(smic);
    507. 

  507. 			write_smic_control(smic, SMIC_CC_SMS_RD_END);
    508. 

  508. 			write_smic_flags(smic, flags | SMIC_FLAG_BSY);
    509. 

  509. 			smic->state = SMIC_READ_END;
    510. 

  510. 			break;
    511. 

  511. 		case SMIC_SC_SMS_RD_NEXT:
    512. 

  512. 			if (flags & SMIC_RX_DATA_READY) {
    513. 

  513. 				read_next_byte(smic);
    514. 

  514. 				write_smic_control(smic, SMIC_CC_SMS_RD_NEXT);
    515. 

  515. 				write_smic_flags(smic, flags | SMIC_FLAG_BSY);
    516. 

  516. 				smic->state = SMIC_READ_NEXT;
    517. 

  517. 			} else {
    518. 

  518. 				return SI_SM_CALL_WITH_DELAY;
    519. 

  519. 			}
    520. 

  520. 			break;
    521. 

  521. 		default:
    522. 

  522. 			start_error_recovery(
    523. 

  523. 				smic,
    524. 

  524. 				"state = SMIC_READ_NEXT, "
    525. 

  525. 				"status != SMIC_SC_SMS_RD_(NEXT|END)");
    526. 

  526. 			return SI_SM_CALL_WITH_DELAY;
    527. 

  527. 		}
    528. 

  528. 		break;
    529. 

  529. 

  530. 	case SMIC_READ_END:
    531. 

  531. 		if (status != SMIC_SC_SMS_READY) {
    532. 

  532. 			start_error_recovery(smic,
    533. 

  533. 					     "state = SMIC_READ_END, "
    534. 

  534. 					     "status != SMIC_SC_SMS_READY");
    535. 

  535. 			return SI_SM_CALL_WITH_DELAY;
    536. 

  536. 		}
    537. 

  537. 		data = read_smic_data(smic);
    538. 

  538. 		/* data register holds an error code */
    539. 

  539. 		if (data != 0) {
    540. 

  540. 			if (smic_debug & SMIC_DEBUG_ENABLE) {
    541. 

  541. 				printk(KERN_INFO
    542. 

  542. 				       "SMIC_READ_END: data = %02x\n", data);
    543. 

  543. 			}
    544. 

  544. 			start_error_recovery(smic,
    545. 

  545. 					     "state = SMIC_READ_END, "
    546. 

  546. 					     "data != SUCCESS");
    547. 

  547. 			return SI_SM_CALL_WITH_DELAY;
    548. 

  548. 		} else {
    549. 

  549. 			smic->state = SMIC_IDLE;
    550. 

  550. 			return SI_SM_TRANSACTION_COMPLETE;
    551. 

  551. 		}
    552. 

  552. 

  553. 	case SMIC_HOSED:
    554. 

  554. 		init_smic_data(smic, smic->io);
    555. 

  555. 		return SI_SM_HOSED;
    556. 

  556. 

  557. 	default:
    558. 

  558. 		if (smic_debug & SMIC_DEBUG_ENABLE) {
    559. 

  559. 			printk(KERN_WARNING "smic->state = %d\n", smic->state);
    560. 

  560. 			start_error_recovery(smic, "state = UNKNOWN");
    561. 

  561. 			return SI_SM_CALL_WITH_DELAY;
    562. 

  562. 		}
    563. 

  563. 	}
    564. 

  564. 	smic->smic_timeout = SMIC_RETRY_TIMEOUT;
    565. 

  565. 	return SI_SM_CALL_WITHOUT_DELAY;
    566. 

  566. }
    567. 

  567. 

  568. static int smic_detect(struct si_sm_data *smic)
    569. 

  569. {
    570. 

  570. 	/* It's impossible for the SMIC fnags register to be all 1's,
    571. 

  571. 	   (assuming a properly functioning, self-initialized BMC)
    572. 

  572. 	   but that's what you get from reading a bogus address, so we
    573. 

  573. 	   test that first. */
    574. 

  574. 	if (read_smic_flags(smic) == 0xff)
    575. 

  575. 		return 1;
    576. 

  576. 

  577. 	return 0;
    578. 

  578. }
    579. 

  579. 

  580. static void smic_cleanup(struct si_sm_data *kcs)
    581. 

  581. {
    582. 

  582. }
    583. 

  583. 

  584. static int smic_size(void)
    585. 

  585. {
    586. 

  586. 	return sizeof(struct si_sm_data);
    587. 

  587. }
    588. 

  588. 

  589. struct si_sm_handlers smic_smi_handlers =
    590. 

  590. {
    591. 

  591. 	.version           = IPMI_SMIC_VERSION,
    592. 

  592. 	.init_data         = init_smic_data,
    593. 

  593. 	.start_transaction = start_smic_transaction,
    594. 

  594. 	.get_result        = smic_get_result,
    595. 

  595. 	.event             = smic_event,
    596. 

  596. 	.detect            = smic_detect,
    597. 

  597. 	.cleanup           = smic_cleanup,
    598. 

  598. 	.size              = smic_size,
    599. 

  599. };
    600.