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/drivers/char/drm/i810_drm.h

https://bitbucket.org/evzijst/gittest
C Header | 289 lines | 200 code | 35 blank | 54 comment | 0 complexity | ab0b84cf05c514f058afa398cceffffa MD5 | raw file
  1#ifndef _I810_DRM_H_
  2#define _I810_DRM_H_
  3
  4/* WARNING: These defines must be the same as what the Xserver uses.
  5 * if you change them, you must change the defines in the Xserver.
  6 */
  7
  8#ifndef _I810_DEFINES_
  9#define _I810_DEFINES_
 10
 11#define I810_DMA_BUF_ORDER		12
 12#define I810_DMA_BUF_SZ 		(1<<I810_DMA_BUF_ORDER)
 13#define I810_DMA_BUF_NR 		256
 14#define I810_NR_SAREA_CLIPRECTS 	8
 15
 16/* Each region is a minimum of 64k, and there are at most 64 of them.
 17 */
 18#define I810_NR_TEX_REGIONS 64
 19#define I810_LOG_MIN_TEX_REGION_SIZE 16
 20#endif
 21
 22#define I810_UPLOAD_TEX0IMAGE  0x1 /* handled clientside */
 23#define I810_UPLOAD_TEX1IMAGE  0x2 /* handled clientside */
 24#define I810_UPLOAD_CTX        0x4
 25#define I810_UPLOAD_BUFFERS    0x8
 26#define I810_UPLOAD_TEX0       0x10
 27#define I810_UPLOAD_TEX1       0x20
 28#define I810_UPLOAD_CLIPRECTS  0x40
 29
 30
 31/* Indices into buf.Setup where various bits of state are mirrored per
 32 * context and per buffer.  These can be fired at the card as a unit,
 33 * or in a piecewise fashion as required.
 34 */
 35
 36/* Destbuffer state 
 37 *    - backbuffer linear offset and pitch -- invarient in the current dri
 38 *    - zbuffer linear offset and pitch -- also invarient
 39 *    - drawing origin in back and depth buffers.
 40 *
 41 * Keep the depth/back buffer state here to accommodate private buffers
 42 * in the future.
 43 */
 44#define I810_DESTREG_DI0  0	/* CMD_OP_DESTBUFFER_INFO (2 dwords) */
 45#define I810_DESTREG_DI1  1
 46#define I810_DESTREG_DV0  2	/* GFX_OP_DESTBUFFER_VARS (2 dwords) */
 47#define I810_DESTREG_DV1  3
 48#define I810_DESTREG_DR0  4	/* GFX_OP_DRAWRECT_INFO (4 dwords) */
 49#define I810_DESTREG_DR1  5
 50#define I810_DESTREG_DR2  6
 51#define I810_DESTREG_DR3  7
 52#define I810_DESTREG_DR4  8
 53#define I810_DEST_SETUP_SIZE 10
 54
 55/* Context state
 56 */
 57#define I810_CTXREG_CF0   0	/* GFX_OP_COLOR_FACTOR */
 58#define I810_CTXREG_CF1   1	
 59#define I810_CTXREG_ST0   2     /* GFX_OP_STIPPLE */
 60#define I810_CTXREG_ST1   3
 61#define I810_CTXREG_VF    4	/* GFX_OP_VERTEX_FMT */
 62#define I810_CTXREG_MT    5	/* GFX_OP_MAP_TEXELS */
 63#define I810_CTXREG_MC0   6	/* GFX_OP_MAP_COLOR_STAGES - stage 0 */
 64#define I810_CTXREG_MC1   7     /* GFX_OP_MAP_COLOR_STAGES - stage 1 */
 65#define I810_CTXREG_MC2   8	/* GFX_OP_MAP_COLOR_STAGES - stage 2 */
 66#define I810_CTXREG_MA0   9	/* GFX_OP_MAP_ALPHA_STAGES - stage 0 */
 67#define I810_CTXREG_MA1   10	/* GFX_OP_MAP_ALPHA_STAGES - stage 1 */
 68#define I810_CTXREG_MA2   11	/* GFX_OP_MAP_ALPHA_STAGES - stage 2 */
 69#define I810_CTXREG_SDM   12	/* GFX_OP_SRC_DEST_MONO */
 70#define I810_CTXREG_FOG   13	/* GFX_OP_FOG_COLOR */
 71#define I810_CTXREG_B1    14	/* GFX_OP_BOOL_1 */
 72#define I810_CTXREG_B2    15	/* GFX_OP_BOOL_2 */
 73#define I810_CTXREG_LCS   16	/* GFX_OP_LINEWIDTH_CULL_SHADE_MODE */
 74#define I810_CTXREG_PV    17	/* GFX_OP_PV_RULE -- Invarient! */
 75#define I810_CTXREG_ZA    18	/* GFX_OP_ZBIAS_ALPHAFUNC */
 76#define I810_CTXREG_AA    19	/* GFX_OP_ANTIALIAS */
 77#define I810_CTX_SETUP_SIZE 20 
 78
 79/* Texture state (per tex unit)
 80 */
 81#define I810_TEXREG_MI0  0	/* GFX_OP_MAP_INFO (4 dwords) */
 82#define I810_TEXREG_MI1  1	
 83#define I810_TEXREG_MI2  2	
 84#define I810_TEXREG_MI3  3	
 85#define I810_TEXREG_MF   4	/* GFX_OP_MAP_FILTER */
 86#define I810_TEXREG_MLC  5	/* GFX_OP_MAP_LOD_CTL */
 87#define I810_TEXREG_MLL  6	/* GFX_OP_MAP_LOD_LIMITS */
 88#define I810_TEXREG_MCS  7	/* GFX_OP_MAP_COORD_SETS ??? */
 89#define I810_TEX_SETUP_SIZE 8
 90
 91/* Flags for clear ioctl
 92 */
 93#define I810_FRONT   0x1
 94#define I810_BACK    0x2
 95#define I810_DEPTH   0x4
 96
 97typedef enum _drm_i810_init_func {
 98	I810_INIT_DMA = 0x01,
 99	I810_CLEANUP_DMA = 0x02,
100	I810_INIT_DMA_1_4 = 0x03
101 } drm_i810_init_func_t;
102
103/* This is the init structure after v1.2 */
104typedef struct _drm_i810_init {
105	drm_i810_init_func_t func;
106#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
107	int ring_map_idx;
108	int buffer_map_idx;
109#else
110	unsigned int mmio_offset;
111	unsigned int buffers_offset;
112#endif
113	int sarea_priv_offset;
114	unsigned int ring_start;
115	unsigned int ring_end;
116	unsigned int ring_size;
117	unsigned int front_offset;
118	unsigned int back_offset;
119	unsigned int depth_offset;
120	unsigned int overlay_offset;
121	unsigned int overlay_physical;
122	unsigned int w;
123	unsigned int h;
124	unsigned int pitch;
125	unsigned int pitch_bits; 
126} drm_i810_init_t;
127
128/* This is the init structure prior to v1.2 */
129typedef struct _drm_i810_pre12_init {
130	drm_i810_init_func_t func;
131	unsigned int mmio_offset;
132	unsigned int buffers_offset;
133	int sarea_priv_offset;
134	unsigned int ring_start;
135	unsigned int ring_end;
136	unsigned int ring_size;
137	unsigned int front_offset;
138	unsigned int back_offset;
139	unsigned int depth_offset;
140	unsigned int w;
141	unsigned int h;
142	unsigned int pitch;
143	unsigned int pitch_bits; 
144} drm_i810_pre12_init_t;
145
146/* Warning: If you change the SAREA structure you must change the Xserver
147 * structure as well */
148
149typedef struct _drm_i810_tex_region {
150	unsigned char next, prev; /* indices to form a circular LRU  */
151	unsigned char in_use;	/* owned by a client, or free? */
152	int age;		/* tracked by clients to update local LRU's */
153} drm_i810_tex_region_t;
154
155typedef struct _drm_i810_sarea {
156   	unsigned int ContextState[I810_CTX_SETUP_SIZE];
157   	unsigned int BufferState[I810_DEST_SETUP_SIZE];
158   	unsigned int TexState[2][I810_TEX_SETUP_SIZE];
159   	unsigned int dirty;
160
161	unsigned int nbox;
162	drm_clip_rect_t boxes[I810_NR_SAREA_CLIPRECTS];
163
164	/* Maintain an LRU of contiguous regions of texture space.  If
165	 * you think you own a region of texture memory, and it has an
166	 * age different to the one you set, then you are mistaken and
167	 * it has been stolen by another client.  If global texAge
168	 * hasn't changed, there is no need to walk the list.
169	 *
170	 * These regions can be used as a proxy for the fine-grained
171	 * texture information of other clients - by maintaining them
172	 * in the same lru which is used to age their own textures,
173	 * clients have an approximate lru for the whole of global
174	 * texture space, and can make informed decisions as to which
175	 * areas to kick out.  There is no need to choose whether to
176	 * kick out your own texture or someone else's - simply eject
177	 * them all in LRU order.  
178	 */
179   
180	drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS+1]; 
181				/* Last elt is sentinal */
182        int texAge;		/* last time texture was uploaded */
183        int last_enqueue;	/* last time a buffer was enqueued */
184	int last_dispatch;	/* age of the most recently dispatched buffer */
185	int last_quiescent;     /*  */
186	int ctxOwner;		/* last context to upload state */
187
188	int vertex_prim;
189
190	int pf_enabled;               /* is pageflipping allowed? */
191	int pf_active;
192	int pf_current_page;	    /* which buffer is being displayed? */
193} drm_i810_sarea_t;
194
195/* WARNING: If you change any of these defines, make sure to change the
196 * defines in the Xserver file (xf86drmMga.h)
197 */
198
199/* i810 specific ioctls
200 * The device specific ioctl range is 0x40 to 0x79.
201 */
202#define DRM_I810_INIT		0x00
203#define DRM_I810_VERTEX		0x01
204#define DRM_I810_CLEAR		0x02
205#define DRM_I810_FLUSH		0x03
206#define DRM_I810_GETAGE		0x04
207#define DRM_I810_GETBUF		0x05
208#define DRM_I810_SWAP		0x06
209#define DRM_I810_COPY		0x07
210#define DRM_I810_DOCOPY		0x08
211#define DRM_I810_OV0INFO	0x09
212#define DRM_I810_FSTATUS	0x0a
213#define DRM_I810_OV0FLIP	0x0b
214#define DRM_I810_MC		0x0c
215#define DRM_I810_RSTATUS	0x0d
216#define DRM_I810_FLIP		0x0e
217
218#define DRM_IOCTL_I810_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I810_INIT, drm_i810_init_t)
219#define DRM_IOCTL_I810_VERTEX		DRM_IOW( DRM_COMMAND_BASE + DRM_I810_VERTEX, drm_i810_vertex_t)
220#define DRM_IOCTL_I810_CLEAR		DRM_IOW( DRM_COMMAND_BASE + DRM_I810_CLEAR, drm_i810_clear_t)
221#define DRM_IOCTL_I810_FLUSH		DRM_IO(  DRM_COMMAND_BASE + DRM_I810_FLUSH)
222#define DRM_IOCTL_I810_GETAGE		DRM_IO(  DRM_COMMAND_BASE + DRM_I810_GETAGE)
223#define DRM_IOCTL_I810_GETBUF		DRM_IOWR(DRM_COMMAND_BASE + DRM_I810_GETBUF, drm_i810_dma_t)
224#define DRM_IOCTL_I810_SWAP		DRM_IO(  DRM_COMMAND_BASE + DRM_I810_SWAP)
225#define DRM_IOCTL_I810_COPY		DRM_IOW( DRM_COMMAND_BASE + DRM_I810_COPY, drm_i810_copy_t)
226#define DRM_IOCTL_I810_DOCOPY		DRM_IO(  DRM_COMMAND_BASE + DRM_I810_DOCOPY)
227#define DRM_IOCTL_I810_OV0INFO		DRM_IOR( DRM_COMMAND_BASE + DRM_I810_OV0INFO, drm_i810_overlay_t)
228#define DRM_IOCTL_I810_FSTATUS		DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FSTATUS)
229#define DRM_IOCTL_I810_OV0FLIP		DRM_IO ( DRM_COMMAND_BASE + DRM_I810_OV0FLIP)
230#define DRM_IOCTL_I810_MC		DRM_IOW( DRM_COMMAND_BASE + DRM_I810_MC, drm_i810_mc_t)
231#define DRM_IOCTL_I810_RSTATUS		DRM_IO ( DRM_COMMAND_BASE + DRM_I810_RSTATUS)
232#define DRM_IOCTL_I810_FLIP             DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FLIP)
233
234typedef struct _drm_i810_clear {
235	int clear_color;
236	int clear_depth;
237	int flags;
238} drm_i810_clear_t;
239
240/* These may be placeholders if we have more cliprects than
241 * I810_NR_SAREA_CLIPRECTS.  In that case, the client sets discard to
242 * false, indicating that the buffer will be dispatched again with a
243 * new set of cliprects.
244 */
245typedef struct _drm_i810_vertex {
246   	int idx;		/* buffer index */
247	int used;		/* nr bytes in use */
248	int discard;		/* client is finished with the buffer? */
249} drm_i810_vertex_t;
250
251typedef struct _drm_i810_copy_t {
252   	int idx;		/* buffer index */
253	int used;		/* nr bytes in use */
254	void *address;		/* Address to copy from */
255} drm_i810_copy_t;
256
257#define PR_TRIANGLES         (0x0<<18)
258#define PR_TRISTRIP_0        (0x1<<18)
259#define PR_TRISTRIP_1        (0x2<<18)
260#define PR_TRIFAN            (0x3<<18)
261#define PR_POLYGON           (0x4<<18)
262#define PR_LINES             (0x5<<18)
263#define PR_LINESTRIP         (0x6<<18)
264#define PR_RECTS             (0x7<<18)
265#define PR_MASK              (0x7<<18)
266
267
268typedef struct drm_i810_dma {
269	void *virtual;
270	int request_idx;
271	int request_size;
272	int granted;
273} drm_i810_dma_t;
274
275typedef struct _drm_i810_overlay_t {
276	unsigned int offset;    /* Address of the Overlay Regs */
277	unsigned int physical;
278} drm_i810_overlay_t;
279
280typedef struct _drm_i810_mc {
281	int idx;                /* buffer index */
282	int used;               /* nr bytes in use */
283	int num_blocks;         /* number of GFXBlocks */
284	int *length;            /* List of lengths for GFXBlocks (FUTURE)*/
285	unsigned int last_render; /* Last Render Request */
286} drm_i810_mc_t;
287
288
289#endif /* _I810_DRM_H_ */