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/drivers/char/agp/sis-agp.c

https://bitbucket.org/evzijst/gittest
C | 360 lines | 300 code | 47 blank | 13 comment | 21 complexity | ef4442215ba0f1d77edf6fba3aca9cfd MD5 | raw file
  1/*
  2 * SiS AGPGART routines.
  3 */
  4
  5#include <linux/module.h>
  6#include <linux/pci.h>
  7#include <linux/init.h>
  8#include <linux/agp_backend.h>
  9#include <linux/delay.h>
 10#include "agp.h"
 11
 12#define SIS_ATTBASE	0x90
 13#define SIS_APSIZE	0x94
 14#define SIS_TLBCNTRL	0x97
 15#define SIS_TLBFLUSH	0x98
 16
 17static int __devinitdata agp_sis_force_delay = 0;
 18static int __devinitdata agp_sis_agp_spec = -1;
 19
 20static int sis_fetch_size(void)
 21{
 22	u8 temp_size;
 23	int i;
 24	struct aper_size_info_8 *values;
 25
 26	pci_read_config_byte(agp_bridge->dev, SIS_APSIZE, &temp_size);
 27	values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
 28	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
 29		if ((temp_size == values[i].size_value) ||
 30		    ((temp_size & ~(0x03)) ==
 31		     (values[i].size_value & ~(0x03)))) {
 32			agp_bridge->previous_size =
 33			    agp_bridge->current_size = (void *) (values + i);
 34
 35			agp_bridge->aperture_size_idx = i;
 36			return values[i].size;
 37		}
 38	}
 39
 40	return 0;
 41}
 42
 43static void sis_tlbflush(struct agp_memory *mem)
 44{
 45	pci_write_config_byte(agp_bridge->dev, SIS_TLBFLUSH, 0x02);
 46}
 47
 48static int sis_configure(void)
 49{
 50	u32 temp;
 51	struct aper_size_info_8 *current_size;
 52
 53	current_size = A_SIZE_8(agp_bridge->current_size);
 54	pci_write_config_byte(agp_bridge->dev, SIS_TLBCNTRL, 0x05);
 55	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
 56	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 57	pci_write_config_dword(agp_bridge->dev, SIS_ATTBASE,
 58			       agp_bridge->gatt_bus_addr);
 59	pci_write_config_byte(agp_bridge->dev, SIS_APSIZE,
 60			      current_size->size_value);
 61	return 0;
 62}
 63
 64static void sis_cleanup(void)
 65{
 66	struct aper_size_info_8 *previous_size;
 67
 68	previous_size = A_SIZE_8(agp_bridge->previous_size);
 69	pci_write_config_byte(agp_bridge->dev, SIS_APSIZE,
 70			      (previous_size->size_value & ~(0x03)));
 71}
 72
 73static void sis_delayed_enable(struct agp_bridge_data *bridge, u32 mode)
 74{
 75	struct pci_dev *device = NULL;
 76	u32 command;
 77	int rate;
 78
 79	printk(KERN_INFO PFX "Found an AGP %d.%d compliant device at %s.\n",
 80		agp_bridge->major_version,
 81		agp_bridge->minor_version,
 82		pci_name(agp_bridge->dev));
 83
 84	pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx + PCI_AGP_STATUS, &command);
 85	command = agp_collect_device_status(bridge, mode, command);
 86	command |= AGPSTAT_AGP_ENABLE;
 87	rate = (command & 0x7) << 2;
 88
 89	for_each_pci_dev(device) {
 90		u8 agp = pci_find_capability(device, PCI_CAP_ID_AGP);
 91		if (!agp)
 92			continue;
 93
 94		printk(KERN_INFO PFX "Putting AGP V3 device at %s into %dx mode\n",
 95			pci_name(device), rate);
 96
 97		pci_write_config_dword(device, agp + PCI_AGP_COMMAND, command);
 98
 99		/*
100		 * Weird: on some sis chipsets any rate change in the target
101		 * command register triggers a 5ms screwup during which the master
102		 * cannot be configured
103		 */
104		if (device->device == bridge->dev->device) {
105			printk(KERN_INFO PFX "SiS delay workaround: giving bridge time to recover.\n");
106			msleep(10);
107		}
108	}
109}
110
111static struct aper_size_info_8 sis_generic_sizes[7] =
112{
113	{256, 65536, 6, 99},
114	{128, 32768, 5, 83},
115	{64, 16384, 4, 67},
116	{32, 8192, 3, 51},
117	{16, 4096, 2, 35},
118	{8, 2048, 1, 19},
119	{4, 1024, 0, 3}
120};
121
122struct agp_bridge_driver sis_driver = {
123	.owner			= THIS_MODULE,
124	.aperture_sizes 	= sis_generic_sizes,
125	.size_type		= U8_APER_SIZE,
126	.num_aperture_sizes	= 7,
127	.configure		= sis_configure,
128	.fetch_size		= sis_fetch_size,
129	.cleanup		= sis_cleanup,
130	.tlb_flush		= sis_tlbflush,
131	.mask_memory		= agp_generic_mask_memory,
132	.masks			= NULL,
133	.agp_enable		= agp_generic_enable,
134	.cache_flush		= global_cache_flush,
135	.create_gatt_table	= agp_generic_create_gatt_table,
136	.free_gatt_table	= agp_generic_free_gatt_table,
137	.insert_memory		= agp_generic_insert_memory,
138	.remove_memory		= agp_generic_remove_memory,
139	.alloc_by_type		= agp_generic_alloc_by_type,
140	.free_by_type		= agp_generic_free_by_type,
141	.agp_alloc_page		= agp_generic_alloc_page,
142	.agp_destroy_page	= agp_generic_destroy_page,
143};
144
145static struct agp_device_ids sis_agp_device_ids[] __devinitdata =
146{
147	{
148		.device_id	= PCI_DEVICE_ID_SI_5591_AGP,
149		.chipset_name	= "5591",
150	},
151	{
152		.device_id	= PCI_DEVICE_ID_SI_530,
153		.chipset_name	= "530",
154	},
155	{
156		.device_id	= PCI_DEVICE_ID_SI_540,
157		.chipset_name	= "540",
158	},
159	{
160		.device_id	= PCI_DEVICE_ID_SI_550,
161		.chipset_name	= "550",
162	},
163	{
164		.device_id	= PCI_DEVICE_ID_SI_620,
165		.chipset_name	= "620",
166	},
167	{
168		.device_id	= PCI_DEVICE_ID_SI_630,
169		.chipset_name	= "630",
170	},
171	{
172		.device_id	= PCI_DEVICE_ID_SI_635,
173		.chipset_name	= "635",
174	},
175	{
176		.device_id	= PCI_DEVICE_ID_SI_645,
177		.chipset_name	= "645",
178	},
179	{
180		.device_id	= PCI_DEVICE_ID_SI_646,
181		.chipset_name	= "646",
182	},
183	{
184		.device_id	= PCI_DEVICE_ID_SI_648,
185		.chipset_name	= "648",
186	},
187	{
188		.device_id	= PCI_DEVICE_ID_SI_650,
189		.chipset_name	= "650",
190	},
191	{
192		.device_id  = PCI_DEVICE_ID_SI_651,
193		.chipset_name   = "651",
194	},
195	{
196		.device_id	= PCI_DEVICE_ID_SI_655,
197		.chipset_name	= "655",
198	},
199	{
200		.device_id	= PCI_DEVICE_ID_SI_661,
201		.chipset_name	= "661",
202	},
203	{
204		.device_id	= PCI_DEVICE_ID_SI_730,
205		.chipset_name	= "730",
206	},
207	{
208		.device_id	= PCI_DEVICE_ID_SI_735,
209		.chipset_name	= "735",
210	},
211	{
212		.device_id	= PCI_DEVICE_ID_SI_740,
213		.chipset_name	= "740",
214	},
215	{
216		.device_id	= PCI_DEVICE_ID_SI_741,
217		.chipset_name	= "741",
218	},
219	{
220		.device_id	= PCI_DEVICE_ID_SI_745,
221		.chipset_name	= "745",
222	},
223	{
224		.device_id	= PCI_DEVICE_ID_SI_746,
225		.chipset_name	= "746",
226	},
227	{
228		.device_id	= PCI_DEVICE_ID_SI_760,
229		.chipset_name	= "760",
230	},
231	{ }, /* dummy final entry, always present */
232};
233
234
235// chipsets that require the 'delay hack'
236static int sis_broken_chipsets[] __devinitdata = {
237	PCI_DEVICE_ID_SI_648,
238	PCI_DEVICE_ID_SI_746,
239	0 // terminator
240};
241
242static void __devinit sis_get_driver(struct agp_bridge_data *bridge)
243{
244	int i;
245
246	for(i=0; sis_broken_chipsets[i]!=0; ++i)
247		if(bridge->dev->device==sis_broken_chipsets[i])
248			break;
249
250	if(sis_broken_chipsets[i] || agp_sis_force_delay)
251		sis_driver.agp_enable=sis_delayed_enable;
252
253	// sis chipsets that indicate less than agp3.5
254	// are not actually fully agp3 compliant
255	if ((agp_bridge->major_version == 3 && agp_bridge->minor_version >= 5
256	     && agp_sis_agp_spec!=0) || agp_sis_agp_spec==1) {
257		sis_driver.aperture_sizes = agp3_generic_sizes;
258		sis_driver.size_type = U16_APER_SIZE;
259		sis_driver.num_aperture_sizes = AGP_GENERIC_SIZES_ENTRIES;
260		sis_driver.configure = agp3_generic_configure;
261		sis_driver.fetch_size = agp3_generic_fetch_size;
262		sis_driver.cleanup = agp3_generic_cleanup;
263		sis_driver.tlb_flush = agp3_generic_tlbflush;
264	}
265}
266
267
268static int __devinit agp_sis_probe(struct pci_dev *pdev,
269				   const struct pci_device_id *ent)
270{
271	struct agp_device_ids *devs = sis_agp_device_ids;
272	struct agp_bridge_data *bridge;
273	u8 cap_ptr;
274	int j;
275
276	cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
277	if (!cap_ptr)
278		return -ENODEV;
279
280	/* probe for known chipsets */
281	for (j = 0; devs[j].chipset_name; j++) {
282		if (pdev->device == devs[j].device_id) {
283			printk(KERN_INFO PFX "Detected SiS %s chipset\n",
284					devs[j].chipset_name);
285			goto found;
286		}
287	}
288
289	printk(KERN_ERR PFX "Unsupported SiS chipset (device id: %04x)\n",
290		    pdev->device);
291	return -ENODEV;
292
293found:
294	bridge = agp_alloc_bridge();
295	if (!bridge)
296		return -ENOMEM;
297
298	bridge->driver = &sis_driver;
299	bridge->dev = pdev;
300	bridge->capndx = cap_ptr;
301
302	get_agp_version(bridge);
303
304	/* Fill in the mode register */
305	pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
306	sis_get_driver(bridge);
307
308	pci_set_drvdata(pdev, bridge);
309	return agp_add_bridge(bridge);
310}
311
312static void __devexit agp_sis_remove(struct pci_dev *pdev)
313{
314	struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
315
316	agp_remove_bridge(bridge);
317	agp_put_bridge(bridge);
318}
319
320static struct pci_device_id agp_sis_pci_table[] = {
321	{
322	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
323	.class_mask	= ~0,
324	.vendor		= PCI_VENDOR_ID_SI,
325	.device		= PCI_ANY_ID,
326	.subvendor	= PCI_ANY_ID,
327	.subdevice	= PCI_ANY_ID,
328	},
329	{ }
330};
331
332MODULE_DEVICE_TABLE(pci, agp_sis_pci_table);
333
334static struct pci_driver agp_sis_pci_driver = {
335	.name		= "agpgart-sis",
336	.id_table	= agp_sis_pci_table,
337	.probe		= agp_sis_probe,
338	.remove		= agp_sis_remove,
339};
340
341static int __init agp_sis_init(void)
342{
343	if (agp_off)
344		return -EINVAL;
345	return pci_register_driver(&agp_sis_pci_driver);
346}
347
348static void __exit agp_sis_cleanup(void)
349{
350	pci_unregister_driver(&agp_sis_pci_driver);
351}
352
353module_init(agp_sis_init);
354module_exit(agp_sis_cleanup);
355
356module_param(agp_sis_force_delay, bool, 0);
357MODULE_PARM_DESC(agp_sis_force_delay,"forces sis delay hack");
358module_param(agp_sis_agp_spec, int, 0);
359MODULE_PARM_DESC(agp_sis_agp_spec,"0=force sis init, 1=force generic agp3 init, default: autodetect");
360MODULE_LICENSE("GPL and additional rights");