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/arch/x86_64/kernel/i8259.c

https://bitbucket.org/evzijst/gittest
C | 579 lines | 358 code | 89 blank | 132 comment | 25 complexity | 3c39df833f8978253885b631ebfc5657 MD5 | raw file
  1#include <linux/linkage.h>
  2#include <linux/config.h>
  3#include <linux/errno.h>
  4#include <linux/signal.h>
  5#include <linux/sched.h>
  6#include <linux/ioport.h>
  7#include <linux/interrupt.h>
  8#include <linux/timex.h>
  9#include <linux/slab.h>
 10#include <linux/random.h>
 11#include <linux/smp_lock.h>
 12#include <linux/init.h>
 13#include <linux/kernel_stat.h>
 14#include <linux/sysdev.h>
 15#include <linux/bitops.h>
 16
 17#include <asm/acpi.h>
 18#include <asm/atomic.h>
 19#include <asm/system.h>
 20#include <asm/io.h>
 21#include <asm/irq.h>
 22#include <asm/hw_irq.h>
 23#include <asm/pgtable.h>
 24#include <asm/delay.h>
 25#include <asm/desc.h>
 26#include <asm/apic.h>
 27
 28#include <linux/irq.h>
 29
 30/*
 31 * Common place to define all x86 IRQ vectors
 32 *
 33 * This builds up the IRQ handler stubs using some ugly macros in irq.h
 34 *
 35 * These macros create the low-level assembly IRQ routines that save
 36 * register context and call do_IRQ(). do_IRQ() then does all the
 37 * operations that are needed to keep the AT (or SMP IOAPIC)
 38 * interrupt-controller happy.
 39 */
 40
 41#define BI(x,y) \
 42	BUILD_IRQ(x##y)
 43
 44#define BUILD_16_IRQS(x) \
 45	BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
 46	BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
 47	BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
 48	BI(x,c) BI(x,d) BI(x,e) BI(x,f)
 49
 50#define BUILD_14_IRQS(x) \
 51	BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
 52	BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
 53	BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
 54	BI(x,c) BI(x,d)
 55
 56/*
 57 * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
 58 * (these are usually mapped to vectors 0x20-0x2f)
 59 */
 60BUILD_16_IRQS(0x0)
 61
 62#ifdef CONFIG_X86_LOCAL_APIC
 63/*
 64 * The IO-APIC gives us many more interrupt sources. Most of these 
 65 * are unused but an SMP system is supposed to have enough memory ...
 66 * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
 67 * across the spectrum, so we really want to be prepared to get all
 68 * of these. Plus, more powerful systems might have more than 64
 69 * IO-APIC registers.
 70 *
 71 * (these are usually mapped into the 0x30-0xff vector range)
 72 */
 73		   BUILD_16_IRQS(0x1) BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
 74BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7)
 75BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb)
 76BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd)
 77
 78#ifdef CONFIG_PCI_MSI
 79	BUILD_14_IRQS(0xe)
 80#endif
 81
 82#endif
 83
 84#undef BUILD_16_IRQS
 85#undef BUILD_14_IRQS
 86#undef BI
 87
 88
 89#define IRQ(x,y) \
 90	IRQ##x##y##_interrupt
 91
 92#define IRQLIST_16(x) \
 93	IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
 94	IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
 95	IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
 96	IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
 97
 98#define IRQLIST_14(x) \
 99	IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
100	IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
101	IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
102	IRQ(x,c), IRQ(x,d)
103
104void (*interrupt[NR_IRQS])(void) = {
105	IRQLIST_16(0x0),
106
107#ifdef CONFIG_X86_IO_APIC
108			 IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3),
109	IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
110	IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
111	IRQLIST_16(0xc), IRQLIST_16(0xd)
112
113#ifdef CONFIG_PCI_MSI
114	, IRQLIST_14(0xe)
115#endif
116
117#endif
118};
119
120#undef IRQ
121#undef IRQLIST_16
122#undef IRQLIST_14
123
124/*
125 * This is the 'legacy' 8259A Programmable Interrupt Controller,
126 * present in the majority of PC/AT boxes.
127 * plus some generic x86 specific things if generic specifics makes
128 * any sense at all.
129 * this file should become arch/i386/kernel/irq.c when the old irq.c
130 * moves to arch independent land
131 */
132
133DEFINE_SPINLOCK(i8259A_lock);
134
135static void end_8259A_irq (unsigned int irq)
136{
137	if (irq > 256) { 
138		char var;
139		printk("return %p stack %p ti %p\n", __builtin_return_address(0), &var, current->thread_info); 
140
141		BUG(); 
142	}
143
144	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
145	    irq_desc[irq].action)
146		enable_8259A_irq(irq);
147}
148
149#define shutdown_8259A_irq	disable_8259A_irq
150
151static void mask_and_ack_8259A(unsigned int);
152
153static unsigned int startup_8259A_irq(unsigned int irq)
154{ 
155	enable_8259A_irq(irq);
156	return 0; /* never anything pending */
157}
158
159static struct hw_interrupt_type i8259A_irq_type = {
160	"XT-PIC",
161	startup_8259A_irq,
162	shutdown_8259A_irq,
163	enable_8259A_irq,
164	disable_8259A_irq,
165	mask_and_ack_8259A,
166	end_8259A_irq,
167	NULL
168};
169
170/*
171 * 8259A PIC functions to handle ISA devices:
172 */
173
174/*
175 * This contains the irq mask for both 8259A irq controllers,
176 */
177static unsigned int cached_irq_mask = 0xffff;
178
179#define __byte(x,y) 	(((unsigned char *)&(y))[x])
180#define cached_21	(__byte(0,cached_irq_mask))
181#define cached_A1	(__byte(1,cached_irq_mask))
182
183/*
184 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
185 * boards the timer interrupt is not really connected to any IO-APIC pin,
186 * it's fed to the master 8259A's IR0 line only.
187 *
188 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
189 * this 'mixed mode' IRQ handling costs nothing because it's only used
190 * at IRQ setup time.
191 */
192unsigned long io_apic_irqs;
193
194void disable_8259A_irq(unsigned int irq)
195{
196	unsigned int mask = 1 << irq;
197	unsigned long flags;
198
199	spin_lock_irqsave(&i8259A_lock, flags);
200	cached_irq_mask |= mask;
201	if (irq & 8)
202		outb(cached_A1,0xA1);
203	else
204		outb(cached_21,0x21);
205	spin_unlock_irqrestore(&i8259A_lock, flags);
206}
207
208void enable_8259A_irq(unsigned int irq)
209{
210	unsigned int mask = ~(1 << irq);
211	unsigned long flags;
212
213	spin_lock_irqsave(&i8259A_lock, flags);
214	cached_irq_mask &= mask;
215	if (irq & 8)
216		outb(cached_A1,0xA1);
217	else
218		outb(cached_21,0x21);
219	spin_unlock_irqrestore(&i8259A_lock, flags);
220}
221
222int i8259A_irq_pending(unsigned int irq)
223{
224	unsigned int mask = 1<<irq;
225	unsigned long flags;
226	int ret;
227
228	spin_lock_irqsave(&i8259A_lock, flags);
229	if (irq < 8)
230		ret = inb(0x20) & mask;
231	else
232		ret = inb(0xA0) & (mask >> 8);
233	spin_unlock_irqrestore(&i8259A_lock, flags);
234
235	return ret;
236}
237
238void make_8259A_irq(unsigned int irq)
239{
240	disable_irq_nosync(irq);
241	io_apic_irqs &= ~(1<<irq);
242	irq_desc[irq].handler = &i8259A_irq_type;
243	enable_irq(irq);
244}
245
246/*
247 * This function assumes to be called rarely. Switching between
248 * 8259A registers is slow.
249 * This has to be protected by the irq controller spinlock
250 * before being called.
251 */
252static inline int i8259A_irq_real(unsigned int irq)
253{
254	int value;
255	int irqmask = 1<<irq;
256
257	if (irq < 8) {
258		outb(0x0B,0x20);		/* ISR register */
259		value = inb(0x20) & irqmask;
260		outb(0x0A,0x20);		/* back to the IRR register */
261		return value;
262	}
263	outb(0x0B,0xA0);		/* ISR register */
264	value = inb(0xA0) & (irqmask >> 8);
265	outb(0x0A,0xA0);		/* back to the IRR register */
266	return value;
267}
268
269/*
270 * Careful! The 8259A is a fragile beast, it pretty
271 * much _has_ to be done exactly like this (mask it
272 * first, _then_ send the EOI, and the order of EOI
273 * to the two 8259s is important!
274 */
275static void mask_and_ack_8259A(unsigned int irq)
276{
277	unsigned int irqmask = 1 << irq;
278	unsigned long flags;
279
280	spin_lock_irqsave(&i8259A_lock, flags);
281	/*
282	 * Lightweight spurious IRQ detection. We do not want
283	 * to overdo spurious IRQ handling - it's usually a sign
284	 * of hardware problems, so we only do the checks we can
285	 * do without slowing down good hardware unnecesserily.
286	 *
287	 * Note that IRQ7 and IRQ15 (the two spurious IRQs
288	 * usually resulting from the 8259A-1|2 PICs) occur
289	 * even if the IRQ is masked in the 8259A. Thus we
290	 * can check spurious 8259A IRQs without doing the
291	 * quite slow i8259A_irq_real() call for every IRQ.
292	 * This does not cover 100% of spurious interrupts,
293	 * but should be enough to warn the user that there
294	 * is something bad going on ...
295	 */
296	if (cached_irq_mask & irqmask)
297		goto spurious_8259A_irq;
298	cached_irq_mask |= irqmask;
299
300handle_real_irq:
301	if (irq & 8) {
302		inb(0xA1);		/* DUMMY - (do we need this?) */
303		outb(cached_A1,0xA1);
304		outb(0x60+(irq&7),0xA0);/* 'Specific EOI' to slave */
305		outb(0x62,0x20);	/* 'Specific EOI' to master-IRQ2 */
306	} else {
307		inb(0x21);		/* DUMMY - (do we need this?) */
308		outb(cached_21,0x21);
309		outb(0x60+irq,0x20);	/* 'Specific EOI' to master */
310	}
311	spin_unlock_irqrestore(&i8259A_lock, flags);
312	return;
313
314spurious_8259A_irq:
315	/*
316	 * this is the slow path - should happen rarely.
317	 */
318	if (i8259A_irq_real(irq))
319		/*
320		 * oops, the IRQ _is_ in service according to the
321		 * 8259A - not spurious, go handle it.
322		 */
323		goto handle_real_irq;
324
325	{
326		static int spurious_irq_mask;
327		/*
328		 * At this point we can be sure the IRQ is spurious,
329		 * lets ACK and report it. [once per IRQ]
330		 */
331		if (!(spurious_irq_mask & irqmask)) {
332			printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
333			spurious_irq_mask |= irqmask;
334		}
335		atomic_inc(&irq_err_count);
336		/*
337		 * Theoretically we do not have to handle this IRQ,
338		 * but in Linux this does not cause problems and is
339		 * simpler for us.
340		 */
341		goto handle_real_irq;
342	}
343}
344
345void init_8259A(int auto_eoi)
346{
347	unsigned long flags;
348
349	spin_lock_irqsave(&i8259A_lock, flags);
350
351	outb(0xff, 0x21);	/* mask all of 8259A-1 */
352	outb(0xff, 0xA1);	/* mask all of 8259A-2 */
353
354	/*
355	 * outb_p - this has to work on a wide range of PC hardware.
356	 */
357	outb_p(0x11, 0x20);	/* ICW1: select 8259A-1 init */
358	outb_p(0x20 + 0, 0x21);	/* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
359	outb_p(0x04, 0x21);	/* 8259A-1 (the master) has a slave on IR2 */
360	if (auto_eoi)
361		outb_p(0x03, 0x21);	/* master does Auto EOI */
362	else
363		outb_p(0x01, 0x21);	/* master expects normal EOI */
364
365	outb_p(0x11, 0xA0);	/* ICW1: select 8259A-2 init */
366	outb_p(0x20 + 8, 0xA1);	/* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
367	outb_p(0x02, 0xA1);	/* 8259A-2 is a slave on master's IR2 */
368	outb_p(0x01, 0xA1);	/* (slave's support for AEOI in flat mode
369				    is to be investigated) */
370
371	if (auto_eoi)
372		/*
373		 * in AEOI mode we just have to mask the interrupt
374		 * when acking.
375		 */
376		i8259A_irq_type.ack = disable_8259A_irq;
377	else
378		i8259A_irq_type.ack = mask_and_ack_8259A;
379
380	udelay(100);		/* wait for 8259A to initialize */
381
382	outb(cached_21, 0x21);	/* restore master IRQ mask */
383	outb(cached_A1, 0xA1);	/* restore slave IRQ mask */
384
385	spin_unlock_irqrestore(&i8259A_lock, flags);
386}
387
388static char irq_trigger[2];
389/**
390 * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
391 */
392static void restore_ELCR(char *trigger)
393{
394	outb(trigger[0], 0x4d0);
395	outb(trigger[1], 0x4d1);
396}
397
398static void save_ELCR(char *trigger)
399{
400	/* IRQ 0,1,2,8,13 are marked as reserved */
401	trigger[0] = inb(0x4d0) & 0xF8;
402	trigger[1] = inb(0x4d1) & 0xDE;
403}
404
405static int i8259A_resume(struct sys_device *dev)
406{
407	init_8259A(0);
408	restore_ELCR(irq_trigger);
409	return 0;
410}
411
412static int i8259A_suspend(struct sys_device *dev, u32 state)
413{
414	save_ELCR(irq_trigger);
415	return 0;
416}
417
418static struct sysdev_class i8259_sysdev_class = {
419	set_kset_name("i8259"),
420	.suspend = i8259A_suspend,
421	.resume = i8259A_resume,
422};
423
424static struct sys_device device_i8259A = {
425	.id	= 0,
426	.cls	= &i8259_sysdev_class,
427};
428
429static int __init i8259A_init_sysfs(void)
430{
431	int error = sysdev_class_register(&i8259_sysdev_class);
432	if (!error)
433		error = sysdev_register(&device_i8259A);
434	return error;
435}
436
437device_initcall(i8259A_init_sysfs);
438
439/*
440 * IRQ2 is cascade interrupt to second interrupt controller
441 */
442
443static struct irqaction irq2 = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL};
444
445void __init init_ISA_irqs (void)
446{
447	int i;
448
449#ifdef CONFIG_X86_LOCAL_APIC
450	init_bsp_APIC();
451#endif
452	init_8259A(0);
453
454	for (i = 0; i < NR_IRQS; i++) {
455		irq_desc[i].status = IRQ_DISABLED;
456		irq_desc[i].action = NULL;
457		irq_desc[i].depth = 1;
458
459		if (i < 16) {
460			/*
461			 * 16 old-style INTA-cycle interrupts:
462			 */
463			irq_desc[i].handler = &i8259A_irq_type;
464		} else {
465			/*
466			 * 'high' PCI IRQs filled in on demand
467			 */
468			irq_desc[i].handler = &no_irq_type;
469		}
470	}
471}
472
473void apic_timer_interrupt(void);
474void spurious_interrupt(void);
475void error_interrupt(void);
476void reschedule_interrupt(void);
477void call_function_interrupt(void);
478void invalidate_interrupt(void);
479void thermal_interrupt(void);
480void i8254_timer_resume(void);
481
482static void setup_timer(void)
483{
484	outb_p(0x34,0x43);		/* binary, mode 2, LSB/MSB, ch 0 */
485	udelay(10);
486	outb_p(LATCH & 0xff , 0x40);	/* LSB */
487	udelay(10);
488	outb(LATCH >> 8 , 0x40);	/* MSB */
489}
490
491static int timer_resume(struct sys_device *dev)
492{
493	setup_timer();
494	return 0;
495}
496
497void i8254_timer_resume(void)
498{
499	setup_timer();
500}
501
502static struct sysdev_class timer_sysclass = {
503	set_kset_name("timer"),
504	.resume		= timer_resume,
505};
506
507static struct sys_device device_timer = {
508	.id		= 0,
509	.cls		= &timer_sysclass,
510};
511
512static int __init init_timer_sysfs(void)
513{
514	int error = sysdev_class_register(&timer_sysclass);
515	if (!error)
516		error = sysdev_register(&device_timer);
517	return error;
518}
519
520device_initcall(init_timer_sysfs);
521
522void __init init_IRQ(void)
523{
524	int i;
525
526	init_ISA_irqs();
527	/*
528	 * Cover the whole vector space, no vector can escape
529	 * us. (some of these will be overridden and become
530	 * 'special' SMP interrupts)
531	 */
532	for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) {
533		int vector = FIRST_EXTERNAL_VECTOR + i;
534		if (i >= NR_IRQS)
535			break;
536		if (vector != IA32_SYSCALL_VECTOR && vector != KDB_VECTOR) { 
537			set_intr_gate(vector, interrupt[i]);
538	}
539	}
540
541#ifdef CONFIG_SMP
542	/*
543	 * IRQ0 must be given a fixed assignment and initialized,
544	 * because it's used before the IO-APIC is set up.
545	 */
546	set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
547
548	/*
549	 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
550	 * IPI, driven by wakeup.
551	 */
552	set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
553
554	/* IPI for invalidation */
555	set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
556
557	/* IPI for generic function call */
558	set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
559#endif	
560	set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
561
562#ifdef CONFIG_X86_LOCAL_APIC
563	/* self generated IPI for local APIC timer */
564	set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
565
566	/* IPI vectors for APIC spurious and error interrupts */
567	set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
568	set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
569#endif
570
571	/*
572	 * Set the clock to HZ Hz, we already have a valid
573	 * vector now:
574	 */
575	setup_timer();
576
577	if (!acpi_ioapic)
578		setup_irq(2, &irq2);
579}