/arch/x86_64/kernel/i8259.c

https://bitbucket.org/evzijst/gittest · C · 579 lines · 358 code · 89 blank · 132 comment · 25 complexity · 3c39df833f8978253885b631ebfc5657 MD5 · raw file

  1. #include <linux/linkage.h>
  2. #include <linux/config.h>
  3. #include <linux/errno.h>
  4. #include <linux/signal.h>
  5. #include <linux/sched.h>
  6. #include <linux/ioport.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/timex.h>
  9. #include <linux/slab.h>
  10. #include <linux/random.h>
  11. #include <linux/smp_lock.h>
  12. #include <linux/init.h>
  13. #include <linux/kernel_stat.h>
  14. #include <linux/sysdev.h>
  15. #include <linux/bitops.h>
  16. #include <asm/acpi.h>
  17. #include <asm/atomic.h>
  18. #include <asm/system.h>
  19. #include <asm/io.h>
  20. #include <asm/irq.h>
  21. #include <asm/hw_irq.h>
  22. #include <asm/pgtable.h>
  23. #include <asm/delay.h>
  24. #include <asm/desc.h>
  25. #include <asm/apic.h>
  26. #include <linux/irq.h>
  27. /*
  28. * Common place to define all x86 IRQ vectors
  29. *
  30. * This builds up the IRQ handler stubs using some ugly macros in irq.h
  31. *
  32. * These macros create the low-level assembly IRQ routines that save
  33. * register context and call do_IRQ(). do_IRQ() then does all the
  34. * operations that are needed to keep the AT (or SMP IOAPIC)
  35. * interrupt-controller happy.
  36. */
  37. #define BI(x,y) \
  38. BUILD_IRQ(x##y)
  39. #define BUILD_16_IRQS(x) \
  40. BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
  41. BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
  42. BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
  43. BI(x,c) BI(x,d) BI(x,e) BI(x,f)
  44. #define BUILD_14_IRQS(x) \
  45. BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
  46. BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
  47. BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
  48. BI(x,c) BI(x,d)
  49. /*
  50. * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
  51. * (these are usually mapped to vectors 0x20-0x2f)
  52. */
  53. BUILD_16_IRQS(0x0)
  54. #ifdef CONFIG_X86_LOCAL_APIC
  55. /*
  56. * The IO-APIC gives us many more interrupt sources. Most of these
  57. * are unused but an SMP system is supposed to have enough memory ...
  58. * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
  59. * across the spectrum, so we really want to be prepared to get all
  60. * of these. Plus, more powerful systems might have more than 64
  61. * IO-APIC registers.
  62. *
  63. * (these are usually mapped into the 0x30-0xff vector range)
  64. */
  65. BUILD_16_IRQS(0x1) BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
  66. BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7)
  67. BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb)
  68. BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd)
  69. #ifdef CONFIG_PCI_MSI
  70. BUILD_14_IRQS(0xe)
  71. #endif
  72. #endif
  73. #undef BUILD_16_IRQS
  74. #undef BUILD_14_IRQS
  75. #undef BI
  76. #define IRQ(x,y) \
  77. IRQ##x##y##_interrupt
  78. #define IRQLIST_16(x) \
  79. IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
  80. IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
  81. IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
  82. IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
  83. #define IRQLIST_14(x) \
  84. IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
  85. IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
  86. IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
  87. IRQ(x,c), IRQ(x,d)
  88. void (*interrupt[NR_IRQS])(void) = {
  89. IRQLIST_16(0x0),
  90. #ifdef CONFIG_X86_IO_APIC
  91. IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3),
  92. IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
  93. IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
  94. IRQLIST_16(0xc), IRQLIST_16(0xd)
  95. #ifdef CONFIG_PCI_MSI
  96. , IRQLIST_14(0xe)
  97. #endif
  98. #endif
  99. };
  100. #undef IRQ
  101. #undef IRQLIST_16
  102. #undef IRQLIST_14
  103. /*
  104. * This is the 'legacy' 8259A Programmable Interrupt Controller,
  105. * present in the majority of PC/AT boxes.
  106. * plus some generic x86 specific things if generic specifics makes
  107. * any sense at all.
  108. * this file should become arch/i386/kernel/irq.c when the old irq.c
  109. * moves to arch independent land
  110. */
  111. DEFINE_SPINLOCK(i8259A_lock);
  112. static void end_8259A_irq (unsigned int irq)
  113. {
  114. if (irq > 256) {
  115. char var;
  116. printk("return %p stack %p ti %p\n", __builtin_return_address(0), &var, current->thread_info);
  117. BUG();
  118. }
  119. if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
  120. irq_desc[irq].action)
  121. enable_8259A_irq(irq);
  122. }
  123. #define shutdown_8259A_irq disable_8259A_irq
  124. static void mask_and_ack_8259A(unsigned int);
  125. static unsigned int startup_8259A_irq(unsigned int irq)
  126. {
  127. enable_8259A_irq(irq);
  128. return 0; /* never anything pending */
  129. }
  130. static struct hw_interrupt_type i8259A_irq_type = {
  131. "XT-PIC",
  132. startup_8259A_irq,
  133. shutdown_8259A_irq,
  134. enable_8259A_irq,
  135. disable_8259A_irq,
  136. mask_and_ack_8259A,
  137. end_8259A_irq,
  138. NULL
  139. };
  140. /*
  141. * 8259A PIC functions to handle ISA devices:
  142. */
  143. /*
  144. * This contains the irq mask for both 8259A irq controllers,
  145. */
  146. static unsigned int cached_irq_mask = 0xffff;
  147. #define __byte(x,y) (((unsigned char *)&(y))[x])
  148. #define cached_21 (__byte(0,cached_irq_mask))
  149. #define cached_A1 (__byte(1,cached_irq_mask))
  150. /*
  151. * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
  152. * boards the timer interrupt is not really connected to any IO-APIC pin,
  153. * it's fed to the master 8259A's IR0 line only.
  154. *
  155. * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
  156. * this 'mixed mode' IRQ handling costs nothing because it's only used
  157. * at IRQ setup time.
  158. */
  159. unsigned long io_apic_irqs;
  160. void disable_8259A_irq(unsigned int irq)
  161. {
  162. unsigned int mask = 1 << irq;
  163. unsigned long flags;
  164. spin_lock_irqsave(&i8259A_lock, flags);
  165. cached_irq_mask |= mask;
  166. if (irq & 8)
  167. outb(cached_A1,0xA1);
  168. else
  169. outb(cached_21,0x21);
  170. spin_unlock_irqrestore(&i8259A_lock, flags);
  171. }
  172. void enable_8259A_irq(unsigned int irq)
  173. {
  174. unsigned int mask = ~(1 << irq);
  175. unsigned long flags;
  176. spin_lock_irqsave(&i8259A_lock, flags);
  177. cached_irq_mask &= mask;
  178. if (irq & 8)
  179. outb(cached_A1,0xA1);
  180. else
  181. outb(cached_21,0x21);
  182. spin_unlock_irqrestore(&i8259A_lock, flags);
  183. }
  184. int i8259A_irq_pending(unsigned int irq)
  185. {
  186. unsigned int mask = 1<<irq;
  187. unsigned long flags;
  188. int ret;
  189. spin_lock_irqsave(&i8259A_lock, flags);
  190. if (irq < 8)
  191. ret = inb(0x20) & mask;
  192. else
  193. ret = inb(0xA0) & (mask >> 8);
  194. spin_unlock_irqrestore(&i8259A_lock, flags);
  195. return ret;
  196. }
  197. void make_8259A_irq(unsigned int irq)
  198. {
  199. disable_irq_nosync(irq);
  200. io_apic_irqs &= ~(1<<irq);
  201. irq_desc[irq].handler = &i8259A_irq_type;
  202. enable_irq(irq);
  203. }
  204. /*
  205. * This function assumes to be called rarely. Switching between
  206. * 8259A registers is slow.
  207. * This has to be protected by the irq controller spinlock
  208. * before being called.
  209. */
  210. static inline int i8259A_irq_real(unsigned int irq)
  211. {
  212. int value;
  213. int irqmask = 1<<irq;
  214. if (irq < 8) {
  215. outb(0x0B,0x20); /* ISR register */
  216. value = inb(0x20) & irqmask;
  217. outb(0x0A,0x20); /* back to the IRR register */
  218. return value;
  219. }
  220. outb(0x0B,0xA0); /* ISR register */
  221. value = inb(0xA0) & (irqmask >> 8);
  222. outb(0x0A,0xA0); /* back to the IRR register */
  223. return value;
  224. }
  225. /*
  226. * Careful! The 8259A is a fragile beast, it pretty
  227. * much _has_ to be done exactly like this (mask it
  228. * first, _then_ send the EOI, and the order of EOI
  229. * to the two 8259s is important!
  230. */
  231. static void mask_and_ack_8259A(unsigned int irq)
  232. {
  233. unsigned int irqmask = 1 << irq;
  234. unsigned long flags;
  235. spin_lock_irqsave(&i8259A_lock, flags);
  236. /*
  237. * Lightweight spurious IRQ detection. We do not want
  238. * to overdo spurious IRQ handling - it's usually a sign
  239. * of hardware problems, so we only do the checks we can
  240. * do without slowing down good hardware unnecesserily.
  241. *
  242. * Note that IRQ7 and IRQ15 (the two spurious IRQs
  243. * usually resulting from the 8259A-1|2 PICs) occur
  244. * even if the IRQ is masked in the 8259A. Thus we
  245. * can check spurious 8259A IRQs without doing the
  246. * quite slow i8259A_irq_real() call for every IRQ.
  247. * This does not cover 100% of spurious interrupts,
  248. * but should be enough to warn the user that there
  249. * is something bad going on ...
  250. */
  251. if (cached_irq_mask & irqmask)
  252. goto spurious_8259A_irq;
  253. cached_irq_mask |= irqmask;
  254. handle_real_irq:
  255. if (irq & 8) {
  256. inb(0xA1); /* DUMMY - (do we need this?) */
  257. outb(cached_A1,0xA1);
  258. outb(0x60+(irq&7),0xA0);/* 'Specific EOI' to slave */
  259. outb(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */
  260. } else {
  261. inb(0x21); /* DUMMY - (do we need this?) */
  262. outb(cached_21,0x21);
  263. outb(0x60+irq,0x20); /* 'Specific EOI' to master */
  264. }
  265. spin_unlock_irqrestore(&i8259A_lock, flags);
  266. return;
  267. spurious_8259A_irq:
  268. /*
  269. * this is the slow path - should happen rarely.
  270. */
  271. if (i8259A_irq_real(irq))
  272. /*
  273. * oops, the IRQ _is_ in service according to the
  274. * 8259A - not spurious, go handle it.
  275. */
  276. goto handle_real_irq;
  277. {
  278. static int spurious_irq_mask;
  279. /*
  280. * At this point we can be sure the IRQ is spurious,
  281. * lets ACK and report it. [once per IRQ]
  282. */
  283. if (!(spurious_irq_mask & irqmask)) {
  284. printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
  285. spurious_irq_mask |= irqmask;
  286. }
  287. atomic_inc(&irq_err_count);
  288. /*
  289. * Theoretically we do not have to handle this IRQ,
  290. * but in Linux this does not cause problems and is
  291. * simpler for us.
  292. */
  293. goto handle_real_irq;
  294. }
  295. }
  296. void init_8259A(int auto_eoi)
  297. {
  298. unsigned long flags;
  299. spin_lock_irqsave(&i8259A_lock, flags);
  300. outb(0xff, 0x21); /* mask all of 8259A-1 */
  301. outb(0xff, 0xA1); /* mask all of 8259A-2 */
  302. /*
  303. * outb_p - this has to work on a wide range of PC hardware.
  304. */
  305. outb_p(0x11, 0x20); /* ICW1: select 8259A-1 init */
  306. outb_p(0x20 + 0, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
  307. outb_p(0x04, 0x21); /* 8259A-1 (the master) has a slave on IR2 */
  308. if (auto_eoi)
  309. outb_p(0x03, 0x21); /* master does Auto EOI */
  310. else
  311. outb_p(0x01, 0x21); /* master expects normal EOI */
  312. outb_p(0x11, 0xA0); /* ICW1: select 8259A-2 init */
  313. outb_p(0x20 + 8, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
  314. outb_p(0x02, 0xA1); /* 8259A-2 is a slave on master's IR2 */
  315. outb_p(0x01, 0xA1); /* (slave's support for AEOI in flat mode
  316. is to be investigated) */
  317. if (auto_eoi)
  318. /*
  319. * in AEOI mode we just have to mask the interrupt
  320. * when acking.
  321. */
  322. i8259A_irq_type.ack = disable_8259A_irq;
  323. else
  324. i8259A_irq_type.ack = mask_and_ack_8259A;
  325. udelay(100); /* wait for 8259A to initialize */
  326. outb(cached_21, 0x21); /* restore master IRQ mask */
  327. outb(cached_A1, 0xA1); /* restore slave IRQ mask */
  328. spin_unlock_irqrestore(&i8259A_lock, flags);
  329. }
  330. static char irq_trigger[2];
  331. /**
  332. * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
  333. */
  334. static void restore_ELCR(char *trigger)
  335. {
  336. outb(trigger[0], 0x4d0);
  337. outb(trigger[1], 0x4d1);
  338. }
  339. static void save_ELCR(char *trigger)
  340. {
  341. /* IRQ 0,1,2,8,13 are marked as reserved */
  342. trigger[0] = inb(0x4d0) & 0xF8;
  343. trigger[1] = inb(0x4d1) & 0xDE;
  344. }
  345. static int i8259A_resume(struct sys_device *dev)
  346. {
  347. init_8259A(0);
  348. restore_ELCR(irq_trigger);
  349. return 0;
  350. }
  351. static int i8259A_suspend(struct sys_device *dev, u32 state)
  352. {
  353. save_ELCR(irq_trigger);
  354. return 0;
  355. }
  356. static struct sysdev_class i8259_sysdev_class = {
  357. set_kset_name("i8259"),
  358. .suspend = i8259A_suspend,
  359. .resume = i8259A_resume,
  360. };
  361. static struct sys_device device_i8259A = {
  362. .id = 0,
  363. .cls = &i8259_sysdev_class,
  364. };
  365. static int __init i8259A_init_sysfs(void)
  366. {
  367. int error = sysdev_class_register(&i8259_sysdev_class);
  368. if (!error)
  369. error = sysdev_register(&device_i8259A);
  370. return error;
  371. }
  372. device_initcall(i8259A_init_sysfs);
  373. /*
  374. * IRQ2 is cascade interrupt to second interrupt controller
  375. */
  376. static struct irqaction irq2 = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL};
  377. void __init init_ISA_irqs (void)
  378. {
  379. int i;
  380. #ifdef CONFIG_X86_LOCAL_APIC
  381. init_bsp_APIC();
  382. #endif
  383. init_8259A(0);
  384. for (i = 0; i < NR_IRQS; i++) {
  385. irq_desc[i].status = IRQ_DISABLED;
  386. irq_desc[i].action = NULL;
  387. irq_desc[i].depth = 1;
  388. if (i < 16) {
  389. /*
  390. * 16 old-style INTA-cycle interrupts:
  391. */
  392. irq_desc[i].handler = &i8259A_irq_type;
  393. } else {
  394. /*
  395. * 'high' PCI IRQs filled in on demand
  396. */
  397. irq_desc[i].handler = &no_irq_type;
  398. }
  399. }
  400. }
  401. void apic_timer_interrupt(void);
  402. void spurious_interrupt(void);
  403. void error_interrupt(void);
  404. void reschedule_interrupt(void);
  405. void call_function_interrupt(void);
  406. void invalidate_interrupt(void);
  407. void thermal_interrupt(void);
  408. void i8254_timer_resume(void);
  409. static void setup_timer(void)
  410. {
  411. outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */
  412. udelay(10);
  413. outb_p(LATCH & 0xff , 0x40); /* LSB */
  414. udelay(10);
  415. outb(LATCH >> 8 , 0x40); /* MSB */
  416. }
  417. static int timer_resume(struct sys_device *dev)
  418. {
  419. setup_timer();
  420. return 0;
  421. }
  422. void i8254_timer_resume(void)
  423. {
  424. setup_timer();
  425. }
  426. static struct sysdev_class timer_sysclass = {
  427. set_kset_name("timer"),
  428. .resume = timer_resume,
  429. };
  430. static struct sys_device device_timer = {
  431. .id = 0,
  432. .cls = &timer_sysclass,
  433. };
  434. static int __init init_timer_sysfs(void)
  435. {
  436. int error = sysdev_class_register(&timer_sysclass);
  437. if (!error)
  438. error = sysdev_register(&device_timer);
  439. return error;
  440. }
  441. device_initcall(init_timer_sysfs);
  442. void __init init_IRQ(void)
  443. {
  444. int i;
  445. init_ISA_irqs();
  446. /*
  447. * Cover the whole vector space, no vector can escape
  448. * us. (some of these will be overridden and become
  449. * 'special' SMP interrupts)
  450. */
  451. for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) {
  452. int vector = FIRST_EXTERNAL_VECTOR + i;
  453. if (i >= NR_IRQS)
  454. break;
  455. if (vector != IA32_SYSCALL_VECTOR && vector != KDB_VECTOR) {
  456. set_intr_gate(vector, interrupt[i]);
  457. }
  458. }
  459. #ifdef CONFIG_SMP
  460. /*
  461. * IRQ0 must be given a fixed assignment and initialized,
  462. * because it's used before the IO-APIC is set up.
  463. */
  464. set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
  465. /*
  466. * The reschedule interrupt is a CPU-to-CPU reschedule-helper
  467. * IPI, driven by wakeup.
  468. */
  469. set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
  470. /* IPI for invalidation */
  471. set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
  472. /* IPI for generic function call */
  473. set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
  474. #endif
  475. set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
  476. #ifdef CONFIG_X86_LOCAL_APIC
  477. /* self generated IPI for local APIC timer */
  478. set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
  479. /* IPI vectors for APIC spurious and error interrupts */
  480. set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
  481. set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
  482. #endif
  483. /*
  484. * Set the clock to HZ Hz, we already have a valid
  485. * vector now:
  486. */
  487. setup_timer();
  488. if (!acpi_ioapic)
  489. setup_irq(2, &irq2);
  490. }