/arch/x86_64/kernel/apic.c

https://bitbucket.org/evzijst/gittest · C · 1088 lines · 617 code · 149 blank · 322 comment · 92 complexity · 9065122ad47c925daf208ef4cb5faac9 MD5 · raw file

  1. /*
  2. * Local APIC handling, local APIC timers
  3. *
  4. * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
  5. *
  6. * Fixes
  7. * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
  8. * thanks to Eric Gilmore
  9. * and Rolf G. Tews
  10. * for testing these extensively.
  11. * Maciej W. Rozycki : Various updates and fixes.
  12. * Mikael Pettersson : Power Management for UP-APIC.
  13. * Pavel Machek and
  14. * Mikael Pettersson : PM converted to driver model.
  15. */
  16. #include <linux/config.h>
  17. #include <linux/init.h>
  18. #include <linux/mm.h>
  19. #include <linux/irq.h>
  20. #include <linux/delay.h>
  21. #include <linux/bootmem.h>
  22. #include <linux/smp_lock.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/mc146818rtc.h>
  25. #include <linux/kernel_stat.h>
  26. #include <linux/sysdev.h>
  27. #include <asm/atomic.h>
  28. #include <asm/smp.h>
  29. #include <asm/mtrr.h>
  30. #include <asm/mpspec.h>
  31. #include <asm/pgalloc.h>
  32. #include <asm/mach_apic.h>
  33. int apic_verbosity;
  34. int disable_apic_timer __initdata;
  35. /* Using APIC to generate smp_local_timer_interrupt? */
  36. int using_apic_timer = 0;
  37. static DEFINE_PER_CPU(int, prof_multiplier) = 1;
  38. static DEFINE_PER_CPU(int, prof_old_multiplier) = 1;
  39. static DEFINE_PER_CPU(int, prof_counter) = 1;
  40. static void apic_pm_activate(void);
  41. void enable_NMI_through_LVT0 (void * dummy)
  42. {
  43. unsigned int v, ver;
  44. ver = apic_read(APIC_LVR);
  45. ver = GET_APIC_VERSION(ver);
  46. v = APIC_DM_NMI; /* unmask and set to NMI */
  47. apic_write_around(APIC_LVT0, v);
  48. }
  49. int get_maxlvt(void)
  50. {
  51. unsigned int v, ver, maxlvt;
  52. v = apic_read(APIC_LVR);
  53. ver = GET_APIC_VERSION(v);
  54. maxlvt = GET_APIC_MAXLVT(v);
  55. return maxlvt;
  56. }
  57. void clear_local_APIC(void)
  58. {
  59. int maxlvt;
  60. unsigned int v;
  61. maxlvt = get_maxlvt();
  62. /*
  63. * Masking an LVT entry on a P6 can trigger a local APIC error
  64. * if the vector is zero. Mask LVTERR first to prevent this.
  65. */
  66. if (maxlvt >= 3) {
  67. v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
  68. apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
  69. }
  70. /*
  71. * Careful: we have to set masks only first to deassert
  72. * any level-triggered sources.
  73. */
  74. v = apic_read(APIC_LVTT);
  75. apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
  76. v = apic_read(APIC_LVT0);
  77. apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
  78. v = apic_read(APIC_LVT1);
  79. apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
  80. if (maxlvt >= 4) {
  81. v = apic_read(APIC_LVTPC);
  82. apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
  83. }
  84. /*
  85. * Clean APIC state for other OSs:
  86. */
  87. apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
  88. apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
  89. apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
  90. if (maxlvt >= 3)
  91. apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
  92. if (maxlvt >= 4)
  93. apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
  94. v = GET_APIC_VERSION(apic_read(APIC_LVR));
  95. if (APIC_INTEGRATED(v)) { /* !82489DX */
  96. if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */
  97. apic_write(APIC_ESR, 0);
  98. apic_read(APIC_ESR);
  99. }
  100. }
  101. void __init connect_bsp_APIC(void)
  102. {
  103. if (pic_mode) {
  104. /*
  105. * Do not trust the local APIC being empty at bootup.
  106. */
  107. clear_local_APIC();
  108. /*
  109. * PIC mode, enable APIC mode in the IMCR, i.e.
  110. * connect BSP's local APIC to INT and NMI lines.
  111. */
  112. apic_printk(APIC_VERBOSE, "leaving PIC mode, enabling APIC mode.\n");
  113. outb(0x70, 0x22);
  114. outb(0x01, 0x23);
  115. }
  116. }
  117. void disconnect_bsp_APIC(void)
  118. {
  119. if (pic_mode) {
  120. /*
  121. * Put the board back into PIC mode (has an effect
  122. * only on certain older boards). Note that APIC
  123. * interrupts, including IPIs, won't work beyond
  124. * this point! The only exception are INIT IPIs.
  125. */
  126. apic_printk(APIC_QUIET, "disabling APIC mode, entering PIC mode.\n");
  127. outb(0x70, 0x22);
  128. outb(0x00, 0x23);
  129. }
  130. }
  131. void disable_local_APIC(void)
  132. {
  133. unsigned int value;
  134. clear_local_APIC();
  135. /*
  136. * Disable APIC (implies clearing of registers
  137. * for 82489DX!).
  138. */
  139. value = apic_read(APIC_SPIV);
  140. value &= ~APIC_SPIV_APIC_ENABLED;
  141. apic_write_around(APIC_SPIV, value);
  142. }
  143. /*
  144. * This is to verify that we're looking at a real local APIC.
  145. * Check these against your board if the CPUs aren't getting
  146. * started for no apparent reason.
  147. */
  148. int __init verify_local_APIC(void)
  149. {
  150. unsigned int reg0, reg1;
  151. /*
  152. * The version register is read-only in a real APIC.
  153. */
  154. reg0 = apic_read(APIC_LVR);
  155. apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
  156. apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
  157. reg1 = apic_read(APIC_LVR);
  158. apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
  159. /*
  160. * The two version reads above should print the same
  161. * numbers. If the second one is different, then we
  162. * poke at a non-APIC.
  163. */
  164. if (reg1 != reg0)
  165. return 0;
  166. /*
  167. * Check if the version looks reasonably.
  168. */
  169. reg1 = GET_APIC_VERSION(reg0);
  170. if (reg1 == 0x00 || reg1 == 0xff)
  171. return 0;
  172. reg1 = get_maxlvt();
  173. if (reg1 < 0x02 || reg1 == 0xff)
  174. return 0;
  175. /*
  176. * The ID register is read/write in a real APIC.
  177. */
  178. reg0 = apic_read(APIC_ID);
  179. apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
  180. apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
  181. reg1 = apic_read(APIC_ID);
  182. apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
  183. apic_write(APIC_ID, reg0);
  184. if (reg1 != (reg0 ^ APIC_ID_MASK))
  185. return 0;
  186. /*
  187. * The next two are just to see if we have sane values.
  188. * They're only really relevant if we're in Virtual Wire
  189. * compatibility mode, but most boxes are anymore.
  190. */
  191. reg0 = apic_read(APIC_LVT0);
  192. apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0);
  193. reg1 = apic_read(APIC_LVT1);
  194. apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
  195. return 1;
  196. }
  197. void __init sync_Arb_IDs(void)
  198. {
  199. /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
  200. unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
  201. if (ver >= 0x14) /* P4 or higher */
  202. return;
  203. /*
  204. * Wait for idle.
  205. */
  206. apic_wait_icr_idle();
  207. apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
  208. apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
  209. | APIC_DM_INIT);
  210. }
  211. extern void __error_in_apic_c (void);
  212. /*
  213. * An initial setup of the virtual wire mode.
  214. */
  215. void __init init_bsp_APIC(void)
  216. {
  217. unsigned int value, ver;
  218. /*
  219. * Don't do the setup now if we have a SMP BIOS as the
  220. * through-I/O-APIC virtual wire mode might be active.
  221. */
  222. if (smp_found_config || !cpu_has_apic)
  223. return;
  224. value = apic_read(APIC_LVR);
  225. ver = GET_APIC_VERSION(value);
  226. /*
  227. * Do not trust the local APIC being empty at bootup.
  228. */
  229. clear_local_APIC();
  230. /*
  231. * Enable APIC.
  232. */
  233. value = apic_read(APIC_SPIV);
  234. value &= ~APIC_VECTOR_MASK;
  235. value |= APIC_SPIV_APIC_ENABLED;
  236. value |= APIC_SPIV_FOCUS_DISABLED;
  237. value |= SPURIOUS_APIC_VECTOR;
  238. apic_write_around(APIC_SPIV, value);
  239. /*
  240. * Set up the virtual wire mode.
  241. */
  242. apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
  243. value = APIC_DM_NMI;
  244. if (!APIC_INTEGRATED(ver)) /* 82489DX */
  245. value |= APIC_LVT_LEVEL_TRIGGER;
  246. apic_write_around(APIC_LVT1, value);
  247. }
  248. void __init setup_local_APIC (void)
  249. {
  250. unsigned int value, ver, maxlvt;
  251. /* Pound the ESR really hard over the head with a big hammer - mbligh */
  252. if (esr_disable) {
  253. apic_write(APIC_ESR, 0);
  254. apic_write(APIC_ESR, 0);
  255. apic_write(APIC_ESR, 0);
  256. apic_write(APIC_ESR, 0);
  257. }
  258. value = apic_read(APIC_LVR);
  259. ver = GET_APIC_VERSION(value);
  260. if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
  261. __error_in_apic_c();
  262. /*
  263. * Double-check whether this APIC is really registered.
  264. * This is meaningless in clustered apic mode, so we skip it.
  265. */
  266. if (!apic_id_registered())
  267. BUG();
  268. /*
  269. * Intel recommends to set DFR, LDR and TPR before enabling
  270. * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
  271. * document number 292116). So here it goes...
  272. */
  273. init_apic_ldr();
  274. /*
  275. * Set Task Priority to 'accept all'. We never change this
  276. * later on.
  277. */
  278. value = apic_read(APIC_TASKPRI);
  279. value &= ~APIC_TPRI_MASK;
  280. apic_write_around(APIC_TASKPRI, value);
  281. /*
  282. * Now that we are all set up, enable the APIC
  283. */
  284. value = apic_read(APIC_SPIV);
  285. value &= ~APIC_VECTOR_MASK;
  286. /*
  287. * Enable APIC
  288. */
  289. value |= APIC_SPIV_APIC_ENABLED;
  290. /*
  291. * Some unknown Intel IO/APIC (or APIC) errata is biting us with
  292. * certain networking cards. If high frequency interrupts are
  293. * happening on a particular IOAPIC pin, plus the IOAPIC routing
  294. * entry is masked/unmasked at a high rate as well then sooner or
  295. * later IOAPIC line gets 'stuck', no more interrupts are received
  296. * from the device. If focus CPU is disabled then the hang goes
  297. * away, oh well :-(
  298. *
  299. * [ This bug can be reproduced easily with a level-triggered
  300. * PCI Ne2000 networking cards and PII/PIII processors, dual
  301. * BX chipset. ]
  302. */
  303. /*
  304. * Actually disabling the focus CPU check just makes the hang less
  305. * frequent as it makes the interrupt distributon model be more
  306. * like LRU than MRU (the short-term load is more even across CPUs).
  307. * See also the comment in end_level_ioapic_irq(). --macro
  308. */
  309. #if 1
  310. /* Enable focus processor (bit==0) */
  311. value &= ~APIC_SPIV_FOCUS_DISABLED;
  312. #else
  313. /* Disable focus processor (bit==1) */
  314. value |= APIC_SPIV_FOCUS_DISABLED;
  315. #endif
  316. /*
  317. * Set spurious IRQ vector
  318. */
  319. value |= SPURIOUS_APIC_VECTOR;
  320. apic_write_around(APIC_SPIV, value);
  321. /*
  322. * Set up LVT0, LVT1:
  323. *
  324. * set up through-local-APIC on the BP's LINT0. This is not
  325. * strictly necessary in pure symmetric-IO mode, but sometimes
  326. * we delegate interrupts to the 8259A.
  327. */
  328. /*
  329. * TODO: set up through-local-APIC from through-I/O-APIC? --macro
  330. */
  331. value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
  332. if (!smp_processor_id() && (pic_mode || !value)) {
  333. value = APIC_DM_EXTINT;
  334. apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id());
  335. } else {
  336. value = APIC_DM_EXTINT | APIC_LVT_MASKED;
  337. apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id());
  338. }
  339. apic_write_around(APIC_LVT0, value);
  340. /*
  341. * only the BP should see the LINT1 NMI signal, obviously.
  342. */
  343. if (!smp_processor_id())
  344. value = APIC_DM_NMI;
  345. else
  346. value = APIC_DM_NMI | APIC_LVT_MASKED;
  347. if (!APIC_INTEGRATED(ver)) /* 82489DX */
  348. value |= APIC_LVT_LEVEL_TRIGGER;
  349. apic_write_around(APIC_LVT1, value);
  350. if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */
  351. unsigned oldvalue;
  352. maxlvt = get_maxlvt();
  353. if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
  354. apic_write(APIC_ESR, 0);
  355. oldvalue = apic_read(APIC_ESR);
  356. value = ERROR_APIC_VECTOR; // enables sending errors
  357. apic_write_around(APIC_LVTERR, value);
  358. /*
  359. * spec says clear errors after enabling vector.
  360. */
  361. if (maxlvt > 3)
  362. apic_write(APIC_ESR, 0);
  363. value = apic_read(APIC_ESR);
  364. if (value != oldvalue)
  365. apic_printk(APIC_VERBOSE,
  366. "ESR value after enabling vector: %08x, after %08x\n",
  367. oldvalue, value);
  368. } else {
  369. if (esr_disable)
  370. /*
  371. * Something untraceble is creating bad interrupts on
  372. * secondary quads ... for the moment, just leave the
  373. * ESR disabled - we can't do anything useful with the
  374. * errors anyway - mbligh
  375. */
  376. apic_printk(APIC_DEBUG, "Leaving ESR disabled.\n");
  377. else
  378. apic_printk(APIC_DEBUG, "No ESR for 82489DX.\n");
  379. }
  380. nmi_watchdog_default();
  381. if (nmi_watchdog == NMI_LOCAL_APIC)
  382. setup_apic_nmi_watchdog();
  383. apic_pm_activate();
  384. }
  385. #ifdef CONFIG_PM
  386. static struct {
  387. /* 'active' is true if the local APIC was enabled by us and
  388. not the BIOS; this signifies that we are also responsible
  389. for disabling it before entering apm/acpi suspend */
  390. int active;
  391. /* r/w apic fields */
  392. unsigned int apic_id;
  393. unsigned int apic_taskpri;
  394. unsigned int apic_ldr;
  395. unsigned int apic_dfr;
  396. unsigned int apic_spiv;
  397. unsigned int apic_lvtt;
  398. unsigned int apic_lvtpc;
  399. unsigned int apic_lvt0;
  400. unsigned int apic_lvt1;
  401. unsigned int apic_lvterr;
  402. unsigned int apic_tmict;
  403. unsigned int apic_tdcr;
  404. unsigned int apic_thmr;
  405. } apic_pm_state;
  406. static int lapic_suspend(struct sys_device *dev, u32 state)
  407. {
  408. unsigned long flags;
  409. if (!apic_pm_state.active)
  410. return 0;
  411. apic_pm_state.apic_id = apic_read(APIC_ID);
  412. apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
  413. apic_pm_state.apic_ldr = apic_read(APIC_LDR);
  414. apic_pm_state.apic_dfr = apic_read(APIC_DFR);
  415. apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
  416. apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
  417. apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
  418. apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
  419. apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
  420. apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
  421. apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
  422. apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
  423. apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
  424. local_save_flags(flags);
  425. local_irq_disable();
  426. disable_local_APIC();
  427. local_irq_restore(flags);
  428. return 0;
  429. }
  430. static int lapic_resume(struct sys_device *dev)
  431. {
  432. unsigned int l, h;
  433. unsigned long flags;
  434. if (!apic_pm_state.active)
  435. return 0;
  436. /* XXX: Pavel needs this for S3 resume, but can't explain why */
  437. set_fixmap_nocache(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE);
  438. local_irq_save(flags);
  439. rdmsr(MSR_IA32_APICBASE, l, h);
  440. l &= ~MSR_IA32_APICBASE_BASE;
  441. l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
  442. wrmsr(MSR_IA32_APICBASE, l, h);
  443. apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
  444. apic_write(APIC_ID, apic_pm_state.apic_id);
  445. apic_write(APIC_DFR, apic_pm_state.apic_dfr);
  446. apic_write(APIC_LDR, apic_pm_state.apic_ldr);
  447. apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
  448. apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
  449. apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
  450. apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
  451. apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
  452. apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
  453. apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
  454. apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
  455. apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
  456. apic_write(APIC_ESR, 0);
  457. apic_read(APIC_ESR);
  458. apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
  459. apic_write(APIC_ESR, 0);
  460. apic_read(APIC_ESR);
  461. local_irq_restore(flags);
  462. return 0;
  463. }
  464. static struct sysdev_class lapic_sysclass = {
  465. set_kset_name("lapic"),
  466. .resume = lapic_resume,
  467. .suspend = lapic_suspend,
  468. };
  469. static struct sys_device device_lapic = {
  470. .id = 0,
  471. .cls = &lapic_sysclass,
  472. };
  473. static void __init apic_pm_activate(void)
  474. {
  475. apic_pm_state.active = 1;
  476. }
  477. static int __init init_lapic_sysfs(void)
  478. {
  479. int error;
  480. if (!cpu_has_apic)
  481. return 0;
  482. /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
  483. error = sysdev_class_register(&lapic_sysclass);
  484. if (!error)
  485. error = sysdev_register(&device_lapic);
  486. return error;
  487. }
  488. device_initcall(init_lapic_sysfs);
  489. #else /* CONFIG_PM */
  490. static void apic_pm_activate(void) { }
  491. #endif /* CONFIG_PM */
  492. static int __init apic_set_verbosity(char *str)
  493. {
  494. if (strcmp("debug", str) == 0)
  495. apic_verbosity = APIC_DEBUG;
  496. else if (strcmp("verbose", str) == 0)
  497. apic_verbosity = APIC_VERBOSE;
  498. else
  499. printk(KERN_WARNING "APIC Verbosity level %s not recognised"
  500. " use apic=verbose or apic=debug", str);
  501. return 0;
  502. }
  503. __setup("apic=", apic_set_verbosity);
  504. /*
  505. * Detect and enable local APICs on non-SMP boards.
  506. * Original code written by Keir Fraser.
  507. * On AMD64 we trust the BIOS - if it says no APIC it is likely
  508. * not correctly set up (usually the APIC timer won't work etc.)
  509. */
  510. static int __init detect_init_APIC (void)
  511. {
  512. if (!cpu_has_apic) {
  513. printk(KERN_INFO "No local APIC present\n");
  514. return -1;
  515. }
  516. mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
  517. boot_cpu_id = 0;
  518. return 0;
  519. }
  520. void __init init_apic_mappings(void)
  521. {
  522. unsigned long apic_phys;
  523. /*
  524. * If no local APIC can be found then set up a fake all
  525. * zeroes page to simulate the local APIC and another
  526. * one for the IO-APIC.
  527. */
  528. if (!smp_found_config && detect_init_APIC()) {
  529. apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
  530. apic_phys = __pa(apic_phys);
  531. } else
  532. apic_phys = mp_lapic_addr;
  533. set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
  534. apic_printk(APIC_VERBOSE,"mapped APIC to %16lx (%16lx)\n", APIC_BASE, apic_phys);
  535. /*
  536. * Fetch the APIC ID of the BSP in case we have a
  537. * default configuration (or the MP table is broken).
  538. */
  539. if (boot_cpu_id == -1U)
  540. boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
  541. #ifdef CONFIG_X86_IO_APIC
  542. {
  543. unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
  544. int i;
  545. for (i = 0; i < nr_ioapics; i++) {
  546. if (smp_found_config) {
  547. ioapic_phys = mp_ioapics[i].mpc_apicaddr;
  548. } else {
  549. ioapic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
  550. ioapic_phys = __pa(ioapic_phys);
  551. }
  552. set_fixmap_nocache(idx, ioapic_phys);
  553. apic_printk(APIC_VERBOSE,"mapped IOAPIC to %016lx (%016lx)\n",
  554. __fix_to_virt(idx), ioapic_phys);
  555. idx++;
  556. }
  557. }
  558. #endif
  559. }
  560. /*
  561. * This function sets up the local APIC timer, with a timeout of
  562. * 'clocks' APIC bus clock. During calibration we actually call
  563. * this function twice on the boot CPU, once with a bogus timeout
  564. * value, second time for real. The other (noncalibrating) CPUs
  565. * call this function only once, with the real, calibrated value.
  566. *
  567. * We do reads before writes even if unnecessary, to get around the
  568. * P5 APIC double write bug.
  569. */
  570. #define APIC_DIVISOR 16
  571. static void __setup_APIC_LVTT(unsigned int clocks)
  572. {
  573. unsigned int lvtt_value, tmp_value, ver;
  574. ver = GET_APIC_VERSION(apic_read(APIC_LVR));
  575. lvtt_value = APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR;
  576. if (!APIC_INTEGRATED(ver))
  577. lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
  578. apic_write_around(APIC_LVTT, lvtt_value);
  579. /*
  580. * Divide PICLK by 16
  581. */
  582. tmp_value = apic_read(APIC_TDCR);
  583. apic_write_around(APIC_TDCR, (tmp_value
  584. & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
  585. | APIC_TDR_DIV_16);
  586. apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
  587. }
  588. static void setup_APIC_timer(unsigned int clocks)
  589. {
  590. unsigned long flags;
  591. local_irq_save(flags);
  592. /* For some reasons this doesn't work on Simics, so fake it for now */
  593. if (!strstr(boot_cpu_data.x86_model_id, "Screwdriver")) {
  594. __setup_APIC_LVTT(clocks);
  595. return;
  596. }
  597. /* wait for irq slice */
  598. if (vxtime.hpet_address) {
  599. int trigger = hpet_readl(HPET_T0_CMP);
  600. while (hpet_readl(HPET_COUNTER) >= trigger)
  601. /* do nothing */ ;
  602. while (hpet_readl(HPET_COUNTER) < trigger)
  603. /* do nothing */ ;
  604. } else {
  605. int c1, c2;
  606. outb_p(0x00, 0x43);
  607. c2 = inb_p(0x40);
  608. c2 |= inb_p(0x40) << 8;
  609. do {
  610. c1 = c2;
  611. outb_p(0x00, 0x43);
  612. c2 = inb_p(0x40);
  613. c2 |= inb_p(0x40) << 8;
  614. } while (c2 - c1 < 300);
  615. }
  616. __setup_APIC_LVTT(clocks);
  617. local_irq_restore(flags);
  618. }
  619. /*
  620. * In this function we calibrate APIC bus clocks to the external
  621. * timer. Unfortunately we cannot use jiffies and the timer irq
  622. * to calibrate, since some later bootup code depends on getting
  623. * the first irq? Ugh.
  624. *
  625. * We want to do the calibration only once since we
  626. * want to have local timer irqs syncron. CPUs connected
  627. * by the same APIC bus have the very same bus frequency.
  628. * And we want to have irqs off anyways, no accidental
  629. * APIC irq that way.
  630. */
  631. #define TICK_COUNT 100000000
  632. static int __init calibrate_APIC_clock(void)
  633. {
  634. int apic, apic_start, tsc, tsc_start;
  635. int result;
  636. /*
  637. * Put whatever arbitrary (but long enough) timeout
  638. * value into the APIC clock, we just want to get the
  639. * counter running for calibration.
  640. */
  641. __setup_APIC_LVTT(1000000000);
  642. apic_start = apic_read(APIC_TMCCT);
  643. rdtscl(tsc_start);
  644. do {
  645. apic = apic_read(APIC_TMCCT);
  646. rdtscl(tsc);
  647. } while ((tsc - tsc_start) < TICK_COUNT && (apic - apic_start) < TICK_COUNT);
  648. result = (apic_start - apic) * 1000L * cpu_khz / (tsc - tsc_start);
  649. printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
  650. result / 1000 / 1000, result / 1000 % 1000);
  651. return result * APIC_DIVISOR / HZ;
  652. }
  653. static unsigned int calibration_result;
  654. void __init setup_boot_APIC_clock (void)
  655. {
  656. if (disable_apic_timer) {
  657. printk(KERN_INFO "Disabling APIC timer\n");
  658. return;
  659. }
  660. printk(KERN_INFO "Using local APIC timer interrupts.\n");
  661. using_apic_timer = 1;
  662. local_irq_disable();
  663. calibration_result = calibrate_APIC_clock();
  664. /*
  665. * Now set up the timer for real.
  666. */
  667. setup_APIC_timer(calibration_result);
  668. local_irq_enable();
  669. }
  670. void __init setup_secondary_APIC_clock(void)
  671. {
  672. local_irq_disable(); /* FIXME: Do we need this? --RR */
  673. setup_APIC_timer(calibration_result);
  674. local_irq_enable();
  675. }
  676. void __init disable_APIC_timer(void)
  677. {
  678. if (using_apic_timer) {
  679. unsigned long v;
  680. v = apic_read(APIC_LVTT);
  681. apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
  682. }
  683. }
  684. void enable_APIC_timer(void)
  685. {
  686. if (using_apic_timer) {
  687. unsigned long v;
  688. v = apic_read(APIC_LVTT);
  689. apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED);
  690. }
  691. }
  692. /*
  693. * the frequency of the profiling timer can be changed
  694. * by writing a multiplier value into /proc/profile.
  695. */
  696. int setup_profiling_timer(unsigned int multiplier)
  697. {
  698. int i;
  699. /*
  700. * Sanity check. [at least 500 APIC cycles should be
  701. * between APIC interrupts as a rule of thumb, to avoid
  702. * irqs flooding us]
  703. */
  704. if ( (!multiplier) || (calibration_result/multiplier < 500))
  705. return -EINVAL;
  706. /*
  707. * Set the new multiplier for each CPU. CPUs don't start using the
  708. * new values until the next timer interrupt in which they do process
  709. * accounting. At that time they also adjust their APIC timers
  710. * accordingly.
  711. */
  712. for (i = 0; i < NR_CPUS; ++i)
  713. per_cpu(prof_multiplier, i) = multiplier;
  714. return 0;
  715. }
  716. #undef APIC_DIVISOR
  717. /*
  718. * Local timer interrupt handler. It does both profiling and
  719. * process statistics/rescheduling.
  720. *
  721. * We do profiling in every local tick, statistics/rescheduling
  722. * happen only every 'profiling multiplier' ticks. The default
  723. * multiplier is 1 and it can be changed by writing the new multiplier
  724. * value into /proc/profile.
  725. */
  726. void smp_local_timer_interrupt(struct pt_regs *regs)
  727. {
  728. int cpu = smp_processor_id();
  729. profile_tick(CPU_PROFILING, regs);
  730. if (--per_cpu(prof_counter, cpu) <= 0) {
  731. /*
  732. * The multiplier may have changed since the last time we got
  733. * to this point as a result of the user writing to
  734. * /proc/profile. In this case we need to adjust the APIC
  735. * timer accordingly.
  736. *
  737. * Interrupts are already masked off at this point.
  738. */
  739. per_cpu(prof_counter, cpu) = per_cpu(prof_multiplier, cpu);
  740. if (per_cpu(prof_counter, cpu) !=
  741. per_cpu(prof_old_multiplier, cpu)) {
  742. __setup_APIC_LVTT(calibration_result/
  743. per_cpu(prof_counter, cpu));
  744. per_cpu(prof_old_multiplier, cpu) =
  745. per_cpu(prof_counter, cpu);
  746. }
  747. #ifdef CONFIG_SMP
  748. update_process_times(user_mode(regs));
  749. #endif
  750. }
  751. /*
  752. * We take the 'long' return path, and there every subsystem
  753. * grabs the appropriate locks (kernel lock/ irq lock).
  754. *
  755. * we might want to decouple profiling from the 'long path',
  756. * and do the profiling totally in assembly.
  757. *
  758. * Currently this isn't too much of an issue (performance wise),
  759. * we can take more than 100K local irqs per second on a 100 MHz P5.
  760. */
  761. }
  762. /*
  763. * Local APIC timer interrupt. This is the most natural way for doing
  764. * local interrupts, but local timer interrupts can be emulated by
  765. * broadcast interrupts too. [in case the hw doesn't support APIC timers]
  766. *
  767. * [ if a single-CPU system runs an SMP kernel then we call the local
  768. * interrupt as well. Thus we cannot inline the local irq ... ]
  769. */
  770. void smp_apic_timer_interrupt(struct pt_regs *regs)
  771. {
  772. /*
  773. * the NMI deadlock-detector uses this.
  774. */
  775. add_pda(apic_timer_irqs, 1);
  776. /*
  777. * NOTE! We'd better ACK the irq immediately,
  778. * because timer handling can be slow.
  779. */
  780. ack_APIC_irq();
  781. /*
  782. * update_process_times() expects us to have done irq_enter().
  783. * Besides, if we don't timer interrupts ignore the global
  784. * interrupt lock, which is the WrongThing (tm) to do.
  785. */
  786. irq_enter();
  787. smp_local_timer_interrupt(regs);
  788. irq_exit();
  789. }
  790. /*
  791. * oem_force_hpet_timer -- force HPET mode for some boxes.
  792. *
  793. * Thus far, the major user of this is IBM's Summit2 series:
  794. *
  795. * Clustered boxes may have unsynced TSC problems if they are
  796. * multi-chassis. Use available data to take a good guess.
  797. * If in doubt, go HPET.
  798. */
  799. __init int oem_force_hpet_timer(void)
  800. {
  801. int i, clusters, zeros;
  802. unsigned id;
  803. DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
  804. bitmap_empty(clustermap, NUM_APIC_CLUSTERS);
  805. for (i = 0; i < NR_CPUS; i++) {
  806. id = bios_cpu_apicid[i];
  807. if (id != BAD_APICID)
  808. __set_bit(APIC_CLUSTERID(id), clustermap);
  809. }
  810. /* Problem: Partially populated chassis may not have CPUs in some of
  811. * the APIC clusters they have been allocated. Only present CPUs have
  812. * bios_cpu_apicid entries, thus causing zeroes in the bitmap. Since
  813. * clusters are allocated sequentially, count zeros only if they are
  814. * bounded by ones.
  815. */
  816. clusters = 0;
  817. zeros = 0;
  818. for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
  819. if (test_bit(i, clustermap)) {
  820. clusters += 1 + zeros;
  821. zeros = 0;
  822. } else
  823. ++zeros;
  824. }
  825. /*
  826. * If clusters > 2, then should be multi-chassis. Return 1 for HPET.
  827. * Else return 0 to use TSC.
  828. * May have to revisit this when multi-core + hyperthreaded CPUs come
  829. * out, but AFAIK this will work even for them.
  830. */
  831. return (clusters > 2);
  832. }
  833. /*
  834. * This interrupt should _never_ happen with our APIC/SMP architecture
  835. */
  836. asmlinkage void smp_spurious_interrupt(void)
  837. {
  838. unsigned int v;
  839. irq_enter();
  840. /*
  841. * Check if this really is a spurious interrupt and ACK it
  842. * if it is a vectored one. Just in case...
  843. * Spurious interrupts should not be ACKed.
  844. */
  845. v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
  846. if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
  847. ack_APIC_irq();
  848. #if 0
  849. static unsigned long last_warning;
  850. static unsigned long skipped;
  851. /* see sw-dev-man vol 3, chapter 7.4.13.5 */
  852. if (time_before(last_warning+30*HZ,jiffies)) {
  853. printk(KERN_INFO "spurious APIC interrupt on CPU#%d, %ld skipped.\n",
  854. smp_processor_id(), skipped);
  855. last_warning = jiffies;
  856. skipped = 0;
  857. } else {
  858. skipped++;
  859. }
  860. #endif
  861. irq_exit();
  862. }
  863. /*
  864. * This interrupt should never happen with our APIC/SMP architecture
  865. */
  866. asmlinkage void smp_error_interrupt(void)
  867. {
  868. unsigned int v, v1;
  869. irq_enter();
  870. /* First tickle the hardware, only then report what went on. -- REW */
  871. v = apic_read(APIC_ESR);
  872. apic_write(APIC_ESR, 0);
  873. v1 = apic_read(APIC_ESR);
  874. ack_APIC_irq();
  875. atomic_inc(&irq_err_count);
  876. /* Here is what the APIC error bits mean:
  877. 0: Send CS error
  878. 1: Receive CS error
  879. 2: Send accept error
  880. 3: Receive accept error
  881. 4: Reserved
  882. 5: Send illegal vector
  883. 6: Received illegal vector
  884. 7: Illegal register address
  885. */
  886. printk (KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
  887. smp_processor_id(), v , v1);
  888. irq_exit();
  889. }
  890. int disable_apic;
  891. /*
  892. * This initializes the IO-APIC and APIC hardware if this is
  893. * a UP kernel.
  894. */
  895. int __init APIC_init_uniprocessor (void)
  896. {
  897. if (disable_apic) {
  898. printk(KERN_INFO "Apic disabled\n");
  899. return -1;
  900. }
  901. if (!cpu_has_apic) {
  902. disable_apic = 1;
  903. printk(KERN_INFO "Apic disabled by BIOS\n");
  904. return -1;
  905. }
  906. verify_local_APIC();
  907. connect_bsp_APIC();
  908. phys_cpu_present_map = physid_mask_of_physid(0);
  909. apic_write_around(APIC_ID, boot_cpu_id);
  910. setup_local_APIC();
  911. #ifdef CONFIG_X86_IO_APIC
  912. if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
  913. setup_IO_APIC();
  914. else
  915. nr_ioapics = 0;
  916. #endif
  917. setup_boot_APIC_clock();
  918. return 0;
  919. }
  920. static __init int setup_disableapic(char *str)
  921. {
  922. disable_apic = 1;
  923. return 0;
  924. }
  925. static __init int setup_nolapic(char *str)
  926. {
  927. disable_apic = 1;
  928. return 0;
  929. }
  930. static __init int setup_noapictimer(char *str)
  931. {
  932. disable_apic_timer = 1;
  933. return 0;
  934. }
  935. /* dummy parsing: see setup.c */
  936. __setup("disableapic", setup_disableapic);
  937. __setup("nolapic", setup_nolapic); /* same as disableapic, for compatibility */
  938. __setup("noapictimer", setup_noapictimer);
  939. /* no "lapic" flag - we only use the lapic when the BIOS tells us so. */