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/arch/x86_64/kernel/apic.c

https://bitbucket.org/evzijst/gittest
C | 1088 lines | 617 code | 149 blank | 322 comment | 92 complexity | 9065122ad47c925daf208ef4cb5faac9 MD5 | raw file
   1/*
   2 *	Local APIC handling, local APIC timers
   3 *
   4 *	(c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
   5 *
   6 *	Fixes
   7 *	Maciej W. Rozycki	:	Bits for genuine 82489DX APICs;
   8 *					thanks to Eric Gilmore
   9 *					and Rolf G. Tews
  10 *					for testing these extensively.
  11 *	Maciej W. Rozycki	:	Various updates and fixes.
  12 *	Mikael Pettersson	:	Power Management for UP-APIC.
  13 *	Pavel Machek and
  14 *	Mikael Pettersson	:	PM converted to driver model.
  15 */
  16
  17#include <linux/config.h>
  18#include <linux/init.h>
  19
  20#include <linux/mm.h>
  21#include <linux/irq.h>
  22#include <linux/delay.h>
  23#include <linux/bootmem.h>
  24#include <linux/smp_lock.h>
  25#include <linux/interrupt.h>
  26#include <linux/mc146818rtc.h>
  27#include <linux/kernel_stat.h>
  28#include <linux/sysdev.h>
  29
  30#include <asm/atomic.h>
  31#include <asm/smp.h>
  32#include <asm/mtrr.h>
  33#include <asm/mpspec.h>
  34#include <asm/pgalloc.h>
  35#include <asm/mach_apic.h>
  36
  37int apic_verbosity;
  38
  39int disable_apic_timer __initdata;
  40
  41/* Using APIC to generate smp_local_timer_interrupt? */
  42int using_apic_timer = 0;
  43
  44static DEFINE_PER_CPU(int, prof_multiplier) = 1;
  45static DEFINE_PER_CPU(int, prof_old_multiplier) = 1;
  46static DEFINE_PER_CPU(int, prof_counter) = 1;
  47
  48static void apic_pm_activate(void);
  49
  50void enable_NMI_through_LVT0 (void * dummy)
  51{
  52	unsigned int v, ver;
  53	
  54	ver = apic_read(APIC_LVR);
  55	ver = GET_APIC_VERSION(ver);
  56	v = APIC_DM_NMI;                        /* unmask and set to NMI */
  57	apic_write_around(APIC_LVT0, v);
  58}
  59
  60int get_maxlvt(void)
  61{
  62	unsigned int v, ver, maxlvt;
  63
  64	v = apic_read(APIC_LVR);
  65	ver = GET_APIC_VERSION(v);
  66	maxlvt = GET_APIC_MAXLVT(v);
  67	return maxlvt;
  68}
  69
  70void clear_local_APIC(void)
  71{
  72	int maxlvt;
  73	unsigned int v;
  74
  75	maxlvt = get_maxlvt();
  76
  77	/*
  78	 * Masking an LVT entry on a P6 can trigger a local APIC error
  79	 * if the vector is zero. Mask LVTERR first to prevent this.
  80	 */
  81	if (maxlvt >= 3) {
  82		v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
  83		apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
  84	}
  85	/*
  86	 * Careful: we have to set masks only first to deassert
  87	 * any level-triggered sources.
  88	 */
  89	v = apic_read(APIC_LVTT);
  90	apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
  91	v = apic_read(APIC_LVT0);
  92	apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
  93	v = apic_read(APIC_LVT1);
  94	apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
  95	if (maxlvt >= 4) {
  96		v = apic_read(APIC_LVTPC);
  97		apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
  98	}
  99
 100	/*
 101	 * Clean APIC state for other OSs:
 102	 */
 103	apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
 104	apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
 105	apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
 106	if (maxlvt >= 3)
 107		apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
 108	if (maxlvt >= 4)
 109		apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
 110	v = GET_APIC_VERSION(apic_read(APIC_LVR));
 111	if (APIC_INTEGRATED(v)) {	/* !82489DX */
 112		if (maxlvt > 3)		/* Due to Pentium errata 3AP and 11AP. */
 113			apic_write(APIC_ESR, 0);
 114		apic_read(APIC_ESR);
 115	}
 116}
 117
 118void __init connect_bsp_APIC(void)
 119{
 120	if (pic_mode) {
 121		/*
 122		 * Do not trust the local APIC being empty at bootup.
 123		 */
 124		clear_local_APIC();
 125		/*
 126		 * PIC mode, enable APIC mode in the IMCR, i.e.
 127		 * connect BSP's local APIC to INT and NMI lines.
 128		 */
 129		apic_printk(APIC_VERBOSE, "leaving PIC mode, enabling APIC mode.\n");
 130		outb(0x70, 0x22);
 131		outb(0x01, 0x23);
 132	}
 133}
 134
 135void disconnect_bsp_APIC(void)
 136{
 137	if (pic_mode) {
 138		/*
 139		 * Put the board back into PIC mode (has an effect
 140		 * only on certain older boards).  Note that APIC
 141		 * interrupts, including IPIs, won't work beyond
 142		 * this point!  The only exception are INIT IPIs.
 143		 */
 144		apic_printk(APIC_QUIET, "disabling APIC mode, entering PIC mode.\n");
 145		outb(0x70, 0x22);
 146		outb(0x00, 0x23);
 147	}
 148}
 149
 150void disable_local_APIC(void)
 151{
 152	unsigned int value;
 153
 154	clear_local_APIC();
 155
 156	/*
 157	 * Disable APIC (implies clearing of registers
 158	 * for 82489DX!).
 159	 */
 160	value = apic_read(APIC_SPIV);
 161	value &= ~APIC_SPIV_APIC_ENABLED;
 162	apic_write_around(APIC_SPIV, value);
 163}
 164
 165/*
 166 * This is to verify that we're looking at a real local APIC.
 167 * Check these against your board if the CPUs aren't getting
 168 * started for no apparent reason.
 169 */
 170int __init verify_local_APIC(void)
 171{
 172	unsigned int reg0, reg1;
 173
 174	/*
 175	 * The version register is read-only in a real APIC.
 176	 */
 177	reg0 = apic_read(APIC_LVR);
 178	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
 179	apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
 180	reg1 = apic_read(APIC_LVR);
 181	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
 182
 183	/*
 184	 * The two version reads above should print the same
 185	 * numbers.  If the second one is different, then we
 186	 * poke at a non-APIC.
 187	 */
 188	if (reg1 != reg0)
 189		return 0;
 190
 191	/*
 192	 * Check if the version looks reasonably.
 193	 */
 194	reg1 = GET_APIC_VERSION(reg0);
 195	if (reg1 == 0x00 || reg1 == 0xff)
 196		return 0;
 197	reg1 = get_maxlvt();
 198	if (reg1 < 0x02 || reg1 == 0xff)
 199		return 0;
 200
 201	/*
 202	 * The ID register is read/write in a real APIC.
 203	 */
 204	reg0 = apic_read(APIC_ID);
 205	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
 206	apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
 207	reg1 = apic_read(APIC_ID);
 208	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
 209	apic_write(APIC_ID, reg0);
 210	if (reg1 != (reg0 ^ APIC_ID_MASK))
 211		return 0;
 212
 213	/*
 214	 * The next two are just to see if we have sane values.
 215	 * They're only really relevant if we're in Virtual Wire
 216	 * compatibility mode, but most boxes are anymore.
 217	 */
 218	reg0 = apic_read(APIC_LVT0);
 219	apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0);
 220	reg1 = apic_read(APIC_LVT1);
 221	apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
 222
 223	return 1;
 224}
 225
 226void __init sync_Arb_IDs(void)
 227{
 228	/* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
 229	unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
 230	if (ver >= 0x14)	/* P4 or higher */
 231		return;
 232
 233	/*
 234	 * Wait for idle.
 235	 */
 236	apic_wait_icr_idle();
 237
 238	apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
 239	apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
 240				| APIC_DM_INIT);
 241}
 242
 243extern void __error_in_apic_c (void);
 244
 245/*
 246 * An initial setup of the virtual wire mode.
 247 */
 248void __init init_bsp_APIC(void)
 249{
 250	unsigned int value, ver;
 251
 252	/*
 253	 * Don't do the setup now if we have a SMP BIOS as the
 254	 * through-I/O-APIC virtual wire mode might be active.
 255	 */
 256	if (smp_found_config || !cpu_has_apic)
 257		return;
 258
 259	value = apic_read(APIC_LVR);
 260	ver = GET_APIC_VERSION(value);
 261
 262	/*
 263	 * Do not trust the local APIC being empty at bootup.
 264	 */
 265	clear_local_APIC();
 266
 267	/*
 268	 * Enable APIC.
 269	 */
 270	value = apic_read(APIC_SPIV);
 271	value &= ~APIC_VECTOR_MASK;
 272	value |= APIC_SPIV_APIC_ENABLED;
 273	value |= APIC_SPIV_FOCUS_DISABLED;
 274	value |= SPURIOUS_APIC_VECTOR;
 275	apic_write_around(APIC_SPIV, value);
 276
 277	/*
 278	 * Set up the virtual wire mode.
 279	 */
 280	apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
 281	value = APIC_DM_NMI;
 282	if (!APIC_INTEGRATED(ver))		/* 82489DX */
 283		value |= APIC_LVT_LEVEL_TRIGGER;
 284	apic_write_around(APIC_LVT1, value);
 285}
 286
 287void __init setup_local_APIC (void)
 288{
 289	unsigned int value, ver, maxlvt;
 290
 291	/* Pound the ESR really hard over the head with a big hammer - mbligh */
 292	if (esr_disable) {
 293		apic_write(APIC_ESR, 0);
 294		apic_write(APIC_ESR, 0);
 295		apic_write(APIC_ESR, 0);
 296		apic_write(APIC_ESR, 0);
 297	}
 298
 299	value = apic_read(APIC_LVR);
 300	ver = GET_APIC_VERSION(value);
 301
 302	if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
 303		__error_in_apic_c();
 304
 305	/*
 306	 * Double-check whether this APIC is really registered.
 307	 * This is meaningless in clustered apic mode, so we skip it.
 308	 */
 309	if (!apic_id_registered())
 310		BUG();
 311
 312	/*
 313	 * Intel recommends to set DFR, LDR and TPR before enabling
 314	 * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
 315	 * document number 292116).  So here it goes...
 316	 */
 317	init_apic_ldr();
 318
 319	/*
 320	 * Set Task Priority to 'accept all'. We never change this
 321	 * later on.
 322	 */
 323	value = apic_read(APIC_TASKPRI);
 324	value &= ~APIC_TPRI_MASK;
 325	apic_write_around(APIC_TASKPRI, value);
 326
 327	/*
 328	 * Now that we are all set up, enable the APIC
 329	 */
 330	value = apic_read(APIC_SPIV);
 331	value &= ~APIC_VECTOR_MASK;
 332	/*
 333	 * Enable APIC
 334	 */
 335	value |= APIC_SPIV_APIC_ENABLED;
 336
 337	/*
 338	 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
 339	 * certain networking cards. If high frequency interrupts are
 340	 * happening on a particular IOAPIC pin, plus the IOAPIC routing
 341	 * entry is masked/unmasked at a high rate as well then sooner or
 342	 * later IOAPIC line gets 'stuck', no more interrupts are received
 343	 * from the device. If focus CPU is disabled then the hang goes
 344	 * away, oh well :-(
 345	 *
 346	 * [ This bug can be reproduced easily with a level-triggered
 347	 *   PCI Ne2000 networking cards and PII/PIII processors, dual
 348	 *   BX chipset. ]
 349	 */
 350	/*
 351	 * Actually disabling the focus CPU check just makes the hang less
 352	 * frequent as it makes the interrupt distributon model be more
 353	 * like LRU than MRU (the short-term load is more even across CPUs).
 354	 * See also the comment in end_level_ioapic_irq().  --macro
 355	 */
 356#if 1
 357	/* Enable focus processor (bit==0) */
 358	value &= ~APIC_SPIV_FOCUS_DISABLED;
 359#else
 360	/* Disable focus processor (bit==1) */
 361	value |= APIC_SPIV_FOCUS_DISABLED;
 362#endif
 363	/*
 364	 * Set spurious IRQ vector
 365	 */
 366	value |= SPURIOUS_APIC_VECTOR;
 367	apic_write_around(APIC_SPIV, value);
 368
 369	/*
 370	 * Set up LVT0, LVT1:
 371	 *
 372	 * set up through-local-APIC on the BP's LINT0. This is not
 373	 * strictly necessary in pure symmetric-IO mode, but sometimes
 374	 * we delegate interrupts to the 8259A.
 375	 */
 376	/*
 377	 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
 378	 */
 379	value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
 380	if (!smp_processor_id() && (pic_mode || !value)) {
 381		value = APIC_DM_EXTINT;
 382		apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id());
 383	} else {
 384		value = APIC_DM_EXTINT | APIC_LVT_MASKED;
 385		apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id());
 386	}
 387	apic_write_around(APIC_LVT0, value);
 388
 389	/*
 390	 * only the BP should see the LINT1 NMI signal, obviously.
 391	 */
 392	if (!smp_processor_id())
 393		value = APIC_DM_NMI;
 394	else
 395		value = APIC_DM_NMI | APIC_LVT_MASKED;
 396	if (!APIC_INTEGRATED(ver))		/* 82489DX */
 397		value |= APIC_LVT_LEVEL_TRIGGER;
 398	apic_write_around(APIC_LVT1, value);
 399
 400	if (APIC_INTEGRATED(ver) && !esr_disable) {		/* !82489DX */
 401		unsigned oldvalue;
 402		maxlvt = get_maxlvt();
 403		if (maxlvt > 3)		/* Due to the Pentium erratum 3AP. */
 404			apic_write(APIC_ESR, 0);
 405		oldvalue = apic_read(APIC_ESR);
 406		value = ERROR_APIC_VECTOR;      // enables sending errors
 407		apic_write_around(APIC_LVTERR, value);
 408		/*
 409		 * spec says clear errors after enabling vector.
 410		 */
 411		if (maxlvt > 3)
 412			apic_write(APIC_ESR, 0);
 413		value = apic_read(APIC_ESR);
 414		if (value != oldvalue)
 415			apic_printk(APIC_VERBOSE,
 416			"ESR value after enabling vector: %08x, after %08x\n",
 417			oldvalue, value);
 418	} else {
 419		if (esr_disable)	
 420			/* 
 421			 * Something untraceble is creating bad interrupts on 
 422			 * secondary quads ... for the moment, just leave the
 423			 * ESR disabled - we can't do anything useful with the
 424			 * errors anyway - mbligh
 425			 */
 426			apic_printk(APIC_DEBUG, "Leaving ESR disabled.\n");
 427		else 
 428			apic_printk(APIC_DEBUG, "No ESR for 82489DX.\n");
 429	}
 430
 431	nmi_watchdog_default();
 432	if (nmi_watchdog == NMI_LOCAL_APIC)
 433		setup_apic_nmi_watchdog();
 434	apic_pm_activate();
 435}
 436
 437#ifdef CONFIG_PM
 438
 439static struct {
 440	/* 'active' is true if the local APIC was enabled by us and
 441	   not the BIOS; this signifies that we are also responsible
 442	   for disabling it before entering apm/acpi suspend */
 443	int active;
 444	/* r/w apic fields */
 445	unsigned int apic_id;
 446	unsigned int apic_taskpri;
 447	unsigned int apic_ldr;
 448	unsigned int apic_dfr;
 449	unsigned int apic_spiv;
 450	unsigned int apic_lvtt;
 451	unsigned int apic_lvtpc;
 452	unsigned int apic_lvt0;
 453	unsigned int apic_lvt1;
 454	unsigned int apic_lvterr;
 455	unsigned int apic_tmict;
 456	unsigned int apic_tdcr;
 457	unsigned int apic_thmr;
 458} apic_pm_state;
 459
 460static int lapic_suspend(struct sys_device *dev, u32 state)
 461{
 462	unsigned long flags;
 463
 464	if (!apic_pm_state.active)
 465		return 0;
 466
 467	apic_pm_state.apic_id = apic_read(APIC_ID);
 468	apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
 469	apic_pm_state.apic_ldr = apic_read(APIC_LDR);
 470	apic_pm_state.apic_dfr = apic_read(APIC_DFR);
 471	apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
 472	apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
 473	apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
 474	apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
 475	apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
 476	apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
 477	apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
 478	apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
 479	apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
 480	local_save_flags(flags);
 481	local_irq_disable();
 482	disable_local_APIC();
 483	local_irq_restore(flags);
 484	return 0;
 485}
 486
 487static int lapic_resume(struct sys_device *dev)
 488{
 489	unsigned int l, h;
 490	unsigned long flags;
 491
 492	if (!apic_pm_state.active)
 493		return 0;
 494
 495	/* XXX: Pavel needs this for S3 resume, but can't explain why */
 496	set_fixmap_nocache(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE);
 497
 498	local_irq_save(flags);
 499	rdmsr(MSR_IA32_APICBASE, l, h);
 500	l &= ~MSR_IA32_APICBASE_BASE;
 501	l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
 502	wrmsr(MSR_IA32_APICBASE, l, h);
 503	apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
 504	apic_write(APIC_ID, apic_pm_state.apic_id);
 505	apic_write(APIC_DFR, apic_pm_state.apic_dfr);
 506	apic_write(APIC_LDR, apic_pm_state.apic_ldr);
 507	apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
 508	apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
 509	apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
 510	apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
 511	apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
 512	apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
 513	apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
 514	apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
 515	apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
 516	apic_write(APIC_ESR, 0);
 517	apic_read(APIC_ESR);
 518	apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
 519	apic_write(APIC_ESR, 0);
 520	apic_read(APIC_ESR);
 521	local_irq_restore(flags);
 522	return 0;
 523}
 524
 525static struct sysdev_class lapic_sysclass = {
 526	set_kset_name("lapic"),
 527	.resume		= lapic_resume,
 528	.suspend	= lapic_suspend,
 529};
 530
 531static struct sys_device device_lapic = {
 532	.id		= 0,
 533	.cls		= &lapic_sysclass,
 534};
 535
 536static void __init apic_pm_activate(void)
 537{
 538	apic_pm_state.active = 1;
 539}
 540
 541static int __init init_lapic_sysfs(void)
 542{
 543	int error;
 544	if (!cpu_has_apic)
 545		return 0;
 546	/* XXX: remove suspend/resume procs if !apic_pm_state.active? */
 547	error = sysdev_class_register(&lapic_sysclass);
 548	if (!error)
 549		error = sysdev_register(&device_lapic);
 550	return error;
 551}
 552device_initcall(init_lapic_sysfs);
 553
 554#else	/* CONFIG_PM */
 555
 556static void apic_pm_activate(void) { }
 557
 558#endif	/* CONFIG_PM */
 559
 560static int __init apic_set_verbosity(char *str)
 561{
 562	if (strcmp("debug", str) == 0)
 563		apic_verbosity = APIC_DEBUG;
 564	else if (strcmp("verbose", str) == 0)
 565		apic_verbosity = APIC_VERBOSE;
 566	else
 567		printk(KERN_WARNING "APIC Verbosity level %s not recognised"
 568				" use apic=verbose or apic=debug", str);
 569
 570	return 0;
 571}
 572
 573__setup("apic=", apic_set_verbosity);
 574
 575/*
 576 * Detect and enable local APICs on non-SMP boards.
 577 * Original code written by Keir Fraser.
 578 * On AMD64 we trust the BIOS - if it says no APIC it is likely
 579 * not correctly set up (usually the APIC timer won't work etc.) 
 580 */
 581
 582static int __init detect_init_APIC (void)
 583{
 584	if (!cpu_has_apic) {
 585		printk(KERN_INFO "No local APIC present\n");
 586		return -1;
 587	}
 588
 589	mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
 590	boot_cpu_id = 0;
 591	return 0;
 592}
 593
 594void __init init_apic_mappings(void)
 595{
 596	unsigned long apic_phys;
 597
 598	/*
 599	 * If no local APIC can be found then set up a fake all
 600	 * zeroes page to simulate the local APIC and another
 601	 * one for the IO-APIC.
 602	 */
 603	if (!smp_found_config && detect_init_APIC()) {
 604		apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
 605		apic_phys = __pa(apic_phys);
 606	} else
 607		apic_phys = mp_lapic_addr;
 608
 609	set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
 610	apic_printk(APIC_VERBOSE,"mapped APIC to %16lx (%16lx)\n", APIC_BASE, apic_phys);
 611
 612	/*
 613	 * Fetch the APIC ID of the BSP in case we have a
 614	 * default configuration (or the MP table is broken).
 615	 */
 616	if (boot_cpu_id == -1U)
 617		boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
 618
 619#ifdef CONFIG_X86_IO_APIC
 620	{
 621		unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
 622		int i;
 623
 624		for (i = 0; i < nr_ioapics; i++) {
 625			if (smp_found_config) {
 626				ioapic_phys = mp_ioapics[i].mpc_apicaddr;
 627			} else {
 628				ioapic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
 629				ioapic_phys = __pa(ioapic_phys);
 630			}
 631			set_fixmap_nocache(idx, ioapic_phys);
 632			apic_printk(APIC_VERBOSE,"mapped IOAPIC to %016lx (%016lx)\n",
 633					__fix_to_virt(idx), ioapic_phys);
 634			idx++;
 635		}
 636	}
 637#endif
 638}
 639
 640/*
 641 * This function sets up the local APIC timer, with a timeout of
 642 * 'clocks' APIC bus clock. During calibration we actually call
 643 * this function twice on the boot CPU, once with a bogus timeout
 644 * value, second time for real. The other (noncalibrating) CPUs
 645 * call this function only once, with the real, calibrated value.
 646 *
 647 * We do reads before writes even if unnecessary, to get around the
 648 * P5 APIC double write bug.
 649 */
 650
 651#define APIC_DIVISOR 16
 652
 653static void __setup_APIC_LVTT(unsigned int clocks)
 654{
 655	unsigned int lvtt_value, tmp_value, ver;
 656
 657	ver = GET_APIC_VERSION(apic_read(APIC_LVR));
 658	lvtt_value = APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR;
 659	if (!APIC_INTEGRATED(ver))
 660		lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
 661	apic_write_around(APIC_LVTT, lvtt_value);
 662
 663	/*
 664	 * Divide PICLK by 16
 665	 */
 666	tmp_value = apic_read(APIC_TDCR);
 667	apic_write_around(APIC_TDCR, (tmp_value
 668				& ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
 669				| APIC_TDR_DIV_16);
 670
 671	apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
 672}
 673
 674static void setup_APIC_timer(unsigned int clocks)
 675{
 676	unsigned long flags;
 677
 678	local_irq_save(flags);
 679
 680	/* For some reasons this doesn't work on Simics, so fake it for now */ 
 681	if (!strstr(boot_cpu_data.x86_model_id, "Screwdriver")) { 
 682	__setup_APIC_LVTT(clocks);
 683		return;
 684	} 
 685
 686	/* wait for irq slice */
 687 	if (vxtime.hpet_address) {
 688 		int trigger = hpet_readl(HPET_T0_CMP);
 689 		while (hpet_readl(HPET_COUNTER) >= trigger)
 690 			/* do nothing */ ;
 691 		while (hpet_readl(HPET_COUNTER) <  trigger)
 692 			/* do nothing */ ;
 693 	} else {
 694		int c1, c2;
 695		outb_p(0x00, 0x43);
 696		c2 = inb_p(0x40);
 697		c2 |= inb_p(0x40) << 8;
 698	do {
 699			c1 = c2;
 700			outb_p(0x00, 0x43);
 701			c2 = inb_p(0x40);
 702			c2 |= inb_p(0x40) << 8;
 703		} while (c2 - c1 < 300);
 704	}
 705
 706	__setup_APIC_LVTT(clocks);
 707
 708	local_irq_restore(flags);
 709}
 710
 711/*
 712 * In this function we calibrate APIC bus clocks to the external
 713 * timer. Unfortunately we cannot use jiffies and the timer irq
 714 * to calibrate, since some later bootup code depends on getting
 715 * the first irq? Ugh.
 716 *
 717 * We want to do the calibration only once since we
 718 * want to have local timer irqs syncron. CPUs connected
 719 * by the same APIC bus have the very same bus frequency.
 720 * And we want to have irqs off anyways, no accidental
 721 * APIC irq that way.
 722 */
 723
 724#define TICK_COUNT 100000000
 725
 726static int __init calibrate_APIC_clock(void)
 727{
 728	int apic, apic_start, tsc, tsc_start;
 729	int result;
 730	/*
 731	 * Put whatever arbitrary (but long enough) timeout
 732	 * value into the APIC clock, we just want to get the
 733	 * counter running for calibration.
 734	 */
 735	__setup_APIC_LVTT(1000000000);
 736
 737	apic_start = apic_read(APIC_TMCCT);
 738	rdtscl(tsc_start);
 739
 740	do {
 741		apic = apic_read(APIC_TMCCT);
 742		rdtscl(tsc);
 743	} while ((tsc - tsc_start) < TICK_COUNT && (apic - apic_start) < TICK_COUNT);
 744
 745	result = (apic_start - apic) * 1000L * cpu_khz / (tsc - tsc_start);
 746
 747	printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
 748		result / 1000 / 1000, result / 1000 % 1000);
 749
 750	return result * APIC_DIVISOR / HZ;
 751}
 752
 753static unsigned int calibration_result;
 754
 755void __init setup_boot_APIC_clock (void)
 756{
 757	if (disable_apic_timer) { 
 758		printk(KERN_INFO "Disabling APIC timer\n"); 
 759		return; 
 760	} 
 761
 762	printk(KERN_INFO "Using local APIC timer interrupts.\n");
 763	using_apic_timer = 1;
 764
 765	local_irq_disable();
 766
 767	calibration_result = calibrate_APIC_clock();
 768	/*
 769	 * Now set up the timer for real.
 770	 */
 771	setup_APIC_timer(calibration_result);
 772
 773	local_irq_enable();
 774}
 775
 776void __init setup_secondary_APIC_clock(void)
 777{
 778	local_irq_disable(); /* FIXME: Do we need this? --RR */
 779	setup_APIC_timer(calibration_result);
 780	local_irq_enable();
 781}
 782
 783void __init disable_APIC_timer(void)
 784{
 785	if (using_apic_timer) {
 786		unsigned long v;
 787
 788		v = apic_read(APIC_LVTT);
 789		apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
 790	}
 791}
 792
 793void enable_APIC_timer(void)
 794{
 795	if (using_apic_timer) {
 796		unsigned long v;
 797
 798		v = apic_read(APIC_LVTT);
 799		apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED);
 800	}
 801}
 802
 803/*
 804 * the frequency of the profiling timer can be changed
 805 * by writing a multiplier value into /proc/profile.
 806 */
 807int setup_profiling_timer(unsigned int multiplier)
 808{
 809	int i;
 810
 811	/*
 812	 * Sanity check. [at least 500 APIC cycles should be
 813	 * between APIC interrupts as a rule of thumb, to avoid
 814	 * irqs flooding us]
 815	 */
 816	if ( (!multiplier) || (calibration_result/multiplier < 500))
 817		return -EINVAL;
 818
 819	/* 
 820	 * Set the new multiplier for each CPU. CPUs don't start using the
 821	 * new values until the next timer interrupt in which they do process
 822	 * accounting. At that time they also adjust their APIC timers
 823	 * accordingly.
 824	 */
 825	for (i = 0; i < NR_CPUS; ++i)
 826		per_cpu(prof_multiplier, i) = multiplier;
 827
 828	return 0;
 829}
 830
 831#undef APIC_DIVISOR
 832
 833/*
 834 * Local timer interrupt handler. It does both profiling and
 835 * process statistics/rescheduling.
 836 *
 837 * We do profiling in every local tick, statistics/rescheduling
 838 * happen only every 'profiling multiplier' ticks. The default
 839 * multiplier is 1 and it can be changed by writing the new multiplier
 840 * value into /proc/profile.
 841 */
 842
 843void smp_local_timer_interrupt(struct pt_regs *regs)
 844{
 845	int cpu = smp_processor_id();
 846
 847	profile_tick(CPU_PROFILING, regs);
 848	if (--per_cpu(prof_counter, cpu) <= 0) {
 849		/*
 850		 * The multiplier may have changed since the last time we got
 851		 * to this point as a result of the user writing to
 852		 * /proc/profile. In this case we need to adjust the APIC
 853		 * timer accordingly.
 854		 *
 855		 * Interrupts are already masked off at this point.
 856		 */
 857		per_cpu(prof_counter, cpu) = per_cpu(prof_multiplier, cpu);
 858		if (per_cpu(prof_counter, cpu) != 
 859		    per_cpu(prof_old_multiplier, cpu)) {
 860			__setup_APIC_LVTT(calibration_result/
 861					per_cpu(prof_counter, cpu));
 862			per_cpu(prof_old_multiplier, cpu) =
 863				per_cpu(prof_counter, cpu);
 864		}
 865
 866#ifdef CONFIG_SMP
 867		update_process_times(user_mode(regs));
 868#endif
 869	}
 870
 871	/*
 872	 * We take the 'long' return path, and there every subsystem
 873	 * grabs the appropriate locks (kernel lock/ irq lock).
 874	 *
 875	 * we might want to decouple profiling from the 'long path',
 876	 * and do the profiling totally in assembly.
 877	 *
 878	 * Currently this isn't too much of an issue (performance wise),
 879	 * we can take more than 100K local irqs per second on a 100 MHz P5.
 880	 */
 881}
 882
 883/*
 884 * Local APIC timer interrupt. This is the most natural way for doing
 885 * local interrupts, but local timer interrupts can be emulated by
 886 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
 887 *
 888 * [ if a single-CPU system runs an SMP kernel then we call the local
 889 *   interrupt as well. Thus we cannot inline the local irq ... ]
 890 */
 891void smp_apic_timer_interrupt(struct pt_regs *regs)
 892{
 893	/*
 894	 * the NMI deadlock-detector uses this.
 895	 */
 896	add_pda(apic_timer_irqs, 1);
 897
 898	/*
 899	 * NOTE! We'd better ACK the irq immediately,
 900	 * because timer handling can be slow.
 901	 */
 902	ack_APIC_irq();
 903	/*
 904	 * update_process_times() expects us to have done irq_enter().
 905	 * Besides, if we don't timer interrupts ignore the global
 906	 * interrupt lock, which is the WrongThing (tm) to do.
 907	 */
 908	irq_enter();
 909	smp_local_timer_interrupt(regs);
 910	irq_exit();
 911}
 912
 913/*
 914 * oem_force_hpet_timer -- force HPET mode for some boxes.
 915 *
 916 * Thus far, the major user of this is IBM's Summit2 series:
 917 *
 918 * Clustered boxes may have unsynced TSC problems if they are
 919 * multi-chassis. Use available data to take a good guess.
 920 * If in doubt, go HPET.
 921 */
 922__init int oem_force_hpet_timer(void)
 923{
 924	int i, clusters, zeros;
 925	unsigned id;
 926	DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
 927
 928	bitmap_empty(clustermap, NUM_APIC_CLUSTERS);
 929
 930	for (i = 0; i < NR_CPUS; i++) {
 931		id = bios_cpu_apicid[i];
 932		if (id != BAD_APICID)
 933			__set_bit(APIC_CLUSTERID(id), clustermap);
 934	}
 935
 936	/* Problem:  Partially populated chassis may not have CPUs in some of
 937	 * the APIC clusters they have been allocated.  Only present CPUs have
 938	 * bios_cpu_apicid entries, thus causing zeroes in the bitmap.  Since
 939	 * clusters are allocated sequentially, count zeros only if they are
 940	 * bounded by ones.
 941	 */
 942	clusters = 0;
 943	zeros = 0;
 944	for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
 945		if (test_bit(i, clustermap)) {
 946			clusters += 1 + zeros;
 947			zeros = 0;
 948		} else
 949			++zeros;
 950	}
 951
 952	/*
 953	 * If clusters > 2, then should be multi-chassis.  Return 1 for HPET.
 954	 * Else return 0 to use TSC.
 955	 * May have to revisit this when multi-core + hyperthreaded CPUs come
 956	 * out, but AFAIK this will work even for them.
 957	 */
 958	return (clusters > 2);
 959}
 960
 961/*
 962 * This interrupt should _never_ happen with our APIC/SMP architecture
 963 */
 964asmlinkage void smp_spurious_interrupt(void)
 965{
 966	unsigned int v;
 967	irq_enter();
 968	/*
 969	 * Check if this really is a spurious interrupt and ACK it
 970	 * if it is a vectored one.  Just in case...
 971	 * Spurious interrupts should not be ACKed.
 972	 */
 973	v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
 974	if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
 975		ack_APIC_irq();
 976
 977#if 0
 978	static unsigned long last_warning; 
 979	static unsigned long skipped; 
 980
 981	/* see sw-dev-man vol 3, chapter 7.4.13.5 */
 982	if (time_before(last_warning+30*HZ,jiffies)) { 
 983		printk(KERN_INFO "spurious APIC interrupt on CPU#%d, %ld skipped.\n",
 984		       smp_processor_id(), skipped);
 985		last_warning = jiffies; 
 986		skipped = 0;
 987	} else { 
 988		skipped++; 
 989	} 
 990#endif 
 991	irq_exit();
 992}
 993
 994/*
 995 * This interrupt should never happen with our APIC/SMP architecture
 996 */
 997
 998asmlinkage void smp_error_interrupt(void)
 999{
1000	unsigned int v, v1;
1001
1002	irq_enter();
1003	/* First tickle the hardware, only then report what went on. -- REW */
1004	v = apic_read(APIC_ESR);
1005	apic_write(APIC_ESR, 0);
1006	v1 = apic_read(APIC_ESR);
1007	ack_APIC_irq();
1008	atomic_inc(&irq_err_count);
1009
1010	/* Here is what the APIC error bits mean:
1011	   0: Send CS error
1012	   1: Receive CS error
1013	   2: Send accept error
1014	   3: Receive accept error
1015	   4: Reserved
1016	   5: Send illegal vector
1017	   6: Received illegal vector
1018	   7: Illegal register address
1019	*/
1020	printk (KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
1021	        smp_processor_id(), v , v1);
1022	irq_exit();
1023}
1024
1025int disable_apic; 
1026
1027/*
1028 * This initializes the IO-APIC and APIC hardware if this is
1029 * a UP kernel.
1030 */
1031int __init APIC_init_uniprocessor (void)
1032{
1033	if (disable_apic) { 
1034		printk(KERN_INFO "Apic disabled\n");
1035		return -1; 
1036	}
1037	if (!cpu_has_apic) { 
1038		disable_apic = 1;
1039		printk(KERN_INFO "Apic disabled by BIOS\n");
1040		return -1;
1041	}
1042
1043	verify_local_APIC();
1044
1045	connect_bsp_APIC();
1046
1047	phys_cpu_present_map = physid_mask_of_physid(0);
1048	apic_write_around(APIC_ID, boot_cpu_id);
1049
1050	setup_local_APIC();
1051
1052#ifdef CONFIG_X86_IO_APIC
1053	if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1054			setup_IO_APIC();
1055	else
1056		nr_ioapics = 0;
1057#endif
1058	setup_boot_APIC_clock();
1059
1060	return 0;
1061}
1062
1063static __init int setup_disableapic(char *str) 
1064{ 
1065	disable_apic = 1;
1066	return 0;
1067} 
1068
1069static __init int setup_nolapic(char *str) 
1070{ 
1071	disable_apic = 1;
1072	return 0;
1073} 
1074
1075static __init int setup_noapictimer(char *str) 
1076{ 
1077	disable_apic_timer = 1;
1078	return 0;
1079} 
1080
1081/* dummy parsing: see setup.c */
1082
1083__setup("disableapic", setup_disableapic); 
1084__setup("nolapic", setup_nolapic);  /* same as disableapic, for compatibility */
1085
1086__setup("noapictimer", setup_noapictimer); 
1087
1088/* no "lapic" flag - we only use the lapic when the BIOS tells us so. */