PageRenderTime 11ms CodeModel.GetById 8ms app.highlight 1ms RepoModel.GetById 1ms app.codeStats 0ms

/arch/v850/kernel/as85ep1.ld

https://bitbucket.org/evzijst/gittest
Unknown | 49 lines | 41 code | 8 blank | 0 comment | 0 complexity | 4f3e75e6554c5923ef0c5bea33a18bf4 MD5 | raw file
 1/* Linker script for the NEC AS85EP1 V850E evaluation board
 2   (CONFIG_V850E_AS85EP1).  */
 3
 4MEMORY {
 5	/* 1MB of internal instruction memory. */
 6	iMEM0 : ORIGIN = 0,	     LENGTH = 0x00100000
 7
 8	/* 1MB of static RAM.  */
 9	SRAM  : ORIGIN = SRAM_ADDR,  LENGTH = SRAM_SIZE
10
11	/* About 58MB of DRAM.  This can actually be at one of two
12	   positions, determined by jump JP3; we have to use the first
13	   position because the second is partially out of processor
14	   instruction addressing range (though in the second position
15	   there's actually 64MB available).  */
16	SDRAM : ORIGIN = SDRAM_ADDR, LENGTH = SDRAM_SIZE
17}
18
19SECTIONS {
20	.resetv : {
21		__intv_start = . ;
22			*(.intv.reset)	/* Reset vector */
23	} > iMEM0
24
25	.sram : {
26		RAMK_KRAM_CONTENTS
27
28		/* We stick most of the interrupt vectors here; they'll be
29		   copied into the proper location by the early init code (we
30		   can't put them directly in the right place because of
31		   hardware bugs).  The vectors shouldn't need to be
32		   relocated, so we don't have to use `> ...  AT> ...' to
33		   split the load/vm addresses (and we can't because of
34		   problems with the loader).  */
35		. = ALIGN (0x10) ;
36		__intv_copy_src_start = . ;
37			*(.intv.common)	/* Vectors common to all v850e proc. */
38			*(.intv.mach)	/* Machine-specific int. vectors.  */
39		. = ALIGN (0x10) ;
40		__intv_copy_src_end = . ;
41	} > SRAM
42
43	/* Where we end up putting the vectors.  */
44	__intv_copy_dst_start = 0x10 ;
45	__intv_copy_dst_end = __intv_copy_dst_start + (__intv_copy_src_end - __intv_copy_src_start) ;
46	__intv_end = __intv_copy_dst_end ;
47
48	.root : { ROOT_FS_CONTENTS } > SDRAM
49}