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/arch/sparc/mm/tsunami.S

https://bitbucket.org/evzijst/gittest
Assembly | 133 lines | 123 code | 10 blank | 0 comment | 0 complexity | fda89a31fef79df2f8c43e61d5746ffb MD5 | raw file
  1/* $Id: tsunami.S,v 1.7 2001/12/21 04:56:15 davem Exp $
  2 * tsunami.S: High speed MicroSparc-I mmu/cache operations.
  3 *
  4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
  5 */
  6
  7#include <linux/config.h>
  8#include <asm/ptrace.h>
  9#include <asm/asm_offsets.h>
 10#include <asm/psr.h>
 11#include <asm/asi.h>
 12#include <asm/page.h>
 13#include <asm/pgtsrmmu.h>
 14
 15	.text
 16	.align	4
 17
 18	.globl	tsunami_flush_cache_all, tsunami_flush_cache_mm
 19	.globl	tsunami_flush_cache_range, tsunami_flush_cache_page
 20	.globl	tsunami_flush_page_to_ram, tsunami_flush_page_for_dma
 21	.globl	tsunami_flush_sig_insns
 22	.globl	tsunami_flush_tlb_all, tsunami_flush_tlb_mm
 23	.globl	tsunami_flush_tlb_range, tsunami_flush_tlb_page
 24
 25	/* Sliiick... */
 26tsunami_flush_cache_page:
 27tsunami_flush_cache_range:
 28	ld	[%o0 + 0x0], %o0	/* XXX vma->vm_mm, GROSS XXX */
 29tsunami_flush_cache_mm:
 30	ld	[%o0 + AOFF_mm_context], %g2
 31	cmp	%g2, -1
 32	be	tsunami_flush_cache_out
 33tsunami_flush_cache_all:
 34	WINDOW_FLUSH(%g4, %g5)
 35tsunami_flush_page_for_dma:
 36	sta	%g0, [%g0] ASI_M_IC_FLCLEAR
 37	sta	%g0, [%g0] ASI_M_DC_FLCLEAR
 38tsunami_flush_cache_out:
 39tsunami_flush_page_to_ram:
 40	retl
 41	 nop
 42
 43tsunami_flush_sig_insns:
 44	flush	%o1
 45	retl
 46	 flush	%o1 + 4
 47
 48	/* More slick stuff... */
 49tsunami_flush_tlb_range:
 50	ld	[%o0 + 0x00], %o0	/* XXX vma->vm_mm GROSS XXX */
 51tsunami_flush_tlb_mm:
 52	ld	[%o0 + AOFF_mm_context], %g2
 53	cmp	%g2, -1
 54	be	tsunami_flush_tlb_out
 55tsunami_flush_tlb_all:
 56	 mov	0x400, %o1
 57	sta	%g0, [%o1] ASI_M_FLUSH_PROBE
 58	nop
 59	nop
 60	nop
 61	nop
 62	nop
 63tsunami_flush_tlb_out:
 64	retl
 65	 nop
 66
 67	/* This one can be done in a fine grained manner... */
 68tsunami_flush_tlb_page:
 69	ld	[%o0 + 0x00], %o0	/* XXX vma->vm_mm GROSS XXX */
 70	mov	SRMMU_CTX_REG, %g1
 71	ld	[%o0 + AOFF_mm_context], %o3
 72	andn	%o1, (PAGE_SIZE - 1), %o1
 73	cmp	%o3, -1
 74	be	tsunami_flush_tlb_page_out
 75	 lda	[%g1] ASI_M_MMUREGS, %g5
 76	sta	%o3, [%g1] ASI_M_MMUREGS
 77	sta	%g0, [%o1] ASI_M_FLUSH_PROBE
 78	nop
 79	nop
 80	nop
 81	nop
 82	nop
 83tsunami_flush_tlb_page_out:
 84	retl
 85	 sta	%g5, [%g1] ASI_M_MMUREGS
 86
 87#define MIRROR_BLOCK(dst, src, offset, t0, t1, t2, t3) \
 88	ldd	[src + offset + 0x18], t0; \
 89	std	t0, [dst + offset + 0x18]; \
 90	ldd	[src + offset + 0x10], t2; \
 91	std	t2, [dst + offset + 0x10]; \
 92	ldd	[src + offset + 0x08], t0; \
 93	std	t0, [dst + offset + 0x08]; \
 94	ldd	[src + offset + 0x00], t2; \
 95	std	t2, [dst + offset + 0x00];
 96
 97	.globl	tsunami_copy_1page
 98tsunami_copy_1page:
 99/* NOTE: This routine has to be shorter than 70insns --jj */
100	or	%g0, (PAGE_SIZE >> 8), %g1
1011:
102	MIRROR_BLOCK(%o0, %o1, 0x00, %o2, %o3, %o4, %o5)
103	MIRROR_BLOCK(%o0, %o1, 0x20, %o2, %o3, %o4, %o5)
104	MIRROR_BLOCK(%o0, %o1, 0x40, %o2, %o3, %o4, %o5)
105	MIRROR_BLOCK(%o0, %o1, 0x60, %o2, %o3, %o4, %o5)
106	MIRROR_BLOCK(%o0, %o1, 0x80, %o2, %o3, %o4, %o5)
107	MIRROR_BLOCK(%o0, %o1, 0xa0, %o2, %o3, %o4, %o5)
108	MIRROR_BLOCK(%o0, %o1, 0xc0, %o2, %o3, %o4, %o5)
109	MIRROR_BLOCK(%o0, %o1, 0xe0, %o2, %o3, %o4, %o5)
110	subcc	%g1, 1, %g1
111	add	%o0, 0x100, %o0
112	bne	1b
113	 add	%o1, 0x100, %o1
114
115	.globl	tsunami_setup_blockops
116tsunami_setup_blockops:
117	sethi	%hi(__copy_1page), %o0
118	or	%o0, %lo(__copy_1page), %o0
119	sethi	%hi(tsunami_copy_1page), %o1
120	or	%o1, %lo(tsunami_copy_1page), %o1
121	sethi	%hi(tsunami_setup_blockops), %o2
122	or	%o2, %lo(tsunami_setup_blockops), %o2
123	ld	[%o1], %o4
1241:	add	%o1, 4, %o1
125	st	%o4, [%o0]
126	add	%o0, 4, %o0
127	cmp	%o1, %o2
128	bne	1b
129	ld	[%o1], %o4
130	sta	%g0, [%g0] ASI_M_IC_FLCLEAR
131	sta	%g0, [%g0] ASI_M_DC_FLCLEAR
132	retl
133	 nop