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/arch/sh/kernel/cpu/irq_ipr.c

https://bitbucket.org/evzijst/gittest
C | 339 lines | 260 code | 45 blank | 34 comment | 45 complexity | 2c4f8f5df08b2c0b924da949c6bd6b23 MD5 | raw file
  1/* $Id: irq_ipr.c,v 1.1.2.1 2002/11/17 10:53:43 mrbrown Exp $
  2 *
  3 * linux/arch/sh/kernel/irq_ipr.c
  4 *
  5 * Copyright (C) 1999  Niibe Yutaka & Takeshi Yaegashi
  6 * Copyright (C) 2000  Kazumoto Kojima
  7 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
  8 *
  9 * Interrupt handling for IPR-based IRQ.
 10 *
 11 * Supported system:
 12 *	On-chip supporting modules (TMU, RTC, etc.).
 13 *	On-chip supporting modules for SH7709/SH7709A/SH7729/SH7300.
 14 *	Hitachi SolutionEngine external I/O:
 15 *		MS7709SE01, MS7709ASE01, and MS7750SE01
 16 *
 17 */
 18
 19#include <linux/config.h>
 20#include <linux/init.h>
 21#include <linux/irq.h>
 22#include <linux/module.h>
 23
 24#include <asm/system.h>
 25#include <asm/io.h>
 26#include <asm/machvec.h>
 27
 28struct ipr_data {
 29	unsigned int addr;	/* Address of Interrupt Priority Register */
 30	int shift;		/* Shifts of the 16-bit data */
 31	int priority;		/* The priority */
 32};
 33static struct ipr_data ipr_data[NR_IRQS];
 34
 35static void enable_ipr_irq(unsigned int irq);
 36static void disable_ipr_irq(unsigned int irq);
 37
 38/* shutdown is same as "disable" */
 39#define shutdown_ipr_irq disable_ipr_irq
 40
 41static void mask_and_ack_ipr(unsigned int);
 42static void end_ipr_irq(unsigned int irq);
 43
 44static unsigned int startup_ipr_irq(unsigned int irq)
 45{
 46	enable_ipr_irq(irq);
 47	return 0; /* never anything pending */
 48}
 49
 50static struct hw_interrupt_type ipr_irq_type = {
 51	"IPR-IRQ",
 52	startup_ipr_irq,
 53	shutdown_ipr_irq,
 54	enable_ipr_irq,
 55	disable_ipr_irq,
 56	mask_and_ack_ipr,
 57	end_ipr_irq
 58};
 59
 60static void disable_ipr_irq(unsigned int irq)
 61{
 62	unsigned long val, flags;
 63	unsigned int addr = ipr_data[irq].addr;
 64	unsigned short mask = 0xffff ^ (0x0f << ipr_data[irq].shift);
 65
 66	/* Set the priority in IPR to 0 */
 67	local_irq_save(flags);
 68	val = ctrl_inw(addr);
 69	val &= mask;
 70	ctrl_outw(val, addr);
 71	local_irq_restore(flags);
 72}
 73
 74static void enable_ipr_irq(unsigned int irq)
 75{
 76	unsigned long val, flags;
 77	unsigned int addr = ipr_data[irq].addr;
 78	int priority = ipr_data[irq].priority;
 79	unsigned short value = (priority << ipr_data[irq].shift);
 80
 81	/* Set priority in IPR back to original value */
 82	local_irq_save(flags);
 83	val = ctrl_inw(addr);
 84	val |= value;
 85	ctrl_outw(val, addr);
 86	local_irq_restore(flags);
 87}
 88
 89static void mask_and_ack_ipr(unsigned int irq)
 90{
 91	disable_ipr_irq(irq);
 92
 93#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
 94    defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
 95	/* This is needed when we use edge triggered setting */
 96	/* XXX: Is it really needed? */
 97	if (IRQ0_IRQ <= irq && irq <= IRQ5_IRQ) {
 98		/* Clear external interrupt request */
 99		int a = ctrl_inb(INTC_IRR0);
100		a &= ~(1 << (irq - IRQ0_IRQ));
101		ctrl_outb(a, INTC_IRR0);
102	}
103#endif
104}
105
106static void end_ipr_irq(unsigned int irq)
107{
108	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
109		enable_ipr_irq(irq);
110}
111
112void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, int priority)
113{
114	disable_irq_nosync(irq);
115	ipr_data[irq].addr = addr;
116	ipr_data[irq].shift = pos*4; /* POSition (0-3) x 4 means shift */
117	ipr_data[irq].priority = priority;
118
119	irq_desc[irq].handler = &ipr_irq_type;
120	disable_ipr_irq(irq);
121}
122
123#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
124    defined(CONFIG_CPU_SUBTYPE_SH7707) || \
125    defined(CONFIG_CPU_SUBTYPE_SH7709)
126static unsigned char pint_map[256];
127static unsigned long portcr_mask = 0;
128
129static void enable_pint_irq(unsigned int irq);
130static void disable_pint_irq(unsigned int irq);
131
132/* shutdown is same as "disable" */
133#define shutdown_pint_irq disable_pint_irq
134
135static void mask_and_ack_pint(unsigned int);
136static void end_pint_irq(unsigned int irq);
137
138static unsigned int startup_pint_irq(unsigned int irq)
139{
140	enable_pint_irq(irq);
141	return 0; /* never anything pending */
142}
143
144static struct hw_interrupt_type pint_irq_type = {
145	"PINT-IRQ",
146	startup_pint_irq,
147	shutdown_pint_irq,
148	enable_pint_irq,
149	disable_pint_irq,
150	mask_and_ack_pint,
151	end_pint_irq
152};
153
154static void disable_pint_irq(unsigned int irq)
155{
156	unsigned long val, flags;
157
158	local_irq_save(flags);
159	val = ctrl_inw(INTC_INTER);
160	val &= ~(1 << (irq - PINT_IRQ_BASE));
161	ctrl_outw(val, INTC_INTER);	/* disable PINTn */
162	portcr_mask &= ~(3 << (irq - PINT_IRQ_BASE)*2);
163	local_irq_restore(flags);
164}
165
166static void enable_pint_irq(unsigned int irq)
167{
168	unsigned long val, flags;
169
170	local_irq_save(flags);
171	val = ctrl_inw(INTC_INTER);
172	val |= 1 << (irq - PINT_IRQ_BASE);
173	ctrl_outw(val, INTC_INTER);	/* enable PINTn */
174	portcr_mask |= 3 << (irq - PINT_IRQ_BASE)*2;
175	local_irq_restore(flags);
176}
177
178static void mask_and_ack_pint(unsigned int irq)
179{
180	disable_pint_irq(irq);
181}
182
183static void end_pint_irq(unsigned int irq)
184{
185	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
186		enable_pint_irq(irq);
187}
188
189void make_pint_irq(unsigned int irq)
190{
191	disable_irq_nosync(irq);
192	irq_desc[irq].handler = &pint_irq_type;
193	disable_pint_irq(irq);
194}
195#endif
196
197void __init init_IRQ(void)
198{
199#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
200    defined(CONFIG_CPU_SUBTYPE_SH7707) || \
201    defined(CONFIG_CPU_SUBTYPE_SH7709)
202	int i;
203#endif
204
205	make_ipr_irq(TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY);
206	make_ipr_irq(TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY);
207#if defined(CONFIG_SH_RTC)
208	make_ipr_irq(RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY);
209#endif
210
211#ifdef SCI_ERI_IRQ
212	make_ipr_irq(SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
213	make_ipr_irq(SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
214	make_ipr_irq(SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
215#endif
216
217#ifdef SCIF1_ERI_IRQ
218	make_ipr_irq(SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
219	make_ipr_irq(SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
220	make_ipr_irq(SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
221	make_ipr_irq(SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
222#endif
223
224#if defined(CONFIG_CPU_SUBTYPE_SH7300)
225	make_ipr_irq(SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY);
226	make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
227	make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
228	make_ipr_irq(VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
229#endif
230
231#ifdef SCIF_ERI_IRQ
232	make_ipr_irq(SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
233	make_ipr_irq(SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
234	make_ipr_irq(SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
235	make_ipr_irq(SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
236#endif
237
238#ifdef IRDA_ERI_IRQ
239	make_ipr_irq(IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
240	make_ipr_irq(IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
241	make_ipr_irq(IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
242	make_ipr_irq(IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
243#endif
244
245#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
246    defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
247	/*
248	 * Initialize the Interrupt Controller (INTC)
249	 * registers to their power on values
250	 */
251
252	/*
253	 * Enable external irq (INTC IRQ mode).
254	 * You should set corresponding bits of PFC to "00"
255	 * to enable these interrupts.
256	 */
257	make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY);
258	make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY);
259	make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY);
260	make_ipr_irq(IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY);
261	make_ipr_irq(IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY);
262	make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY);
263#if !defined(CONFIG_CPU_SUBTYPE_SH7300)
264	make_ipr_irq(PINT0_IRQ, PINT0_IPR_ADDR, PINT0_IPR_POS, PINT0_PRIORITY);
265	make_ipr_irq(PINT8_IRQ, PINT8_IPR_ADDR, PINT8_IPR_POS, PINT8_PRIORITY);
266	enable_ipr_irq(PINT0_IRQ);
267	enable_ipr_irq(PINT8_IRQ);
268
269	for(i = 0; i < 16; i++)
270		make_pint_irq(PINT_IRQ_BASE + i);
271	for(i = 0; i < 256; i++)
272	{
273		if(i & 1) pint_map[i] = 0;
274		else if(i & 2) pint_map[i] = 1;
275		else if(i & 4) pint_map[i] = 2;
276		else if(i & 8) pint_map[i] = 3;
277		else if(i & 0x10) pint_map[i] = 4;
278		else if(i & 0x20) pint_map[i] = 5;
279		else if(i & 0x40) pint_map[i] = 6;
280		else if(i & 0x80) pint_map[i] = 7;
281	}
282#endif /* !CONFIG_CPU_SUBTYPE_SH7300 */
283#endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709  || CONFIG_CPU_SUBTYPE_SH7300*/
284
285#ifdef CONFIG_CPU_SUBTYPE_ST40
286	init_IRQ_intc2();
287#endif
288
289	/* Perform the machine specific initialisation */
290	if (sh_mv.mv_init_irq != NULL) {
291		sh_mv.mv_init_irq();
292	}
293}
294#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
295    defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
296int ipr_irq_demux(int irq)
297{
298#if !defined(CONFIG_CPU_SUBTYPE_SH7300)
299	unsigned long creg, dreg, d, sav;
300
301	if(irq == PINT0_IRQ)
302	{
303#if defined(CONFIG_CPU_SUBTYPE_SH7707)
304		creg = PORT_PACR;
305		dreg = PORT_PADR;
306#else
307		creg = PORT_PCCR;
308		dreg = PORT_PCDR;
309#endif
310		sav = ctrl_inw(creg);
311		ctrl_outw(sav | portcr_mask, creg);
312		d = (~ctrl_inb(dreg) ^ ctrl_inw(INTC_ICR2)) & ctrl_inw(INTC_INTER) & 0xff;
313		ctrl_outw(sav, creg);
314		if(d == 0) return irq;
315		return PINT_IRQ_BASE + pint_map[d];
316	}
317	else if(irq == PINT8_IRQ)
318	{
319#if defined(CONFIG_CPU_SUBTYPE_SH7707)
320		creg = PORT_PBCR;
321		dreg = PORT_PBDR;
322#else
323		creg = PORT_PFCR;
324		dreg = PORT_PFDR;
325#endif
326		sav = ctrl_inw(creg);
327		ctrl_outw(sav | (portcr_mask >> 16), creg);
328		d = (~ctrl_inb(dreg) ^ (ctrl_inw(INTC_ICR2) >> 8)) & (ctrl_inw(INTC_INTER) >> 8) & 0xff;
329		ctrl_outw(sav, creg);
330		if(d == 0) return irq;
331		return PINT_IRQ_BASE + 8 + pint_map[d];
332	}
333#endif
334	return irq;
335}
336#endif
337
338EXPORT_SYMBOL(make_ipr_irq);
339