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/arch/ppc64/xmon/ppc.h

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  1/* ppc.h -- Header file for PowerPC opcode table
  2   Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003
  3   Free Software Foundation, Inc.
  4   Written by Ian Lance Taylor, Cygnus Support
  5
  6This file is part of GDB, GAS, and the GNU binutils.
  7
  8GDB, GAS, and the GNU binutils are free software; you can redistribute
  9them and/or modify them under the terms of the GNU General Public
 10License as published by the Free Software Foundation; either version
 111, or (at your option) any later version.
 12
 13GDB, GAS, and the GNU binutils are distributed in the hope that they
 14will be useful, but WITHOUT ANY WARRANTY; without even the implied
 15warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
 16the GNU General Public License for more details.
 17
 18You should have received a copy of the GNU General Public License
 19along with this file; see the file COPYING.  If not, write to the Free
 20Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 21
 22#ifndef PPC_H
 23#define PPC_H
 24
 25/* The opcode table is an array of struct powerpc_opcode.  */
 26
 27struct powerpc_opcode
 28{
 29  /* The opcode name.  */
 30  const char *name;
 31
 32  /* The opcode itself.  Those bits which will be filled in with
 33     operands are zeroes.  */
 34  unsigned long opcode;
 35
 36  /* The opcode mask.  This is used by the disassembler.  This is a
 37     mask containing ones indicating those bits which must match the
 38     opcode field, and zeroes indicating those bits which need not
 39     match (and are presumably filled in by operands).  */
 40  unsigned long mask;
 41
 42  /* One bit flags for the opcode.  These are used to indicate which
 43     specific processors support the instructions.  The defined values
 44     are listed below.  */
 45  unsigned long flags;
 46
 47  /* An array of operand codes.  Each code is an index into the
 48     operand table.  They appear in the order which the operands must
 49     appear in assembly code, and are terminated by a zero.  */
 50  unsigned char operands[8];
 51};
 52
 53/* The table itself is sorted by major opcode number, and is otherwise
 54   in the order in which the disassembler should consider
 55   instructions.  */
 56extern const struct powerpc_opcode powerpc_opcodes[];
 57extern const int powerpc_num_opcodes;
 58
 59/* Values defined for the flags field of a struct powerpc_opcode.  */
 60
 61/* Opcode is defined for the PowerPC architecture.  */
 62#define PPC_OPCODE_PPC			 1
 63
 64/* Opcode is defined for the POWER (RS/6000) architecture.  */
 65#define PPC_OPCODE_POWER		 2
 66
 67/* Opcode is defined for the POWER2 (Rios 2) architecture.  */
 68#define PPC_OPCODE_POWER2		 4
 69
 70/* Opcode is only defined on 32 bit architectures.  */
 71#define PPC_OPCODE_32			 8
 72
 73/* Opcode is only defined on 64 bit architectures.  */
 74#define PPC_OPCODE_64		      0x10
 75
 76/* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
 77   is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
 78   but it also supports many additional POWER instructions.  */
 79#define PPC_OPCODE_601		      0x20
 80
 81/* Opcode is supported in both the Power and PowerPC architectures
 82   (ie, compiler's -mcpu=common or assembler's -mcom).  */
 83#define PPC_OPCODE_COMMON	      0x40
 84
 85/* Opcode is supported for any Power or PowerPC platform (this is
 86   for the assembler's -many option, and it eliminates duplicates).  */
 87#define PPC_OPCODE_ANY		      0x80
 88
 89/* Opcode is supported as part of the 64-bit bridge.  */
 90#define PPC_OPCODE_64_BRIDGE	     0x100
 91
 92/* Opcode is supported by Altivec Vector Unit */
 93#define PPC_OPCODE_ALTIVEC	     0x200
 94
 95/* Opcode is supported by PowerPC 403 processor.  */
 96#define PPC_OPCODE_403		     0x400
 97
 98/* Opcode is supported by PowerPC BookE processor.  */
 99#define PPC_OPCODE_BOOKE	     0x800
100
101/* Opcode is only supported by 64-bit PowerPC BookE processor.  */
102#define PPC_OPCODE_BOOKE64	    0x1000
103
104/* Opcode is supported by PowerPC 440 processor.  */
105#define PPC_OPCODE_440		    0x2000
106
107/* Opcode is only supported by Power4 architecture.  */
108#define PPC_OPCODE_POWER4	    0x4000
109
110/* Opcode isn't supported by Power4 architecture.  */
111#define PPC_OPCODE_NOPOWER4	    0x8000
112
113/* Opcode is only supported by POWERPC Classic architecture.  */
114#define PPC_OPCODE_CLASSIC	   0x10000
115
116/* Opcode is only supported by e500x2 Core.  */
117#define PPC_OPCODE_SPE		   0x20000
118
119/* Opcode is supported by e500x2 Integer select APU.  */
120#define PPC_OPCODE_ISEL		   0x40000
121
122/* Opcode is an e500 SPE floating point instruction.  */
123#define PPC_OPCODE_EFS		   0x80000
124
125/* Opcode is supported by branch locking APU.  */
126#define PPC_OPCODE_BRLOCK	  0x100000
127
128/* Opcode is supported by performance monitor APU.  */
129#define PPC_OPCODE_PMR		  0x200000
130
131/* Opcode is supported by cache locking APU.  */
132#define PPC_OPCODE_CACHELCK	  0x400000
133
134/* Opcode is supported by machine check APU.  */
135#define PPC_OPCODE_RFMCI	  0x800000
136
137/* A macro to extract the major opcode from an instruction.  */
138#define PPC_OP(i) (((i) >> 26) & 0x3f)
139
140/* The operands table is an array of struct powerpc_operand.  */
141
142struct powerpc_operand
143{
144  /* The number of bits in the operand.  */
145  int bits;
146
147  /* How far the operand is left shifted in the instruction.  */
148  int shift;
149
150  /* Insertion function.  This is used by the assembler.  To insert an
151     operand value into an instruction, check this field.
152
153     If it is NULL, execute
154         i |= (op & ((1 << o->bits) - 1)) << o->shift;
155     (i is the instruction which we are filling in, o is a pointer to
156     this structure, and op is the opcode value; this assumes twos
157     complement arithmetic).
158
159     If this field is not NULL, then simply call it with the
160     instruction and the operand value.  It will return the new value
161     of the instruction.  If the ERRMSG argument is not NULL, then if
162     the operand value is illegal, *ERRMSG will be set to a warning
163     string (the operand will be inserted in any case).  If the
164     operand value is legal, *ERRMSG will be unchanged (most operands
165     can accept any value).  */
166  unsigned long (*insert)
167    (unsigned long instruction, long op, int dialect, const char **errmsg);
168
169  /* Extraction function.  This is used by the disassembler.  To
170     extract this operand type from an instruction, check this field.
171
172     If it is NULL, compute
173         op = ((i) >> o->shift) & ((1 << o->bits) - 1);
174	 if ((o->flags & PPC_OPERAND_SIGNED) != 0
175	     && (op & (1 << (o->bits - 1))) != 0)
176	   op -= 1 << o->bits;
177     (i is the instruction, o is a pointer to this structure, and op
178     is the result; this assumes twos complement arithmetic).
179
180     If this field is not NULL, then simply call it with the
181     instruction value.  It will return the value of the operand.  If
182     the INVALID argument is not NULL, *INVALID will be set to
183     non-zero if this operand type can not actually be extracted from
184     this operand (i.e., the instruction does not match).  If the
185     operand is valid, *INVALID will not be changed.  */
186  long (*extract) (unsigned long instruction, int dialect, int *invalid);
187
188  /* One bit syntax flags.  */
189  unsigned long flags;
190};
191
192/* Elements in the table are retrieved by indexing with values from
193   the operands field of the powerpc_opcodes table.  */
194
195extern const struct powerpc_operand powerpc_operands[];
196
197/* Values defined for the flags field of a struct powerpc_operand.  */
198
199/* This operand takes signed values.  */
200#define PPC_OPERAND_SIGNED (01)
201
202/* This operand takes signed values, but also accepts a full positive
203   range of values when running in 32 bit mode.  That is, if bits is
204   16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
205   this flag is ignored.  */
206#define PPC_OPERAND_SIGNOPT (02)
207
208/* This operand does not actually exist in the assembler input.  This
209   is used to support extended mnemonics such as mr, for which two
210   operands fields are identical.  The assembler should call the
211   insert function with any op value.  The disassembler should call
212   the extract function, ignore the return value, and check the value
213   placed in the valid argument.  */
214#define PPC_OPERAND_FAKE (04)
215
216/* The next operand should be wrapped in parentheses rather than
217   separated from this one by a comma.  This is used for the load and
218   store instructions which want their operands to look like
219       reg,displacement(reg)
220   */
221#define PPC_OPERAND_PARENS (010)
222
223/* This operand may use the symbolic names for the CR fields, which
224   are
225       lt  0	gt  1	eq  2	so  3	un  3
226       cr0 0	cr1 1	cr2 2	cr3 3
227       cr4 4	cr5 5	cr6 6	cr7 7
228   These may be combined arithmetically, as in cr2*4+gt.  These are
229   only supported on the PowerPC, not the POWER.  */
230#define PPC_OPERAND_CR (020)
231
232/* This operand names a register.  The disassembler uses this to print
233   register names with a leading 'r'.  */
234#define PPC_OPERAND_GPR (040)
235
236/* This operand names a floating point register.  The disassembler
237   prints these with a leading 'f'.  */
238#define PPC_OPERAND_FPR (0100)
239
240/* This operand is a relative branch displacement.  The disassembler
241   prints these symbolically if possible.  */
242#define PPC_OPERAND_RELATIVE (0200)
243
244/* This operand is an absolute branch address.  The disassembler
245   prints these symbolically if possible.  */
246#define PPC_OPERAND_ABSOLUTE (0400)
247
248/* This operand is optional, and is zero if omitted.  This is used for
249   the optional BF and L fields in the comparison instructions.  The
250   assembler must count the number of operands remaining on the line,
251   and the number of operands remaining for the opcode, and decide
252   whether this operand is present or not.  The disassembler should
253   print this operand out only if it is not zero.  */
254#define PPC_OPERAND_OPTIONAL (01000)
255
256/* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
257   is omitted, then for the next operand use this operand value plus
258   1, ignoring the next operand field for the opcode.  This wretched
259   hack is needed because the Power rotate instructions can take
260   either 4 or 5 operands.  The disassembler should print this operand
261   out regardless of the PPC_OPERAND_OPTIONAL field.  */
262#define PPC_OPERAND_NEXT (02000)
263
264/* This operand should be regarded as a negative number for the
265   purposes of overflow checking (i.e., the normal most negative
266   number is disallowed and one more than the normal most positive
267   number is allowed).  This flag will only be set for a signed
268   operand.  */
269#define PPC_OPERAND_NEGATIVE (04000)
270
271/* This operand names a vector unit register.  The disassembler
272   prints these with a leading 'v'.  */
273#define PPC_OPERAND_VR (010000)
274
275/* This operand is for the DS field in a DS form instruction.  */
276#define PPC_OPERAND_DS (020000)
277
278/* This operand is for the DQ field in a DQ form instruction.  */
279#define PPC_OPERAND_DQ (040000)
280
281/* The POWER and PowerPC assemblers use a few macros.  We keep them
282   with the operands table for simplicity.  The macro table is an
283   array of struct powerpc_macro.  */
284
285struct powerpc_macro
286{
287  /* The macro name.  */
288  const char *name;
289
290  /* The number of operands the macro takes.  */
291  unsigned int operands;
292
293  /* One bit flags for the opcode.  These are used to indicate which
294     specific processors support the instructions.  The values are the
295     same as those for the struct powerpc_opcode flags field.  */
296  unsigned long flags;
297
298  /* A format string to turn the macro into a normal instruction.
299     Each %N in the string is replaced with operand number N (zero
300     based).  */
301  const char *format;
302};
303
304extern const struct powerpc_macro powerpc_macros[];
305extern const int powerpc_num_macros;
306
307#endif /* PPC_H */