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/arch/ppc/platforms/sbc82xx.c

https://bitbucket.org/evzijst/gittest
C | 259 lines | 170 code | 51 blank | 38 comment | 12 complexity | 71fb3642f186fd48b538a74cc8f672bf MD5 | raw file
  1/*
  2 * arch/ppc/platforms/sbc82xx.c
  3 *
  4 * SBC82XX platform support
  5 *
  6 * Author: Guy Streeter <streeter@redhat.com>
  7 *
  8 * Derived from: est8260_setup.c by Allen Curtis, ONZ
  9 *
 10 * Copyright 2004 Red Hat, Inc.
 11 *
 12 * This program is free software; you can redistribute  it and/or modify it
 13 * under  the terms of  the GNU General  Public License as published by the
 14 * Free Software Foundation;  either version 2 of the  License, or (at your
 15 * option) any later version.
 16 */
 17
 18#include <linux/config.h>
 19#include <linux/stddef.h>
 20#include <linux/interrupt.h>
 21#include <linux/irq.h>
 22#include <linux/init.h>
 23#include <linux/pci.h>
 24
 25#include <asm/mpc8260.h>
 26#include <asm/machdep.h>
 27#include <asm/io.h>
 28#include <asm/todc.h>
 29#include <asm/immap_cpm2.h>
 30#include <asm/pci.h>
 31
 32static void (*callback_init_IRQ)(void);
 33
 34extern unsigned char __res[sizeof(bd_t)];
 35
 36extern void (*late_time_init)(void);
 37
 38#ifdef CONFIG_GEN_RTC
 39TODC_ALLOC();
 40
 41/*
 42 * Timer init happens before mem_init but after paging init, so we cannot
 43 * directly use ioremap() at that time.
 44 * late_time_init() is call after paging init.
 45 */
 46
 47static void sbc82xx_time_init(void)
 48{
 49	volatile memctl_cpm2_t *mc = &cpm2_immr->im_memctl;
 50
 51	/* Set up CS11 for RTC chip */
 52	mc->memc_br11=0;
 53	mc->memc_or11=0xffff0836;
 54	mc->memc_br11=SBC82xx_TODC_NVRAM_ADDR | 0x0801;
 55
 56	TODC_INIT(TODC_TYPE_MK48T59, 0, 0, SBC82xx_TODC_NVRAM_ADDR, 0);
 57
 58	todc_info->nvram_data =
 59		(unsigned int)ioremap(todc_info->nvram_data, 0x2000);
 60	BUG_ON(!todc_info->nvram_data);
 61	ppc_md.get_rtc_time	= todc_get_rtc_time;
 62	ppc_md.set_rtc_time	= todc_set_rtc_time;
 63	ppc_md.nvram_read_val	= todc_direct_read_val;
 64	ppc_md.nvram_write_val	= todc_direct_write_val;
 65	todc_time_init();
 66}
 67#endif /* CONFIG_GEN_RTC */
 68
 69static volatile char *sbc82xx_i8259_map;
 70static char sbc82xx_i8259_mask = 0xff;
 71static DEFINE_SPINLOCK(sbc82xx_i8259_lock);
 72
 73static void sbc82xx_i8259_mask_and_ack_irq(unsigned int irq_nr)
 74{
 75	unsigned long flags;
 76
 77	irq_nr -= NR_SIU_INTS;
 78
 79	spin_lock_irqsave(&sbc82xx_i8259_lock, flags);
 80	sbc82xx_i8259_mask |= 1 << irq_nr;
 81	(void) sbc82xx_i8259_map[1];	/* Dummy read */
 82	sbc82xx_i8259_map[1] = sbc82xx_i8259_mask;
 83	sbc82xx_i8259_map[0] = 0x20;	/* OCW2: Non-specific EOI */
 84	spin_unlock_irqrestore(&sbc82xx_i8259_lock, flags);
 85}
 86
 87static void sbc82xx_i8259_mask_irq(unsigned int irq_nr)
 88{
 89	unsigned long flags;
 90
 91	irq_nr -= NR_SIU_INTS;
 92
 93	spin_lock_irqsave(&sbc82xx_i8259_lock, flags);
 94	sbc82xx_i8259_mask |= 1 << irq_nr;
 95	sbc82xx_i8259_map[1] = sbc82xx_i8259_mask;
 96	spin_unlock_irqrestore(&sbc82xx_i8259_lock, flags);
 97}
 98
 99static void sbc82xx_i8259_unmask_irq(unsigned int irq_nr)
100{
101	unsigned long flags;
102
103	irq_nr -= NR_SIU_INTS;
104
105	spin_lock_irqsave(&sbc82xx_i8259_lock, flags);
106	sbc82xx_i8259_mask &= ~(1 << irq_nr);
107	sbc82xx_i8259_map[1] = sbc82xx_i8259_mask;
108	spin_unlock_irqrestore(&sbc82xx_i8259_lock, flags);
109}
110
111static void sbc82xx_i8259_end_irq(unsigned int irq)
112{
113	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))
114	    && irq_desc[irq].action)
115		sbc82xx_i8259_unmask_irq(irq);
116}
117
118
119struct hw_interrupt_type sbc82xx_i8259_ic = {
120	.typename = " i8259     ",
121	.enable = sbc82xx_i8259_unmask_irq,
122	.disable = sbc82xx_i8259_mask_irq,
123	.ack = sbc82xx_i8259_mask_and_ack_irq,
124	.end = sbc82xx_i8259_end_irq,
125};
126
127static irqreturn_t sbc82xx_i8259_demux(int irq, void *dev_id, struct pt_regs *regs)
128{
129	spin_lock(&sbc82xx_i8259_lock);
130
131	sbc82xx_i8259_map[0] = 0x0c;	/* OCW3: Read IR register on RD# pulse */
132	irq = sbc82xx_i8259_map[0] & 7;	/* Read IRR */
133
134	if (irq == 7) {
135		/* Possible spurious interrupt */
136		int isr;
137		sbc82xx_i8259_map[0] = 0x0b;	/* OCW3: Read IS register on RD# pulse */
138		isr = sbc82xx_i8259_map[0];	/* Read ISR */
139
140		if (!(isr & 0x80)) {
141			printk(KERN_INFO "Spurious i8259 interrupt\n");
142			return IRQ_HANDLED;
143		}
144	}
145	__do_IRQ(NR_SIU_INTS + irq, regs);
146	return IRQ_HANDLED;
147}
148
149static struct irqaction sbc82xx_i8259_irqaction = {
150	.handler = sbc82xx_i8259_demux,
151	.flags = SA_INTERRUPT,
152	.mask = CPU_MASK_NONE,
153	.name = "i8259 demux",
154};
155
156void __init sbc82xx_init_IRQ(void)
157{
158	volatile memctl_cpm2_t *mc = &cpm2_immr->im_memctl;
159	volatile intctl_cpm2_t *ic = &cpm2_immr->im_intctl;
160	int i;
161
162	callback_init_IRQ();
163
164	/* u-boot doesn't always set the board up correctly */
165	mc->memc_br5 = 0;
166	mc->memc_or5 = 0xfff00856;
167	mc->memc_br5 = 0x22000801;
168
169	sbc82xx_i8259_map = ioremap(0x22008000, 2);
170	if (!sbc82xx_i8259_map) {
171		printk(KERN_CRIT "Mapping i8259 interrupt controller failed\n");
172		return;
173	}
174	
175	/* Set up the interrupt handlers for the i8259 IRQs */
176	for (i = NR_SIU_INTS; i < NR_SIU_INTS + 8; i++) {
177                irq_desc[i].handler = &sbc82xx_i8259_ic;
178		irq_desc[i].status |= IRQ_LEVEL;
179	}
180
181	/* make IRQ6 level sensitive */
182	ic->ic_siexr &= ~(1 << (14 - (SIU_INT_IRQ6 - SIU_INT_IRQ1)));
183	irq_desc[SIU_INT_IRQ6].status |= IRQ_LEVEL;
184
185	/* Initialise the i8259 */
186	sbc82xx_i8259_map[0] = 0x1b;	/* ICW1: Level, no cascade, ICW4 */
187	sbc82xx_i8259_map[1] = 0x00;	/* ICW2: vector base */
188					/* No ICW3 (no cascade) */
189	sbc82xx_i8259_map[1] = 0x01;	/* ICW4: 8086 mode, normal EOI */
190
191	sbc82xx_i8259_map[0] = 0x0b;	/* OCW3: Read IS register on RD# pulse */
192
193	sbc82xx_i8259_map[1] = sbc82xx_i8259_mask; /* Set interrupt mask */
194
195	/* Request cascade IRQ */
196	if (setup_irq(SIU_INT_IRQ6, &sbc82xx_i8259_irqaction)) {
197		printk("Installation of i8259 IRQ demultiplexer failed.\n");
198	}
199}
200
201static int sbc82xx_pci_map_irq(struct pci_dev *dev, unsigned char idsel,
202			       unsigned char pin)
203{
204	static char pci_irq_table[][4] = {
205		/*
206		 * PCI IDSEL/INTPIN->INTLINE
207		 *  A      B      C      D
208		 */
209		{ SBC82xx_PIRQA, SBC82xx_PIRQB, SBC82xx_PIRQC, SBC82xx_PIRQD },	/* IDSEL 16 - PMC slot */
210		{ SBC82xx_PC_IRQA, SBC82xx_PC_IRQB, -1,  -1  },			/* IDSEL 17 - CardBus */
211		{ SBC82xx_PIRQA, SBC82xx_PIRQB, SBC82xx_PIRQC, SBC82xx_PIRQD }, /* IDSEL 18 - PCI-X bridge */
212	};
213
214	const long min_idsel = 16, max_idsel = 18, irqs_per_slot = 4;
215
216	return PCI_IRQ_TABLE_LOOKUP;
217}
218
219static void __devinit quirk_sbc8260_cardbus(struct pci_dev *pdev)
220{
221	uint32_t ctrl;
222
223	if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(17, 0))
224		return;
225
226	printk(KERN_INFO "Setting up CardBus controller\n");
227
228	/* Set P2CCLK bit in System Control Register */
229	pci_read_config_dword(pdev, 0x80, &ctrl);
230	ctrl |= (1<<27);
231	pci_write_config_dword(pdev, 0x80, ctrl);
232
233	/* Set MFUNC up for PCI IRQ routing via INTA and INTB, and LEDs. */
234	pci_write_config_dword(pdev, 0x8c, 0x00c01d22);
235
236}
237DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1420, quirk_sbc8260_cardbus);
238
239void __init
240m82xx_board_init(void)
241{
242	/* u-boot may be using one of the FCC Ethernet devices.
243	   Use the MAC address to the SCC. */
244	__res[offsetof(bd_t, bi_enetaddr[5])] &= ~3;
245
246	/* Anything special for this platform */
247	callback_init_IRQ	= ppc_md.init_IRQ;
248
249	ppc_md.init_IRQ		= sbc82xx_init_IRQ;
250	ppc_md.pci_map_irq	= sbc82xx_pci_map_irq;
251#ifdef CONFIG_GEN_RTC
252	ppc_md.time_init        = NULL;
253	ppc_md.get_rtc_time     = NULL;
254	ppc_md.set_rtc_time     = NULL;
255	ppc_md.nvram_read_val   = NULL;
256	ppc_md.nvram_write_val  = NULL;
257	late_time_init		= sbc82xx_time_init;
258#endif /* CONFIG_GEN_RTC */
259}