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/arch/ppc/platforms/pplus.c

https://bitbucket.org/evzijst/gittest
C | 917 lines | 629 code | 141 blank | 147 comment | 73 complexity | 572229f36d52dee255343e9af554e192 MD5 | raw file
  1/*
  2 * arch/ppc/platforms/pplus.c
  3 *
  4 * Board and PCI setup routines for MCG PowerPlus
  5 *
  6 * Author: Randy Vinson <rvinson@mvista.com>
  7 *
  8 * Derived from original PowerPlus PReP work by
  9 * Cort Dougan, Johnnie Peters, Matt Porter, and
 10 * Troy Benjegerdes.
 11 *
 12 * 2001-2004 (c) MontaVista, Software, Inc.  This file is licensed under
 13 * the terms of the GNU General Public License version 2.  This program
 14 * is licensed "as is" without any warranty of any kind, whether express
 15 * or implied.
 16 */
 17
 18#include <linux/config.h>
 19#include <linux/kernel.h>
 20#include <linux/interrupt.h>
 21#include <linux/init.h>
 22#include <linux/ioport.h>
 23#include <linux/console.h>
 24#include <linux/pci.h>
 25#include <linux/irq.h>
 26#include <linux/ide.h>
 27#include <linux/seq_file.h>
 28#include <linux/root_dev.h>
 29
 30#include <asm/system.h>
 31#include <asm/io.h>
 32#include <asm/pgtable.h>
 33#include <asm/dma.h>
 34#include <asm/machdep.h>
 35#include <asm/prep_nvram.h>
 36#include <asm/vga.h>
 37#include <asm/i8259.h>
 38#include <asm/open_pic.h>
 39#include <asm/hawk.h>
 40#include <asm/todc.h>
 41#include <asm/bootinfo.h>
 42#include <asm/kgdb.h>
 43#include <asm/reg.h>
 44
 45#include "pplus.h"
 46
 47#undef DUMP_DBATS
 48
 49TODC_ALLOC();
 50
 51extern void pplus_setup_hose(void);
 52extern void pplus_set_VIA_IDE_native(void);
 53
 54extern unsigned long loops_per_jiffy;
 55unsigned char *Motherboard_map_name;
 56
 57/* Tables for known hardware */
 58
 59/* Motorola Mesquite */
 60static inline int
 61mesquite_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 62{
 63	static char pci_irq_table[][4] =
 64	    /*
 65	     *      MPIC interrupts for various IDSEL values (MPIC IRQ0 =
 66	     *      Linux IRQ16 (to leave room for ISA IRQs at 0-15).
 67	     *      PCI IDSEL/INTPIN->INTLINE
 68	     *         A   B   C   D
 69	     */
 70	{
 71		{18,  0,  0,  0},	/* IDSEL 14 - Enet 0 */
 72		{ 0,  0,  0,  0},	/* IDSEL 15 - unused */
 73		{19, 19, 19, 19},	/* IDSEL 16 - PMC Slot 1 */
 74		{ 0,  0,  0,  0},	/* IDSEL 17 - unused */
 75		{ 0,  0,  0,  0},	/* IDSEL 18 - unused */
 76		{ 0,  0,  0,  0},	/* IDSEL 19 - unused */
 77		{24, 25, 26, 27},	/* IDSEL 20 - P2P bridge (to cPCI 1) */
 78		{ 0,  0,  0,  0},	/* IDSEL 21 - unused */
 79		{28, 29, 30, 31}	/* IDSEL 22 - P2P bridge (to cPCI 2) */
 80	};
 81
 82	const long min_idsel = 14, max_idsel = 22, irqs_per_slot = 4;
 83	return PCI_IRQ_TABLE_LOOKUP;
 84}
 85
 86/* Motorola Sitka */
 87static inline int
 88sitka_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 89{
 90	static char pci_irq_table[][4] =
 91	    /*
 92	     *      MPIC interrupts for various IDSEL values (MPIC IRQ0 =
 93	     *      Linux IRQ16 (to leave room for ISA IRQs at 0-15).
 94	     *      PCI IDSEL/INTPIN->INTLINE
 95	     *         A   B   C   D
 96	     */
 97	{
 98		{18,  0,  0,  0},	/* IDSEL 14 - Enet 0 */
 99		{ 0,  0,  0,  0},	/* IDSEL 15 - unused */
100		{25, 26, 27, 28},	/* IDSEL 16 - PMC Slot 1 */
101		{28, 25, 26, 27},	/* IDSEL 17 - PMC Slot 2 */
102		{ 0,  0,  0,  0},	/* IDSEL 18 - unused */
103		{ 0,  0,  0,  0},	/* IDSEL 19 - unused */
104		{20,  0,  0,  0}	/* IDSEL 20 - P2P bridge (to cPCI) */
105	};
106
107	const long min_idsel = 14, max_idsel = 20, irqs_per_slot = 4;
108	return PCI_IRQ_TABLE_LOOKUP;
109}
110
111/* Motorola MTX */
112static inline int
113MTX_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
114{
115	static char pci_irq_table[][4] =
116	    /*
117	     *      MPIC interrupts for various IDSEL values (MPIC IRQ0 =
118	     *      Linux IRQ16 (to leave room for ISA IRQs at 0-15).
119	     *      PCI IDSEL/INTPIN->INTLINE
120	     *         A   B   C   D
121	     */
122	{
123		{19,  0,  0,  0},	/* IDSEL 12 - SCSI   */
124		{ 0,  0,  0,  0},	/* IDSEL 13 - unused */
125		{18,  0,  0,  0},	/* IDSEL 14 - Enet   */
126		{ 0,  0,  0,  0},	/* IDSEL 15 - unused */
127		{25, 26, 27, 28},	/* IDSEL 16 - PMC Slot 1 */
128		{26, 27, 28, 25},	/* IDSEL 17 - PMC Slot 2 */
129		{27, 28, 25, 26}	/* IDSEL 18 - PCI Slot 3 */
130	};
131
132	const long min_idsel = 12, max_idsel = 18, irqs_per_slot = 4;
133	return PCI_IRQ_TABLE_LOOKUP;
134}
135
136/* Motorola MTX Plus */
137/* Secondary bus interrupt routing is not supported yet */
138static inline int
139MTXplus_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
140{
141	static char pci_irq_table[][4] =
142	    /*
143	     *      MPIC interrupts for various IDSEL values (MPIC IRQ0 =
144	     *      Linux IRQ16 (to leave room for ISA IRQs at 0-15).
145	     *      PCI IDSEL/INTPIN->INTLINE
146	     *         A   B   C   D
147	     */
148	{
149		{19,  0,  0,  0},	/* IDSEL 12 - SCSI   */
150		{ 0,  0,  0,  0},	/* IDSEL 13 - unused */
151		{18,  0,  0,  0},	/* IDSEL 14 - Enet 1 */
152		{ 0,  0,  0,  0},	/* IDSEL 15 - unused */
153		{25, 26, 27, 28},	/* IDSEL 16 - PCI Slot 1P */
154		{26, 27, 28, 25},	/* IDSEL 17 - PCI Slot 2P */
155		{27, 28, 25, 26},	/* IDSEL 18 - PCI Slot 3P */
156		{26,  0,  0,  0},	/* IDSEL 19 - Enet 2 */
157		{ 0,  0,  0,  0}	/* IDSEL 20 - P2P Bridge */
158	};
159
160	const long min_idsel = 12, max_idsel = 20, irqs_per_slot = 4;
161	return PCI_IRQ_TABLE_LOOKUP;
162}
163
164static inline int
165Genesis2_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
166{
167	/* 2600
168	 * Raven 31
169	 * ISA   11
170	 * SCSI  12 - IRQ3
171	 * Univ  13
172	 * eth   14 - IRQ2
173	 * VGA   15 - IRQ4
174	 * PMC1  16 - IRQ9,10,11,12 = PMC1 A-D
175	 * PMC2  17 - IRQ12,9,10,11 = A-D
176	 * SCSI2 18 - IRQ11
177	 * eth2  19 - IRQ10
178	 * PCIX  20 - IRQ9,10,11,12 = PCI A-D
179	 */
180
181	/* 2400
182	 * Hawk 31
183	 * ISA  11
184	 * Univ 13
185	 * eth  14 - IRQ2
186	 * PMC1 16 - IRQ9,10,11,12 = PMC A-D
187	 * PMC2 17 - IRQ12,9,10,11 = PMC A-D
188	 * PCIX 20 - IRQ9,10,11,12 = PMC A-D
189	 */
190
191	/* 2300
192	 * Raven 31
193	 * ISA   11
194	 * Univ  13
195	 * eth   14 - IRQ2
196	 * PMC1  16 - 9,10,11,12 = A-D
197	 * PMC2  17 - 9,10,11,12 = B,C,D,A
198	 */
199
200	static char pci_irq_table[][4] =
201	    /*
202	     *      MPIC interrupts for various IDSEL values (MPIC IRQ0 =
203	     *      Linux IRQ16 (to leave room for ISA IRQs at 0-15).
204	     *      PCI IDSEL/INTPIN->INTLINE
205	     *         A   B   C   D
206	     */
207	{
208		{19,  0,  0,  0},	/* IDSEL 12 - SCSI   */
209		{ 0,  0,  0,  0},	/* IDSEL 13 - Universe PCI - VME */
210		{18,  0,  0,  0},	/* IDSEL 14 - Enet 1 */
211		{ 0,  0,  0,  0},	/* IDSEL 15 - unused */
212		{25, 26, 27, 28},	/* IDSEL 16 - PCI/PMC Slot 1P */
213		{28, 25, 26, 27},	/* IDSEL 17 - PCI/PMC Slot 2P */
214		{27, 28, 25, 26},	/* IDSEL 18 - PCI Slot 3P */
215		{26,  0,  0,  0},	/* IDSEL 19 - Enet 2 */
216		{25, 26, 27, 28}	/* IDSEL 20 - P2P Bridge */
217	};
218
219	const long min_idsel = 12, max_idsel = 20, irqs_per_slot = 4;
220	return PCI_IRQ_TABLE_LOOKUP;
221}
222
223#define MOTOROLA_CPUTYPE_REG	0x800
224#define MOTOROLA_BASETYPE_REG	0x803
225#define MPIC_RAVEN_ID		0x48010000
226#define	MPIC_HAWK_ID		0x48030000
227#define	MOT_PROC2_BIT		0x800
228
229static u_char pplus_openpic_initsenses[] __initdata = {
230	(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* MVME2600_INT_SIO */
231	(IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE),/*MVME2600_INT_FALCN_ECC_ERR */
232	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/*MVME2600_INT_PCI_ETHERNET */
233	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_SCSI */
234	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/*MVME2600_INT_PCI_GRAPHICS */
235	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME0 */
236	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME1 */
237	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME2 */
238	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME3 */
239	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTA */
240	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTB */
241	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTC */
242	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTD */
243	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG0 */
244	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG1 */
245	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),
246};
247
248int mot_entry = -1;
249int prep_keybd_present = 1;
250int mot_multi = 0;
251
252struct brd_info {
253	/* 0x100 mask assumes for Raven and Hawk boards that the level/edge
254	 * are set */
255	int cpu_type;
256	/* 0x200 if this board has a Hawk chip. */
257	int base_type;
258	/* or'ed with 0x80 if this board should be checked for multi CPU */
259	int max_cpu;
260	const char *name;
261	int (*map_irq) (struct pci_dev *, unsigned char, unsigned char);
262};
263struct brd_info mot_info[] = {
264	{0x300, 0x00, 0x00, "MVME 2400", Genesis2_map_irq},
265	{0x1E0, 0xE0, 0x00, "Mesquite cPCI (MCP750)", mesquite_map_irq},
266	{0x1E0, 0xE1, 0x00, "Sitka cPCI (MCPN750)", sitka_map_irq},
267	{0x1E0, 0xE2, 0x00, "Mesquite cPCI (MCP750) w/ HAC", mesquite_map_irq},
268	{0x1E0, 0xF6, 0x80, "MTX Plus", MTXplus_map_irq},
269	{0x1E0, 0xF6, 0x81, "Dual MTX Plus", MTXplus_map_irq},
270	{0x1E0, 0xF7, 0x80, "MTX wo/ Parallel Port", MTX_map_irq},
271	{0x1E0, 0xF7, 0x81, "Dual MTX wo/ Parallel Port", MTX_map_irq},
272	{0x1E0, 0xF8, 0x80, "MTX w/ Parallel Port", MTX_map_irq},
273	{0x1E0, 0xF8, 0x81, "Dual MTX w/ Parallel Port", MTX_map_irq},
274	{0x1E0, 0xF9, 0x00, "MVME 2300", Genesis2_map_irq},
275	{0x1E0, 0xFA, 0x00, "MVME 2300SC/2600", Genesis2_map_irq},
276	{0x1E0, 0xFB, 0x00, "MVME 2600 with MVME712M", Genesis2_map_irq},
277	{0x1E0, 0xFC, 0x00, "MVME 2600/2700 with MVME761", Genesis2_map_irq},
278	{0x1E0, 0xFD, 0x80, "MVME 3600 with MVME712M", Genesis2_map_irq},
279	{0x1E0, 0xFD, 0x81, "MVME 4600 with MVME712M", Genesis2_map_irq},
280	{0x1E0, 0xFE, 0x80, "MVME 3600 with MVME761", Genesis2_map_irq},
281	{0x1E0, 0xFE, 0x81, "MVME 4600 with MVME761", Genesis2_map_irq},
282	{0x000, 0x00, 0x00, "", NULL}
283};
284
285void __init pplus_set_board_type(void)
286{
287	unsigned char cpu_type;
288	unsigned char base_mod;
289	int entry;
290	unsigned short devid;
291	unsigned long *ProcInfo = NULL;
292
293	cpu_type = inb(MOTOROLA_CPUTYPE_REG) & 0xF0;
294	base_mod = inb(MOTOROLA_BASETYPE_REG);
295	early_read_config_word(0, 0, 0, PCI_VENDOR_ID, &devid);
296
297	for (entry = 0; mot_info[entry].cpu_type != 0; entry++) {
298		/* Check for Hawk chip */
299		if (mot_info[entry].cpu_type & 0x200) {
300			if (devid != PCI_DEVICE_ID_MOTOROLA_HAWK)
301				continue;
302		} else {
303			/* store the system config register for later use. */
304			ProcInfo =
305			    (unsigned long *)ioremap(PPLUS_SYS_CONFIG_REG, 4);
306
307			/* Check non hawk boards */
308			if ((mot_info[entry].cpu_type & 0xff) != cpu_type)
309				continue;
310
311			if (mot_info[entry].base_type == 0) {
312				mot_entry = entry;
313				break;
314			}
315
316			if (mot_info[entry].base_type != base_mod)
317				continue;
318		}
319
320		if (!(mot_info[entry].max_cpu & 0x80)) {
321			mot_entry = entry;
322			break;
323		}
324
325		/* processor 1 not present and max processor zero indicated */
326		if ((*ProcInfo & MOT_PROC2_BIT)
327		    && !(mot_info[entry].max_cpu & 0x7f)) {
328			mot_entry = entry;
329			break;
330		}
331
332		/* processor 1 present and max processor zero indicated */
333		if (!(*ProcInfo & MOT_PROC2_BIT)
334		    && (mot_info[entry].max_cpu & 0x7f)) {
335			mot_entry = entry;
336			break;
337		}
338
339		/* Indicate to system if this is a multiprocessor board */
340		if (!(*ProcInfo & MOT_PROC2_BIT))
341			mot_multi = 1;
342	}
343
344	if (mot_entry == -1)
345		/* No particular cpu type found - assume Mesquite (MCP750) */
346		mot_entry = 1;
347
348	Motherboard_map_name = (unsigned char *)mot_info[mot_entry].name;
349	ppc_md.pci_map_irq = mot_info[mot_entry].map_irq;
350}
351void __init pplus_pib_init(void)
352{
353	unsigned char reg;
354	unsigned short short_reg;
355
356	struct pci_dev *dev = NULL;
357
358	/*
359	 * Perform specific configuration for the Via Tech or
360	 * or Winbond PCI-ISA-Bridge part.
361	 */
362	if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
363				   PCI_DEVICE_ID_VIA_82C586_1, dev))) {
364		/*
365		 * PPCBUG does not set the enable bits
366		 * for the IDE device. Force them on here.
367		 */
368		pci_read_config_byte(dev, 0x40, &reg);
369
370		reg |= 0x03;	/* IDE: Chip Enable Bits */
371		pci_write_config_byte(dev, 0x40, reg);
372	}
373
374	if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
375				   PCI_DEVICE_ID_VIA_82C586_2,
376				   dev)) && (dev->devfn = 0x5a)) {
377		/* Force correct USB interrupt */
378		dev->irq = 11;
379		pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
380	}
381
382	if ((dev = pci_get_device(PCI_VENDOR_ID_WINBOND,
383				   PCI_DEVICE_ID_WINBOND_83C553, dev))) {
384		/* Clear PCI Interrupt Routing Control Register. */
385		short_reg = 0x0000;
386		pci_write_config_word(dev, 0x44, short_reg);
387		/* Route IDE interrupts to IRQ 14 */
388		reg = 0xEE;
389		pci_write_config_byte(dev, 0x43, reg);
390	}
391
392	if ((dev = pci_get_device(PCI_VENDOR_ID_WINBOND,
393				   PCI_DEVICE_ID_WINBOND_82C105, dev))) {
394		/*
395		 * Disable LEGIRQ mode so PCI INTS are routed
396		 * directly to the 8259 and enable both channels
397		 */
398		pci_write_config_dword(dev, 0x40, 0x10ff0033);
399
400		/* Force correct IDE interrupt */
401		dev->irq = 14;
402		pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
403	}
404	pci_dev_put(dev);
405}
406
407void __init pplus_set_VIA_IDE_legacy(void)
408{
409	unsigned short vend, dev;
410
411	early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_VENDOR_ID, &vend);
412	early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_DEVICE_ID, &dev);
413
414	if ((vend == PCI_VENDOR_ID_VIA) &&
415			(dev == PCI_DEVICE_ID_VIA_82C586_1)) {
416		unsigned char temp;
417
418		/* put back original "standard" port base addresses */
419		early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
420					 PCI_BASE_ADDRESS_0, 0x1f1);
421		early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
422					 PCI_BASE_ADDRESS_1, 0x3f5);
423		early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
424					 PCI_BASE_ADDRESS_2, 0x171);
425		early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
426					 PCI_BASE_ADDRESS_3, 0x375);
427		early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
428					 PCI_BASE_ADDRESS_4, 0xcc01);
429
430		/* put into legacy mode */
431		early_read_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
432				       &temp);
433		temp &= ~0x05;
434		early_write_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
435					temp);
436	}
437}
438
439void pplus_set_VIA_IDE_native(void)
440{
441	unsigned short vend, dev;
442
443	early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_VENDOR_ID, &vend);
444	early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_DEVICE_ID, &dev);
445
446	if ((vend == PCI_VENDOR_ID_VIA) &&
447			(dev == PCI_DEVICE_ID_VIA_82C586_1)) {
448		unsigned char temp;
449
450		/* put into native mode */
451		early_read_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
452				       &temp);
453		temp |= 0x05;
454		early_write_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
455					temp);
456	}
457}
458
459void __init pplus_pcibios_fixup(void)
460{
461
462	unsigned char reg;
463	unsigned short devid;
464	unsigned char base_mod;
465
466	printk(KERN_INFO "Setting PCI interrupts for a \"%s\"\n",
467			Motherboard_map_name);
468
469	/* Setup the Winbond or Via PIB */
470	pplus_pib_init();
471
472	/* Set up floppy in PS/2 mode */
473	outb(0x09, SIO_CONFIG_RA);
474	reg = inb(SIO_CONFIG_RD);
475	reg = (reg & 0x3F) | 0x40;
476	outb(reg, SIO_CONFIG_RD);
477	outb(reg, SIO_CONFIG_RD);	/* Have to write twice to change! */
478
479	/* This is a hack.  If this is a 2300 or 2400 mot board then there is
480	 * no keyboard controller and we have to indicate that.
481	 */
482
483	early_read_config_word(0, 0, 0, PCI_VENDOR_ID, &devid);
484	base_mod = inb(MOTOROLA_BASETYPE_REG);
485	if ((devid == PCI_DEVICE_ID_MOTOROLA_HAWK) ||
486	    (base_mod == 0xF9) || (base_mod == 0xFA) || (base_mod == 0xE1))
487		prep_keybd_present = 0;
488}
489
490void __init pplus_find_bridges(void)
491{
492	struct pci_controller *hose;
493
494	hose = pcibios_alloc_controller();
495	if (!hose)
496		return;
497
498	hose->first_busno = 0;
499	hose->last_busno = 0xff;
500
501	hose->pci_mem_offset = PREP_ISA_MEM_BASE;
502	hose->io_base_virt = (void *)PREP_ISA_IO_BASE;
503
504	pci_init_resource(&hose->io_resource, PPLUS_PCI_IO_START,
505			  PPLUS_PCI_IO_END, IORESOURCE_IO, "PCI host bridge");
506	pci_init_resource(&hose->mem_resources[0], PPLUS_PROC_PCI_MEM_START,
507			  PPLUS_PROC_PCI_MEM_END, IORESOURCE_MEM,
508			  "PCI host bridge");
509
510	hose->io_space.start = PPLUS_PCI_IO_START;
511	hose->io_space.end = PPLUS_PCI_IO_END;
512	hose->mem_space.start = PPLUS_PCI_MEM_START;
513	hose->mem_space.end = PPLUS_PCI_MEM_END - HAWK_MPIC_SIZE;
514
515	if (hawk_init(hose, PPLUS_HAWK_PPC_REG_BASE, PPLUS_PROC_PCI_MEM_START,
516				PPLUS_PROC_PCI_MEM_END - HAWK_MPIC_SIZE,
517				PPLUS_PROC_PCI_IO_START, PPLUS_PROC_PCI_IO_END,
518				PPLUS_PROC_PCI_MEM_END - HAWK_MPIC_SIZE + 1)
519			!= 0) {
520		printk(KERN_CRIT "Could not initialize host bridge\n");
521
522	}
523
524	pplus_set_VIA_IDE_legacy();
525
526	hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
527
528	ppc_md.pcibios_fixup = pplus_pcibios_fixup;
529	ppc_md.pci_swizzle = common_swizzle;
530}
531
532static int pplus_show_cpuinfo(struct seq_file *m)
533{
534	seq_printf(m, "vendor\t\t: Motorola MCG\n");
535	seq_printf(m, "machine\t\t: %s\n", Motherboard_map_name);
536
537	return 0;
538}
539
540static void __init pplus_setup_arch(void)
541{
542	struct pci_controller *hose;
543
544	if (ppc_md.progress)
545		ppc_md.progress("pplus_setup_arch: enter", 0);
546
547	/* init to some ~sane value until calibrate_delay() runs */
548	loops_per_jiffy = 50000000;
549
550	if (ppc_md.progress)
551		ppc_md.progress("pplus_setup_arch: find_bridges", 0);
552
553	/* Setup PCI host bridge */
554	pplus_find_bridges();
555
556	hose = pci_bus_to_hose(0);
557	isa_io_base = (ulong) hose->io_base_virt;
558
559	if (ppc_md.progress)
560		ppc_md.progress("pplus_setup_arch: set_board_type", 0);
561
562	pplus_set_board_type();
563
564	/* Enable L2.  Assume we don't need to flush -- Cort */
565	*(unsigned char *)(PPLUS_L2_CONTROL_REG) |= 3;
566
567#ifdef CONFIG_BLK_DEV_INITRD
568	if (initrd_start)
569		ROOT_DEV = Root_RAM0;
570	else
571#endif
572#ifdef CONFIG_ROOT_NFS
573		ROOT_DEV = Root_NFS;
574#else
575		ROOT_DEV = Root_SDA2;
576#endif
577
578	printk(KERN_INFO "Motorola PowerPlus Platform\n");
579	printk(KERN_INFO
580	       "Port by MontaVista Software, Inc. (source@mvista.com)\n");
581
582#ifdef CONFIG_VGA_CONSOLE
583	/* remap the VGA memory */
584	vgacon_remap_base = (unsigned long)ioremap(PPLUS_ISA_MEM_BASE,
585						   0x08000000);
586	conswitchp = &vga_con;
587#endif
588#ifdef CONFIG_PPCBUG_NVRAM
589	/* Read in NVRAM data */
590	init_prep_nvram();
591
592	/* if no bootargs, look in NVRAM */
593	if (cmd_line[0] == '\0') {
594		char *bootargs;
595		bootargs = prep_nvram_get_var("bootargs");
596		if (bootargs != NULL) {
597			strcpy(cmd_line, bootargs);
598			/* again.. */
599			strcpy(saved_command_line, cmd_line);
600		}
601	}
602#endif
603	if (ppc_md.progress)
604		ppc_md.progress("pplus_setup_arch: exit", 0);
605}
606
607static void pplus_restart(char *cmd)
608{
609	unsigned long i = 10000;
610
611	local_irq_disable();
612
613	/* set VIA IDE controller into native mode */
614	pplus_set_VIA_IDE_native();
615
616	/* set exception prefix high - to the prom */
617	_nmask_and_or_msr(0, MSR_IP);
618
619	/* make sure bit 0 (reset) is a 0 */
620	outb(inb(0x92) & ~1L, 0x92);
621	/* signal a reset to system control port A - soft reset */
622	outb(inb(0x92) | 1, 0x92);
623
624	while (i != 0)
625		i++;
626	panic("restart failed\n");
627}
628
629static void pplus_halt(void)
630{
631	/* set exception prefix high - to the prom */
632	_nmask_and_or_msr(MSR_EE, MSR_IP);
633
634	/* make sure bit 0 (reset) is a 0 */
635	outb(inb(0x92) & ~1L, 0x92);
636	/* signal a reset to system control port A - soft reset */
637	outb(inb(0x92) | 1, 0x92);
638
639	while (1) ;
640	/*
641	 * Not reached
642	 */
643}
644
645static void pplus_power_off(void)
646{
647	pplus_halt();
648}
649
650static unsigned int pplus_irq_canonicalize(u_int irq)
651{
652	if (irq == 2)
653		return 9;
654	else
655		return irq;
656}
657
658static void __init pplus_init_IRQ(void)
659{
660	int i;
661
662	if (ppc_md.progress)
663		ppc_md.progress("init_irq: enter", 0);
664
665	OpenPIC_InitSenses = pplus_openpic_initsenses;
666	OpenPIC_NumInitSenses = sizeof(pplus_openpic_initsenses);
667
668	if (OpenPIC_Addr != NULL) {
669
670		openpic_set_sources(0, 16, OpenPIC_Addr + 0x10000);
671		openpic_init(NUM_8259_INTERRUPTS);
672		openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
673					i8259_irq);
674		ppc_md.get_irq = openpic_get_irq;
675	}
676
677	for (i = 0; i < NUM_8259_INTERRUPTS; i++)
678		irq_desc[i].handler = &i8259_pic;
679
680	i8259_init(0);
681
682	if (ppc_md.progress)
683		ppc_md.progress("init_irq: exit", 0);
684}
685
686#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
687/*
688 * IDE stuff.
689 */
690static int pplus_ide_default_irq(unsigned long base)
691{
692	switch (base) {
693	case 0x1f0:
694		return 14;
695	case 0x170:
696		return 15;
697	default:
698		return 0;
699	}
700}
701
702static unsigned long pplus_ide_default_io_base(int index)
703{
704	switch (index) {
705	case 0:
706		return 0x1f0;
707	case 1:
708		return 0x170;
709	default:
710		return 0;
711	}
712}
713
714static void __init
715pplus_ide_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
716			  unsigned long ctrl_port, int *irq)
717{
718	unsigned long reg = data_port;
719	int i;
720
721	for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
722		hw->io_ports[i] = reg;
723		reg += 1;
724	}
725
726	if (ctrl_port)
727		hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
728	else
729		hw->io_ports[IDE_CONTROL_OFFSET] =
730		    hw->io_ports[IDE_DATA_OFFSET] + 0x206;
731
732	if (irq != NULL)
733		*irq = pplus_ide_default_irq(data_port);
734}
735#endif
736
737#ifdef CONFIG_SMP
738/* PowerPlus (MTX) support */
739static int __init smp_pplus_probe(void)
740{
741	extern int mot_multi;
742
743	if (mot_multi) {
744		openpic_request_IPIs();
745		smp_hw_index[1] = 1;
746		return 2;
747	}
748
749	return 1;
750}
751
752static void __init smp_pplus_kick_cpu(int nr)
753{
754	*(unsigned long *)KERNELBASE = nr;
755	asm volatile ("dcbf 0,%0"::"r" (KERNELBASE):"memory");
756	printk(KERN_INFO "CPU1 reset, waiting\n");
757}
758
759static void __init smp_pplus_setup_cpu(int cpu_nr)
760{
761	if (OpenPIC_Addr)
762		do_openpic_setup_cpu();
763}
764
765static struct smp_ops_t pplus_smp_ops = {
766	smp_openpic_message_pass,
767	smp_pplus_probe,
768	smp_pplus_kick_cpu,
769	smp_pplus_setup_cpu,
770	.give_timebase = smp_generic_give_timebase,
771	.take_timebase = smp_generic_take_timebase,
772};
773#endif				/* CONFIG_SMP */
774
775#ifdef DUMP_DBATS
776static void print_dbat(int idx, u32 bat)
777{
778
779	char str[64];
780
781	sprintf(str, "DBAT%c%c = 0x%08x\n",
782		(char)((idx - DBAT0U) / 2) + '0', (idx & 1) ? 'L' : 'U', bat);
783	ppc_md.progress(str, 0);
784}
785
786#define DUMP_DBAT(x) \
787	do { \
788	u32 __temp = mfspr(x);\
789	print_dbat(x, __temp); \
790	} while (0)
791
792static void dump_dbats(void)
793{
794	if (ppc_md.progress) {
795		DUMP_DBAT(DBAT0U);
796		DUMP_DBAT(DBAT0L);
797		DUMP_DBAT(DBAT1U);
798		DUMP_DBAT(DBAT1L);
799		DUMP_DBAT(DBAT2U);
800		DUMP_DBAT(DBAT2L);
801		DUMP_DBAT(DBAT3U);
802		DUMP_DBAT(DBAT3L);
803	}
804}
805#endif
806
807static unsigned long __init pplus_find_end_of_memory(void)
808{
809	unsigned long total;
810
811	if (ppc_md.progress)
812		ppc_md.progress("pplus_find_end_of_memory", 0);
813
814#ifdef DUMP_DBATS
815	dump_dbats();
816#endif
817
818	total = hawk_get_mem_size(PPLUS_HAWK_SMC_BASE);
819	return (total);
820}
821
822static void __init pplus_map_io(void)
823{
824	io_block_mapping(PPLUS_ISA_IO_BASE, PPLUS_ISA_IO_BASE, 0x10000000,
825			 _PAGE_IO);
826	io_block_mapping(0xfef80000, 0xfef80000, 0x00080000, _PAGE_IO);
827}
828
829static void __init pplus_init2(void)
830{
831#ifdef CONFIG_NVRAM
832	request_region(PREP_NVRAM_AS0, 0x8, "nvram");
833#endif
834	request_region(0x20, 0x20, "pic1");
835	request_region(0xa0, 0x20, "pic2");
836	request_region(0x00, 0x20, "dma1");
837	request_region(0x40, 0x20, "timer");
838	request_region(0x80, 0x10, "dma page reg");
839	request_region(0xc0, 0x20, "dma2");
840}
841
842/*
843 * Set BAT 2 to access 0x8000000 so progress messages will work and set BAT 3
844 * to 0xf0000000 to access Falcon/Raven or Hawk registers
845 */
846static __inline__ void pplus_set_bat(void)
847{
848	/* wait for all outstanding memory accesses to complete */
849	mb();
850
851	/* setup DBATs */
852	mtspr(SPRN_DBAT2U, 0x80001ffe);
853	mtspr(SPRN_DBAT2L, 0x8000002a);
854	mtspr(SPRN_DBAT3U, 0xf0001ffe);
855	mtspr(SPRN_DBAT3L, 0xf000002a);
856
857	/* wait for updates */
858	mb();
859}
860
861void __init
862platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
863	      unsigned long r6, unsigned long r7)
864{
865	parse_bootinfo(find_bootinfo());
866
867	/* Map in board regs, etc. */
868	pplus_set_bat();
869
870	isa_io_base = PREP_ISA_IO_BASE;
871	isa_mem_base = PREP_ISA_MEM_BASE;
872	pci_dram_offset = PREP_PCI_DRAM_OFFSET;
873	ISA_DMA_THRESHOLD = 0x00ffffff;
874	DMA_MODE_READ = 0x44;
875	DMA_MODE_WRITE = 0x48;
876
877	ppc_md.setup_arch = pplus_setup_arch;
878	ppc_md.show_cpuinfo = pplus_show_cpuinfo;
879	ppc_md.irq_canonicalize = pplus_irq_canonicalize;
880	ppc_md.init_IRQ = pplus_init_IRQ;
881	/* this gets changed later on if we have an OpenPIC -- Cort */
882	ppc_md.get_irq = i8259_irq;
883	ppc_md.init = pplus_init2;
884
885	ppc_md.restart = pplus_restart;
886	ppc_md.power_off = pplus_power_off;
887	ppc_md.halt = pplus_halt;
888
889	TODC_INIT(TODC_TYPE_MK48T59, PREP_NVRAM_AS0, PREP_NVRAM_AS1,
890		  PREP_NVRAM_DATA, 8);
891
892	ppc_md.time_init = todc_time_init;
893	ppc_md.set_rtc_time = todc_set_rtc_time;
894	ppc_md.get_rtc_time = todc_get_rtc_time;
895	ppc_md.calibrate_decr = todc_calibrate_decr;
896	ppc_md.nvram_read_val = todc_m48txx_read_val;
897	ppc_md.nvram_write_val = todc_m48txx_write_val;
898
899	ppc_md.find_end_of_memory = pplus_find_end_of_memory;
900	ppc_md.setup_io_mappings = pplus_map_io;
901
902#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
903	ppc_ide_md.default_irq = pplus_ide_default_irq;
904	ppc_ide_md.default_io_base = pplus_ide_default_io_base;
905	ppc_ide_md.ide_init_hwif = pplus_ide_init_hwif_ports;
906#endif
907
908#ifdef CONFIG_SERIAL_TEXT_DEBUG
909	ppc_md.progress = gen550_progress;
910#endif				/* CONFIG_SERIAL_TEXT_DEBUG */
911#ifdef CONFIG_KGDB
912	ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
913#endif
914#ifdef CONFIG_SMP
915	ppc_md.smp_ops = &pplus_smp_ops;
916#endif				/* CONFIG_SMP */
917}