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/arch/ppc/platforms/pmac_sleep.S

https://bitbucket.org/evzijst/gittest
Assembly | 390 lines | 384 code | 6 blank | 0 comment | 3 complexity | c2bc355c0e9fb6f3f9d9cd9197dba1e5 MD5 | raw file
  1/*
  2 * This file contains sleep low-level functions for PowerBook G3.
  3 *    Copyright (C) 1999 Benjamin Herrenschmidt (benh@kernel.crashing.org)
  4 *    and Paul Mackerras (paulus@samba.org).
  5 *
  6 * This program is free software; you can redistribute it and/or
  7 * modify it under the terms of the GNU General Public License
  8 * as published by the Free Software Foundation; either version
  9 * 2 of the License, or (at your option) any later version.
 10 *
 11 */
 12
 13#include <linux/config.h>
 14#include <asm/processor.h>
 15#include <asm/page.h>
 16#include <asm/ppc_asm.h>
 17#include <asm/cputable.h>
 18#include <asm/cache.h>
 19#include <asm/thread_info.h>
 20#include <asm/offsets.h>
 21
 22#define MAGIC	0x4c617273	/* 'Lars' */
 23
 24/*
 25 * Structure for storing CPU registers on the stack.
 26 */
 27#define SL_SP		0
 28#define SL_PC		4
 29#define SL_MSR		8
 30#define SL_SDR1		0xc
 31#define SL_SPRG0	0x10	/* 4 sprg's */
 32#define SL_DBAT0	0x20
 33#define SL_IBAT0	0x28
 34#define SL_DBAT1	0x30
 35#define SL_IBAT1	0x38
 36#define SL_DBAT2	0x40
 37#define SL_IBAT2	0x48
 38#define SL_DBAT3	0x50
 39#define SL_IBAT3	0x58
 40#define SL_TB		0x60
 41#define SL_R2		0x68
 42#define SL_CR		0x6c
 43#define SL_R12		0x70	/* r12 to r31 */
 44#define SL_SIZE		(SL_R12 + 80)
 45
 46	.section .text
 47	.align	5
 48
 49#if defined(CONFIG_PMAC_PBOOK) || defined(CONFIG_CPU_FREQ_PMAC)
 50
 51/* This gets called by via-pmu.c late during the sleep process.
 52 * The PMU was already send the sleep command and will shut us down
 53 * soon. We need to save all that is needed and setup the wakeup
 54 * vector that will be called by the ROM on wakeup
 55 */
 56_GLOBAL(low_sleep_handler)
 57#ifndef CONFIG_6xx
 58	blr
 59#else
 60	mflr	r0
 61	stw	r0,4(r1)
 62	stwu	r1,-SL_SIZE(r1)
 63	mfcr	r0
 64	stw	r0,SL_CR(r1)
 65	stw	r2,SL_R2(r1)
 66	stmw	r12,SL_R12(r1)
 67
 68	/* Save MSR & SDR1 */
 69	mfmsr	r4
 70	stw	r4,SL_MSR(r1)
 71	mfsdr1	r4
 72	stw	r4,SL_SDR1(r1)
 73
 74	/* Get a stable timebase and save it */
 751:	mftbu	r4
 76	stw	r4,SL_TB(r1)
 77	mftb	r5
 78	stw	r5,SL_TB+4(r1)
 79	mftbu	r3
 80	cmpw	r3,r4
 81	bne	1b
 82
 83	/* Save SPRGs */
 84	mfsprg	r4,0
 85	stw	r4,SL_SPRG0(r1)
 86	mfsprg	r4,1
 87	stw	r4,SL_SPRG0+4(r1)
 88	mfsprg	r4,2
 89	stw	r4,SL_SPRG0+8(r1)
 90	mfsprg	r4,3
 91	stw	r4,SL_SPRG0+12(r1)
 92
 93	/* Save BATs */
 94	mfdbatu	r4,0
 95	stw	r4,SL_DBAT0(r1)
 96	mfdbatl	r4,0
 97	stw	r4,SL_DBAT0+4(r1)
 98	mfdbatu	r4,1
 99	stw	r4,SL_DBAT1(r1)
100	mfdbatl	r4,1
101	stw	r4,SL_DBAT1+4(r1)
102	mfdbatu	r4,2
103	stw	r4,SL_DBAT2(r1)
104	mfdbatl	r4,2
105	stw	r4,SL_DBAT2+4(r1)
106	mfdbatu	r4,3
107	stw	r4,SL_DBAT3(r1)
108	mfdbatl	r4,3
109	stw	r4,SL_DBAT3+4(r1)
110	mfibatu	r4,0
111	stw	r4,SL_IBAT0(r1)
112	mfibatl	r4,0
113	stw	r4,SL_IBAT0+4(r1)
114	mfibatu	r4,1
115	stw	r4,SL_IBAT1(r1)
116	mfibatl	r4,1
117	stw	r4,SL_IBAT1+4(r1)
118	mfibatu	r4,2
119	stw	r4,SL_IBAT2(r1)
120	mfibatl	r4,2
121	stw	r4,SL_IBAT2+4(r1)
122	mfibatu	r4,3
123	stw	r4,SL_IBAT3(r1)
124	mfibatl	r4,3
125	stw	r4,SL_IBAT3+4(r1)
126
127	/* Backup various CPU config stuffs */
128	bl	__save_cpu_setup
129
130	/* The ROM can wake us up via 2 different vectors:
131	 *  - On wallstreet & lombard, we must write a magic
132	 *    value 'Lars' at address 4 and a pointer to a
133	 *    memory location containing the PC to resume from
134	 *    at address 0.
135	 *  - On Core99, we must store the wakeup vector at
136	 *    address 0x80 and eventually it's parameters
137	 *    at address 0x84. I've have some trouble with those
138	 *    parameters however and I no longer use them.
139	 */
140	lis	r5,grackle_wake_up@ha
141	addi	r5,r5,grackle_wake_up@l
142	tophys(r5,r5)
143	stw	r5,SL_PC(r1)
144	lis	r4,KERNELBASE@h
145	tophys(r5,r1)
146	addi	r5,r5,SL_PC
147	lis	r6,MAGIC@ha
148	addi	r6,r6,MAGIC@l
149	stw	r5,0(r4)
150	stw	r6,4(r4)
151	/* Setup stuffs at 0x80-0x84 for Core99 */
152	lis	r3,core99_wake_up@ha
153	addi	r3,r3,core99_wake_up@l
154	tophys(r3,r3)
155	stw	r3,0x80(r4)
156	stw	r5,0x84(r4)
157	/* Store a pointer to our backup storage into
158	 * a kernel global
159	 */
160	lis r3,sleep_storage@ha
161	addi r3,r3,sleep_storage@l
162	stw r5,0(r3)
163
164	/* Flush & disable all caches */
165	bl	flush_disable_caches
166
167	/* Turn off data relocation. */
168	mfmsr	r3		/* Save MSR in r7 */
169	rlwinm	r3,r3,0,28,26	/* Turn off DR bit */
170	sync
171	mtmsr	r3
172	isync
173
174BEGIN_FTR_SECTION
175	/* Flush any pending L2 data prefetches to work around HW bug */
176	sync
177	lis	r3,0xfff0
178	lwz	r0,0(r3)	/* perform cache-inhibited load to ROM */
179	sync			/* (caches are disabled at this point) */
180END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
181
182/*
183 * Set the HID0 and MSR for sleep.
184 */
185	mfspr	r2,SPRN_HID0
186	rlwinm	r2,r2,0,10,7	/* clear doze, nap */
187	oris	r2,r2,HID0_SLEEP@h
188	sync
189	isync
190	mtspr	SPRN_HID0,r2
191	sync
192
193/* This loop puts us back to sleep in case we have a spurrious
194 * wakeup so that the host bridge properly stays asleep. The
195 * CPU will be turned off, either after a known time (about 1
196 * second) on wallstreet & lombard, or as soon as the CPU enters
197 * SLEEP mode on core99
198 */
199	mfmsr	r2
200	oris	r2,r2,MSR_POW@h
2011:	sync
202	mtmsr	r2
203	isync
204	b	1b
205
206/*
207 * Here is the resume code.
208 */
209
210
211/*
212 * Core99 machines resume here
213 * r4 has the physical address of SL_PC(sp) (unused)
214 */
215_GLOBAL(core99_wake_up)
216	/* Make sure HID0 no longer contains any sleep bit and that data cache
217	 * is disabled
218	 */
219	mfspr	r3,SPRN_HID0
220	rlwinm	r3,r3,0,11,7		/* clear SLEEP, NAP, DOZE bits */
221	rlwinm	3,r3,0,18,15		/* clear DCE, ICE */
222	mtspr	SPRN_HID0,r3
223	sync
224	isync
225
226	/* sanitize MSR */
227	mfmsr	r3
228	ori	r3,r3,MSR_EE|MSR_IP
229	xori	r3,r3,MSR_EE|MSR_IP
230	sync
231	isync
232	mtmsr	r3
233	sync
234	isync
235
236	/* Recover sleep storage */
237	lis	r3,sleep_storage@ha
238	addi	r3,r3,sleep_storage@l
239	tophys(r3,r3)
240	lwz	r1,0(r3)
241
242	/* Pass thru to older resume code ... */
243/*
244 * Here is the resume code for older machines.
245 * r1 has the physical address of SL_PC(sp).
246 */
247
248grackle_wake_up:
249
250	/* Restore the kernel's segment registers before
251	 * we do any r1 memory access as we are not sure they
252	 * are in a sane state above the first 256Mb region
253	 */
254	li	r0,16		/* load up segment register values */
255	mtctr	r0		/* for context 0 */
256	lis	r3,0x2000	/* Ku = 1, VSID = 0 */
257	li	r4,0
2583:	mtsrin	r3,r4
259	addi	r3,r3,0x111	/* increment VSID */
260	addis	r4,r4,0x1000	/* address of next segment */
261	bdnz	3b
262	sync
263	isync
264
265	subi	r1,r1,SL_PC
266
267	/* Restore various CPU config stuffs */
268	bl	__restore_cpu_setup
269
270	/* Invalidate & enable L1 cache, we don't care about
271	 * whatever the ROM may have tried to write to memory
272	 */
273	bl	__inval_enable_L1
274
275	/* Restore the BATs, and SDR1.  Then we can turn on the MMU. */
276	lwz	r4,SL_SDR1(r1)
277	mtsdr1	r4
278	lwz	r4,SL_SPRG0(r1)
279	mtsprg	0,r4
280	lwz	r4,SL_SPRG0+4(r1)
281	mtsprg	1,r4
282	lwz	r4,SL_SPRG0+8(r1)
283	mtsprg	2,r4
284	lwz	r4,SL_SPRG0+12(r1)
285	mtsprg	3,r4
286
287	lwz	r4,SL_DBAT0(r1)
288	mtdbatu	0,r4
289	lwz	r4,SL_DBAT0+4(r1)
290	mtdbatl	0,r4
291	lwz	r4,SL_DBAT1(r1)
292	mtdbatu	1,r4
293	lwz	r4,SL_DBAT1+4(r1)
294	mtdbatl	1,r4
295	lwz	r4,SL_DBAT2(r1)
296	mtdbatu	2,r4
297	lwz	r4,SL_DBAT2+4(r1)
298	mtdbatl	2,r4
299	lwz	r4,SL_DBAT3(r1)
300	mtdbatu	3,r4
301	lwz	r4,SL_DBAT3+4(r1)
302	mtdbatl	3,r4
303	lwz	r4,SL_IBAT0(r1)
304	mtibatu	0,r4
305	lwz	r4,SL_IBAT0+4(r1)
306	mtibatl	0,r4
307	lwz	r4,SL_IBAT1(r1)
308	mtibatu	1,r4
309	lwz	r4,SL_IBAT1+4(r1)
310	mtibatl	1,r4
311	lwz	r4,SL_IBAT2(r1)
312	mtibatu	2,r4
313	lwz	r4,SL_IBAT2+4(r1)
314	mtibatl	2,r4
315	lwz	r4,SL_IBAT3(r1)
316	mtibatu	3,r4
317	lwz	r4,SL_IBAT3+4(r1)
318	mtibatl	3,r4
319
320BEGIN_FTR_SECTION
321	li	r4,0
322	mtspr	SPRN_DBAT4U,r4
323	mtspr	SPRN_DBAT4L,r4
324	mtspr	SPRN_DBAT5U,r4
325	mtspr	SPRN_DBAT5L,r4
326	mtspr	SPRN_DBAT6U,r4
327	mtspr	SPRN_DBAT6L,r4
328	mtspr	SPRN_DBAT7U,r4
329	mtspr	SPRN_DBAT7L,r4
330	mtspr	SPRN_IBAT4U,r4
331	mtspr	SPRN_IBAT4L,r4
332	mtspr	SPRN_IBAT5U,r4
333	mtspr	SPRN_IBAT5L,r4
334	mtspr	SPRN_IBAT6U,r4
335	mtspr	SPRN_IBAT6L,r4
336	mtspr	SPRN_IBAT7U,r4
337	mtspr	SPRN_IBAT7L,r4
338END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
339
340	/* Flush all TLBs */
341	lis	r4,0x1000
3421:	addic.	r4,r4,-0x1000
343	tlbie	r4
344	blt	1b
345	sync
346
347	/* restore the MSR and turn on the MMU */
348	lwz	r3,SL_MSR(r1)
349	bl	turn_on_mmu
350
351	/* get back the stack pointer */
352	tovirt(r1,r1)
353
354	/* Restore TB */
355	li	r3,0
356	mttbl	r3
357	lwz	r3,SL_TB(r1)
358	lwz	r4,SL_TB+4(r1)
359	mttbu	r3
360	mttbl	r4
361
362	/* Restore the callee-saved registers and return */
363	lwz	r0,SL_CR(r1)
364	mtcr	r0
365	lwz	r2,SL_R2(r1)
366	lmw	r12,SL_R12(r1)
367	addi	r1,r1,SL_SIZE
368	lwz	r0,4(r1)
369	mtlr	r0
370	blr
371
372turn_on_mmu:
373	mflr	r4
374	tovirt(r4,r4)
375	mtsrr0	r4
376	mtsrr1	r3
377	sync
378	isync
379	rfi
380
381#endif /* defined(CONFIG_PMAC_PBOOK) || defined(CONFIG_CPU_FREQ) */
382
383	.section .data
384	.balign	L1_CACHE_LINE_SIZE
385sleep_storage:
386	.long 0
387	.balign	L1_CACHE_LINE_SIZE, 0
388
389#endif /* CONFIG_6xx */
390	.section .text