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/arch/ppc/platforms/katana.h

https://bitbucket.org/evzijst/gittest
C Header | 255 lines | 178 code | 42 blank | 35 comment | 1 complexity | db640f4124e407b97664275b2eb55d0e MD5 | raw file
  1/*
  2 * arch/ppc/platforms/katana.h
  3 *
  4 * Definitions for Artesyn Katana750i/3750 board.
  5 *
  6 * Author: Tim Montgomery <timm@artesyncp.com>
  7 * Maintained by: Mark A. Greer <mgreer@mvista.com>
  8 *
  9 * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
 10 * Based on code done by Mark A. Greer <mgreer@mvista.com>
 11 *
 12 * This program is free software; you can redistribute it and/or modify it
 13 * under the terms of the GNU General Public License as published by the
 14 * Free Software Foundation; either version 2 of the License, or (at your
 15 * option) any later version.
 16 */
 17
 18/*
 19 * The MV64360 has 2 PCI buses each with 1 window from the CPU bus to
 20 * PCI I/O space and 4 windows from the CPU bus to PCI MEM space.
 21 * We'll only use one PCI MEM window on each PCI bus.
 22 *
 23 * This is the CPU physical memory map (windows must be at least 64 KB and start
 24 * on a boundary that is a multiple of the window size):
 25 *
 26 *    0xff800000-0xffffffff      - Boot window
 27 *    0xf8400000-0xf843ffff      - Internal SRAM
 28 *    0xf8200000-0xf83fffff      - CPLD
 29 *    0xf8100000-0xf810ffff      - MV64360 Registers (CONFIG_MV64X60_NEW_BASE)
 30 *    0xf8000000-0xf80fffff      - Socketed FLASH
 31 *    0xe0000000-0xefffffff      - Soldered FLASH
 32 *    0xc0000000-0xc3ffffff      - PCI I/O (second hose)
 33 *    0x80000000-0xbfffffff      - PCI MEM (second hose)
 34 */
 35
 36#ifndef __PPC_PLATFORMS_KATANA_H
 37#define __PPC_PLATFORMS_KATANA_H
 38
 39/* CPU Physical Memory Map setup. */
 40#define KATANA_BOOT_WINDOW_BASE			0xff800000
 41#define KATANA_BOOT_WINDOW_SIZE			0x00800000 /* 8 MB */
 42#define KATANA_INTERNAL_SRAM_BASE		0xf8400000
 43#define KATANA_CPLD_BASE			0xf8200000
 44#define KATANA_CPLD_SIZE			0x00200000 /* 2 MB */
 45#define KATANA_SOCKET_BASE			0xf8000000
 46#define KATANA_SOCKETED_FLASH_SIZE		0x00100000 /* 1 MB */
 47#define KATANA_SOLDERED_FLASH_BASE		0xe0000000
 48#define KATANA_SOLDERED_FLASH_SIZE		0x10000000 /* 256 MB */
 49
 50#define KATANA_PCI1_MEM_START_PROC_ADDR         0x80000000
 51#define KATANA_PCI1_MEM_START_PCI_HI_ADDR       0x00000000
 52#define KATANA_PCI1_MEM_START_PCI_LO_ADDR       0x80000000
 53#define KATANA_PCI1_MEM_SIZE                    0x40000000 /* 1 GB */
 54#define KATANA_PCI1_IO_START_PROC_ADDR          0xc0000000
 55#define KATANA_PCI1_IO_START_PCI_ADDR           0x00000000
 56#define KATANA_PCI1_IO_SIZE                     0x04000000 /* 64 MB */
 57
 58/* Board-specific IRQ info */
 59#define  KATANA_PCI_INTA_IRQ_3750		64+8
 60#define  KATANA_PCI_INTB_IRQ_3750		64+9
 61#define  KATANA_PCI_INTC_IRQ_3750		64+10
 62
 63#define  KATANA_PCI_INTA_IRQ_750i		64+8
 64#define  KATANA_PCI_INTB_IRQ_750i		64+9
 65#define  KATANA_PCI_INTC_IRQ_750i		64+10
 66#define  KATANA_PCI_INTD_IRQ_750i		64+14
 67
 68#define KATANA_CPLD_RST_EVENT			0x00000000
 69#define KATANA_CPLD_RST_CMD			0x00001000
 70#define KATANA_CPLD_PCI_ERR_INT_EN		0x00002000
 71#define KATANA_CPLD_PCI_ERR_INT_PEND		0x00003000
 72#define KATANA_CPLD_PRODUCT_ID			0x00004000
 73#define KATANA_CPLD_EREADY			0x00005000
 74
 75#define KATANA_CPLD_HARDWARE_VER		0x00007000
 76#define KATANA_CPLD_PLD_VER			0x00008000
 77#define KATANA_CPLD_BD_CFG_0			0x00009000
 78#define KATANA_CPLD_BD_CFG_1			0x0000a000
 79#define KATANA_CPLD_BD_CFG_3			0x0000c000
 80#define KATANA_CPLD_LED				0x0000d000
 81#define KATANA_CPLD_RESET_OUT			0x0000e000
 82
 83#define KATANA_CPLD_RST_EVENT_INITACT		0x80
 84#define KATANA_CPLD_RST_EVENT_SW		0x40
 85#define KATANA_CPLD_RST_EVENT_WD		0x20
 86#define KATANA_CPLD_RST_EVENT_COPS		0x10
 87#define KATANA_CPLD_RST_EVENT_COPH		0x08
 88#define KATANA_CPLD_RST_EVENT_CPCI		0x02
 89#define KATANA_CPLD_RST_EVENT_FP		0x01
 90
 91#define KATANA_CPLD_RST_CMD_SCL			0x80
 92#define KATANA_CPLD_RST_CMD_SDA			0x40
 93#define KATANA_CPLD_RST_CMD_I2C			0x10
 94#define KATANA_CPLD_RST_CMD_FR			0x08
 95#define KATANA_CPLD_RST_CMD_SR			0x04
 96#define KATANA_CPLD_RST_CMD_HR			0x01
 97
 98#define KATANA_CPLD_BD_CFG_0_SYSCLK_MASK	0xc0
 99#define KATANA_CPLD_BD_CFG_0_SYSCLK_200		0x00
100#define KATANA_CPLD_BD_CFG_0_SYSCLK_166		0x80
101#define KATANA_CPLD_BD_CFG_0_SYSCLK_133		0xc0
102#define KATANA_CPLD_BD_CFG_0_SYSCLK_100		0x40
103
104#define KATANA_CPLD_BD_CFG_1_FL_BANK_MASK	0x03
105#define KATANA_CPLD_BD_CFG_1_FL_BANK_16MB	0x00
106#define KATANA_CPLD_BD_CFG_1_FL_BANK_32MB	0x01
107#define KATANA_CPLD_BD_CFG_1_FL_BANK_64MB	0x02
108#define KATANA_CPLD_BD_CFG_1_FL_BANK_128MB	0x03
109
110#define KATANA_CPLD_BD_CFG_1_FL_NUM_BANKS_MASK	0x04
111#define KATANA_CPLD_BD_CFG_1_FL_NUM_BANKS_ONE	0x00
112#define KATANA_CPLD_BD_CFG_1_FL_NUM_BANKS_TWO	0x04
113
114#define KATANA_CPLD_BD_CFG_3_MONARCH		0x04
115
116#define KATANA_CPLD_RESET_OUT_PORTSEL		0x80
117#define KATANA_CPLD_RESET_OUT_WD		0x20
118#define KATANA_CPLD_RESET_OUT_COPH		0x08
119#define KATANA_CPLD_RESET_OUT_PCI_RST_PCI	0x02
120#define KATANA_CPLD_RESET_OUT_PCI_RST_FP	0x01
121
122#define KATANA_MBOX_RESET_REQUEST		0xC83A
123#define KATANA_MBOX_RESET_ACK			0xE430
124#define KATANA_MBOX_RESET_DONE			0x32E5
125
126#define HSL_PLD_BASE				0x00010000
127#define HSL_PLD_J4SGA_REG_OFF			0
128#define HSL_PLD_J4GA_REG_OFF			1
129#define HSL_PLD_J2GA_REG_OFF			2
130#define HSL_PLD_HOT_SWAP_OFF			6
131#define HSL_PLD_HOT_SWAP_LED_BIT		0x1
132#define GA_MASK					0x1f
133#define HSL_PLD_SIZE				0x1000
134#define K3750_GPP_GEO_ADDR_PINS			0xf8000000
135#define K3750_GPP_GEO_ADDR_SHIFT		27
136
137#define K3750_GPP_EVENT_PROC_0			(1 << 21)
138#define K3750_GPP_EVENT_PROC_1_2		(1 << 2)
139
140#define PCI_VENDOR_ID_ARTESYN			0x1223
141#define PCI_DEVICE_ID_KATANA_3750_PROC0		0x0041
142#define PCI_DEVICE_ID_KATANA_3750_PROC1		0x0042
143#define PCI_DEVICE_ID_KATANA_3750_PROC2		0x0043
144
145#define COPROC_MEM_FUNCTION			0
146#define COPROC_MEM_BAR				0
147#define COPROC_REGS_FUNCTION			0
148#define COPROC_REGS_BAR				4
149#define COPROC_FLASH_FUNCTION			2
150#define COPROC_FLASH_BAR			4
151
152#define KATANA_IPMB_LOCAL_I2C_ADDR		0x08
153
154#define	KATANA_DEFAULT_BAUD			9600
155#define	KATANA_MPSC_CLK_SRC			8	  /* TCLK */
156
157#define	KATANA_MTD_MONITOR_SIZE			(1 << 20) /* 1 MB */
158
159#define	KATANA_ETH0_PHY_ADDR			12
160#define	KATANA_ETH1_PHY_ADDR			11
161#define	KATANA_ETH2_PHY_ADDR			4
162
163#define KATANA_PRODUCT_ID_3750			0x01
164#define KATANA_PRODUCT_ID_750i			0x02
165#define KATANA_PRODUCT_ID_752i			0x04
166
167#define KATANA_ETH_TX_QUEUE_SIZE		800
168#define KATANA_ETH_RX_QUEUE_SIZE		400
169
170#define	KATANA_ETH_PORT_CONFIG_VALUE			\
171	ETH_UNICAST_NORMAL_MODE			|	\
172	ETH_DEFAULT_RX_QUEUE_0			|	\
173	ETH_DEFAULT_RX_ARP_QUEUE_0		|	\
174	ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP		|	\
175	ETH_RECEIVE_BC_IF_IP			|	\
176	ETH_RECEIVE_BC_IF_ARP			|	\
177	ETH_CAPTURE_TCP_FRAMES_DIS		|	\
178	ETH_CAPTURE_UDP_FRAMES_DIS		|	\
179	ETH_DEFAULT_RX_TCP_QUEUE_0		|	\
180	ETH_DEFAULT_RX_UDP_QUEUE_0		|	\
181	ETH_DEFAULT_RX_BPDU_QUEUE_0
182
183#define	KATANA_ETH_PORT_CONFIG_EXTEND_VALUE		\
184	ETH_SPAN_BPDU_PACKETS_AS_NORMAL		|	\
185	ETH_PARTITION_DISABLE
186
187#define	GT_ETH_IPG_INT_RX(value)			\
188	((value & 0x3fff) << 8)
189
190#define	KATANA_ETH_PORT_SDMA_CONFIG_VALUE		\
191	ETH_RX_BURST_SIZE_4_64BIT		|	\
192	GT_ETH_IPG_INT_RX(0)			|	\
193	ETH_TX_BURST_SIZE_4_64BIT
194
195#define	KATANA_ETH_PORT_SERIAL_CONTROL_VALUE		\
196	ETH_FORCE_LINK_PASS			|	\
197	ETH_ENABLE_AUTO_NEG_FOR_DUPLX		|	\
198	ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL	|	\
199	ETH_ADV_SYMMETRIC_FLOW_CTRL		|	\
200	ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX	|	\
201	ETH_FORCE_BP_MODE_NO_JAM		|	\
202	BIT9					|	\
203	ETH_DO_NOT_FORCE_LINK_FAIL		|	\
204	ETH_RETRANSMIT_16_ATTEMPTS		|	\
205	ETH_ENABLE_AUTO_NEG_SPEED_GMII		|	\
206	ETH_DTE_ADV_0				|	\
207	ETH_DISABLE_AUTO_NEG_BYPASS		|	\
208	ETH_AUTO_NEG_NO_CHANGE			|	\
209	ETH_MAX_RX_PACKET_9700BYTE		|	\
210	ETH_CLR_EXT_LOOPBACK			|	\
211	ETH_SET_FULL_DUPLEX_MODE		|	\
212	ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
213
214#ifndef __ASSEMBLY__
215
216typedef enum {
217	KATANA_ID_3750,
218	KATANA_ID_750I,
219	KATANA_ID_752I,
220	KATANA_ID_MAX
221} katana_id_t;
222
223#endif
224
225static inline u32
226katana_bus_freq(void __iomem *cpld_base)
227{
228	u8 bd_cfg_0;
229
230	bd_cfg_0 = in_8(cpld_base + KATANA_CPLD_BD_CFG_0);
231
232	switch (bd_cfg_0 & KATANA_CPLD_BD_CFG_0_SYSCLK_MASK) {
233	case KATANA_CPLD_BD_CFG_0_SYSCLK_200:
234		return 200000000;
235		break;
236
237	case KATANA_CPLD_BD_CFG_0_SYSCLK_166:
238		return 166666666;
239		break;
240
241	case KATANA_CPLD_BD_CFG_0_SYSCLK_133:
242		return 133333333;
243		break;
244
245	case KATANA_CPLD_BD_CFG_0_SYSCLK_100:
246		return 100000000;
247		break;
248
249	default:
250		return 133333333;
251		break;
252	}
253}
254
255#endif	/* __PPC_PLATFORMS_KATANA_H */